summaryrefslogtreecommitdiff
path: root/src/mainboard/system76/lemp9/devicetree.cb
blob: 9cdeeabc28733aebf9e657ef2055543ea0fab355 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
chip soc/intel/cannonlake
	# Lock Down
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

# ACPI (soc/intel/cannonlake/acpi.c)
	# Disable s0ix
	register "s0ix_enable" = "0"

	# PM Timer Enabled
	register "PmTimerDisabled" = "0"

	# Disable DPTF
	register "dptf_enable" = "0"

# CPU (soc/intel/cannonlake/cpu.c)
	# Power limit
	register "power_limits_config" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 25,
	}"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"

	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
	register "SaGv" = "SaGv_Enabled"
	#register "enable_c6dram" = "1"

# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
	# SATA
	register "SataMode" = "Sata_AHCI"
	register "SataSalpSupport" = "0"

	register "SataPortsEnable[0]" = "0"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsEnable[2]" = "1"
	register "SataPortsEnable[3]" = "0"
	register "SataPortsEnable[4]" = "0"
	register "SataPortsEnable[5]" = "0"
	register "SataPortsEnable[6]" = "0"
	register "SataPortsEnable[7]" = "0"

	register "SataPortsDevSlp[0]" = "0"
	register "SataPortsDevSlp[1]" = "0"
	register "SataPortsDevSlp[2]" = "0"
	register "SataPortsDevSlp[3]" = "0"
	register "SataPortsDevSlp[4]" = "0"
	register "SataPortsDevSlp[5]" = "0"
	register "SataPortsDevSlp[6]" = "0"
	register "SataPortsDevSlp[7]" = "0"

	# Audio
	register "PchHdaDspEnable" = "0"
	register "PchHdaAudioLinkHda" = "1"
	register "PchHdaAudioLinkDmic0" = "1"
	register "PchHdaAudioLinkDmic1" = "1"
	register "PchHdaAudioLinkSsp0" = "0"
	register "PchHdaAudioLinkSsp1" = "0"
	register "PchHdaAudioLinkSsp2" = "0"
	register "PchHdaAudioLinkSndw1" = "0"
	register "PchHdaAudioLinkSndw2" = "0"
	register "PchHdaAudioLinkSndw3" = "0"
	register "PchHdaAudioLinkSndw4" = "0"

	# USB
	register "SsicPortEnable" = "0"

	# USB2
	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"		# Type-C port 2
	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 3
	register "usb2_ports[3]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[4]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[5]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
	register "usb2_ports[7]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[8]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
	register "usb2_ports[10]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[11]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[12]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[13]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[14]" = "USB2_PORT_EMPTY"			# NC
	register "usb2_ports[15]" = "USB2_PORT_EMPTY"			# NC

	# USB3
	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 1
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-C port 2
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 3
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# NC
	register "usb3_ports[4]" = "USB3_PORT_EMPTY"			# NC
	register "usb3_ports[5]" = "USB3_PORT_EMPTY"			# HSIO used by PCIe root port #6
	register "usb3_ports[6]" = "USB3_PORT_EMPTY"			# NC
	register "usb3_ports[7]" = "USB3_PORT_EMPTY"			# NC
	register "usb3_ports[8]" = "USB3_PORT_EMPTY"			# NC
	register "usb3_ports[9]" = "USB3_PORT_EMPTY"			# NC


	# PCI Express root port #6 x1, Clock 3 (card reader)
	register "PcieRpEnable[5]" = "1"
	register "PcieRpLtrEnable[5]" = "1"
	register "PcieClkSrcUsage[3]" = "5"
	register "PcieClkSrcClkReq[3]" = "3"

	# PCI Express root port #8 x1, Clock 2 (WLAN)
	register "PcieRpEnable[7]" = "1"
	register "PcieRpLtrEnable[7]" = "1"
	register "PcieClkSrcUsage[2]" = "7"
	register "PcieClkSrcClkReq[2]" = "2"

	# PCI Express root port #9 x4, Clock 4 (SSD2)
	register "PcieRpEnable[8]" = "1"
	register "PcieRpLtrEnable[8]" = "1"
	register "PcieClkSrcUsage[4]" = "8"
	register "PcieClkSrcClkReq[4]" = "4"

	# PCI Express root port #13 x4, Clock 5 (SSD1)
	register "PcieRpEnable[12]" = "1"
	register "PcieRpLtrEnable[12]" = "1"
	register "PcieClkSrcUsage[5]" = "12"
	register "PcieClkSrcClkReq[5]" = "5"

	# Misc
	register "AcousticNoiseMitigation" = "1"
	#register "dmipwroptimize" = "1"
	#register "satapwroptimize" = "1"

	# Power
	register "PchPmSlpS3MinAssert" = "3"		# 50ms
	register "PchPmSlpS4MinAssert" = "1"		# 1s
	register "PchPmSlpSusMinAssert" = "2"		# 500ms
	register "PchPmSlpAMinAssert" = "4"		# 2s

	# Thermal
	register "tcc_offset" = "12"

# LPC (soc/intel/cannonlake/lpc.c)
	# LPC configuration from lspci -s 1f.0 -xxx
	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
	register "gen1_dec" = "0x000c0081"
	# Address 0x88: Decode 0x68 - 0x6F (PMC)
	register "gen2_dec" = "0x00040069"
	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
	register "gen3_dec" = "0x00fc0E01"
	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
	register "gen4_dec" = "0x00fc0F01"

# PMC (soc/intel/cannonlake/pmc.c)
	# Enable deep Sx states
	register "deep_s3_enable_ac" = "0"
	register "deep_s3_enable_dc" = "0"
	register "deep_s5_enable_ac" = "1"
	register "deep_s5_enable_dc" = "1"
	register "deep_sx_config" = "DSX_EN_WAKE_PIN"

# PM Util (soc/intel/cannonlake/pmutil.c)
	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
	register "gpe0_dw0" = "PMC_GPP_C"
	register "gpe0_dw1" = "PMC_GPP_D"
	register "gpe0_dw2" = "PMC_GPP_E"

# Actual device tree
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 off     # SA Thermal device
			register "Device4Enable" = "0"
		end
		device pci 12.0 on  end # Thermal Subsystem
		device pci 12.5 off end # UFS SCS
		device pci 12.6 off end # GSPI #2
		device pci 13.0 off end # Integrated Sensor Hub
		device pci 14.0 on  end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		#chip drivers/intel/wifi
		#	register "wake" = "PME_B0_EN_BIT"
			device pci 14.3 on  end # CNVi wifi
		#end
		device pci 14.5 off end # SDCard
		device pci 15.0 off end # I2C #0
		device pci 15.1 off end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 off end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off     # Management Engine Interface 3
			register "Heci3Enabled" = "0"
		end
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 on  end # SATA
		device pci 19.0 off end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 off end # eMMC
		device pci 1c.0 off end # PCI Express Port 1
		device pci 1c.1 off end # PCI Express Port 2
		device pci 1c.2 off end # PCI Express Port 3
		device pci 1c.3 off end # PCI Express Port 4
		device pci 1c.4 off end # PCI Express Port 5
		device pci 1c.5 on  end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 on  end # PCI Express Port 8
		device pci 1d.0 on  end # PCI Express Port 9
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1d.4 on  end # PCI Express Port 13
		device pci 1d.5 off end # PCI Express Port 14
		device pci 1d.6 off end # PCI Express Port 15
		device pci 1d.7 off end # PCI Express Port 16
		device pci 1e.0 off end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on  end # LPC Interface
		device pci 1f.1 off end # P2SB
		device pci 1f.2 off end # Power Management Controller
		device pci 1f.3 on  end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 off end # GbE
	end
end