blob: 3779de28495f5ce1e42910ec9146292ebdd2667c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
default CONFIG_ROM_PAYLOAD = 1
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/ati/ragexl
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds
##
## ROMSTRAP table for CK804
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
##
## Include the secondary Configuration files
##
config chip.h
include devicetree.cb
|
