summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan/s2895/Config.lb
blob: 6b418290172d99ac9c16855956963126004a1f9c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM     = 1

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

arch i386 end 


##
## Build the objects we have code for in this directory.
##

driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o

if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM

	if CONFIG_USE_INIT	
		makerule ./auto.o
		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
		end
	else
		makerule ./auto.inc
        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
		end
	end

else
	##
	## Romcc output
	##
	makerule ./failover.E
        	depends "$(MAINBOARD)/failover.c ./romcc"
	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
	end

	makerule ./failover.inc
        	depends "$(MAINBOARD)/failover.c ./romcc"
	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
	end

	makerule ./auto.E
        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
	end

	makerule ./auto.inc
        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
	end

end

##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/entry16.inc
        ldscript /cpu/x86/16bit/entry16.lds
end

mainboardinit cpu/x86/32bit/entry32.inc

if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end

        if CONFIG_USE_INIT
                ldscript /cpu/amd/car/cache_as_ram.lds
        end
end


##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE 
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
else
	mainboardinit cpu/x86/32bit/reset32.inc 
	ldscript /cpu/x86/32bit/reset32.lds 
end

if USE_DCACHE_RAM
else
	### Should this be in the northbridge code?
	mainboardinit arch/i386/lib/cpu_reset.inc
end

##
## Include an id string (For safe flashing)
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds

##
## ROMSTRAP table for CK804
##
if USE_FALLBACK_IMAGE
	mainboardinit southbridge/nvidia/ck804/romstrap.inc
	ldscript /southbridge/nvidia/ck804/romstrap.lds
end



if USE_DCACHE_RAM
	##
	## Setup Cache-As-Ram
	##
	mainboardinit cpu/amd/car/cache_as_ram.inc
end

###
### This is the early phase of linuxBIOS startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds
	if USE_DCACHE_RAM
	else
	        mainboardinit ./failover.inc
	end
end

##
## Setup RAM
##
if USE_DCACHE_RAM

	if CONFIG_USE_INIT
		initobject auto.o
	else
		mainboardinit ./auto.inc
	end

else
	# ROMCC
	mainboardinit cpu/x86/fpu/enable_fpu.inc
	mainboardinit cpu/x86/mmx/enable_mmx.inc
	mainboardinit cpu/x86/sse/enable_sse.inc
	mainboardinit ./auto.inc
	mainboardinit cpu/x86/sse/disable_sse.inc
	mainboardinit cpu/x86/mmx/disable_mmx.inc

end

##
## Include the secondary Configuration files 
##
if CONFIG_CHIP_NAME
	config chip.h
end

# sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex
        device apic_cluster 0 on
                chip cpu/amd/socket_940
                        device apic 0 on end
                end
        end
	device pci_domain 0 on
		chip northbridge/amd/amdk8 #mc0
			device pci 18.0 on 
				#  devices on link 0, link 0 == LDT 0 
			        chip southbridge/nvidia/ck804 
					device pci 0.0 on end   # HT
                			device pci 1.0 on # LPC
                	                        chip superio/smsc/lpc47b397
                        	                        device pnp 2e.0 on #  Floppy
                                	                         io 0x60 = 0x3f0
                                        	                irq 0x70 = 6
                                                	        drq 0x74 = 2
	                                                end
        	                                        device pnp 2e.3 off #  Parallel Port
                	                                         io 0x60 = 0x378
                        	                                irq 0x70 = 7
                                	                end
                                        	        device pnp 2e.4 on #  Com1
                                                	        io 0x60 = 0x3f8
	                                                        irq 0x70 = 4
        	                                        end
                	                                device pnp 2e.5 off #  Com2
                        	                                io 0x60 = 0x2f8
                                	                        irq 0x70 = 3
                                        	        end
	                                                device pnp 2e.7 on #  Keyboard
        	                                                io 0x60 = 0x60
                	                                        io 0x62 = 0x64
                        	                                irq 0x70 = 1
                                	                        irq 0x72 = 12
                                        	        end
	                                                device pnp 2e.8 on # HW Monitor
        	                                                io 0x60 = 0x290
                                                                chip drivers/generic/generic # LM95221 CPU temp
                                                                        device i2c 2b on end
                                                                end
                                                                chip drivers/generic/generic # EMCT03
                                                                        device i2c 54 on end
                                                                end
							end
	                                                device	pnp 2e.a on #  RT
        	                                                io 0x60 = 0x400
							end
                        	                end
					end
			                device pci 1.1 on # SM 0
                                                chip drivers/generic/generic #dimm 0-0-0
                                                        device i2c 50 on end  
                                                end              
                                                chip drivers/generic/generic #dimm 0-0-1
                                                        device i2c 51 on end
                                                end     
                                                chip drivers/generic/generic #dimm 0-1-0
                                                        device i2c 52 on end
                                                end             
                                                chip drivers/generic/generic #dimm 0-1-1
                                                        device i2c 53 on end
                                                end              
                                                chip drivers/generic/generic #dimm 1-0-0
                                                        device i2c 54 on end
                                                end     
                                                chip drivers/generic/generic #dimm 1-0-1
                                                        device i2c 55 on end
                                                end     
                                                chip drivers/generic/generic #dimm 1-1-0
                                                        device i2c 56 on end
                                                end     
                                                chip drivers/generic/generic #dimm 1-1-1
                                                        device i2c 57 on end
                                                end 
					end # SM
                                        device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
#                                                chip drivers/generic/generic #PCIXA Slot1
#                                                        device i2c 50 on end
#                                                end
#                                                chip drivers/generic/generic #PCIXB Slot1
#                                                        device i2c 51 on end
#                                                end     
#                                                chip drivers/generic/generic #PCIXB Slot2
#                                                        device i2c 52 on end
#                                                end             
#                                                chip drivers/generic/generic #PCI Slot1
#                                                        device i2c 53 on end
#                                                end              
#                                                chip drivers/generic/generic #Master CK804 PCI-E
#                                                        device i2c 54 on end
#                                                end     
#                                                chip drivers/generic/generic #Slave CK804 PCI-E
#                                                        device i2c 55 on end
#                                                end             
                                                chip drivers/generic/generic #MAC EEPROM
                                                        device i2c 51 on end
                                                end 

                                        end # SM 
	                		device pci 2.0 on end # USB 1.1
        	        		device pci 2.1 on end # USB 2
	                		device pci 4.0 on end # ACI
        	        		device pci 4.1 off end # MCI
                			device pci 6.0 on end # IDE
	                		device pci 7.0 on end # SATA 1
        	        		device pci 8.0 on end # SATA 0
                			device pci 9.0 on end # PCI
	                		device pci a.0 on end # NIC
        	       			device pci b.0 off end # PCI E 3
                			device pci c.0 off end # PCI E 2
                			device pci d.0 off end # PCI E 1
                			device pci e.0 on end # PCI E 0
	                                register "ide0_enable" = "1"
        	                        register "ide1_enable" = "1"
                	                register "sata0_enable" = "1"
                        	        register "sata1_enable" = "1"
#					register "nic_rom_address" = "0xfff80000" # 64k
#					register "raid_rom_address" = "0xfff90000"
					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
					register "mac_eeprom_addr" = "0x51"
				end
			end #  device pci 18.0 
			device pci 18.0 on end # Link 1
			device pci 18.0 on
                        #  devices on link 2, link 2 == LDT 2
	                        chip southbridge/amd/amd8131
        	                        # the on/off keyword is mandatory
                	                device pci 0.0 on end
                        	        device pci 0.1 on end
					device pci 1.0 on 
                                                chip drivers/pci/onboard
                                                        device pci 6.0 on end # lsi scsi
                                                        device pci 6.1 on end
                                                end
					end
					device pci 1.1 on end
                	        end
			end # device pci 18.0
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
		end # mc0
		
		chip northbridge/amd/amdk8
                	device pci 19.0 on #  northbridge 
                        	#  devices on link 0, link 0 == LDT 0 
                        	chip southbridge/nvidia/ck804 
                                	device pci 0.0 on end   # HT
                                	device pci 1.0 on end   # LPC
                                	device pci 1.1 off end # SM
                                	device pci 2.0 off end # USB 1.1
                                	device pci 2.1 off end # USB 2
                                	device pci 4.0 off end # ACI
                                	device pci 4.1 off end # MCI
                                	device pci 6.0 off end # IDE
                                	device pci 7.0 off end # SATA 1
                                	device pci 8.0 off end # SATA 0
                                	device pci 9.0 off end # PCI
                                	device pci a.0 on end # NIC
                                	device pci b.0 off end # PCI E 3
                                	device pci c.0 off end # PCI E 2
                                	device pci d.0 off end # PCI E 1
                                	device pci e.0 on end # PCI E 0
#					register "nic_rom_address" = "0xfff80000" # 64k
                                        register "mac_eeprom_smbus" = "3"
                                        register "mac_eeprom_addr" = "0x51"
                        	end
                	end #  device pci 19.0 
			
			device pci 19.0 on end
			device pci 19.0 on end
			device pci 19.1 on end
			device pci 19.2 on end
			device pci 19.3 on end
		end
	end # PCI domain
	
#       chip drivers/generic/debug 
#               device pnp 0.0 off end # chip name
#                device pnp 0.1 off end # pci_regs_all
#                device pnp 0.2 off end # mem
#                device pnp 0.3 off end # cpuid
#                device pnp 0.4 on end # smbus_regs_all
#                device pnp 0.5 off end # dual core msr
#                device pnp 0.6 off end # cache size
#                device pnp 0.7 off end # tsc
#       end  
end #root_complex