summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdk8/coherent_ht.c
blob: 1b0feb123addc892f0f9801eb32621268739952c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
/* coherent hypertransport initialization for AMD64
 *
 * written by Stefan Reinauer <stepan@openbios.org>
 * (c) 2003-2004 by SuSE Linux AG
 *
 * (c) 2004 Tyan Computer
 *  2004.12 yhlu added support to create routing table dynamically.
 *          it also support 8 ways too. (8 ways ladder or 8 ways crossbar)
 *
 * This code is licensed under GPL.
 */

/*
 * This algorithm assumes a grid configuration as follows:
 *
 * nodes :  1    2    4    6    8
 * org.  :  1x1  2x1  2x2  2x3  2x4
 Ladder:
			CPU7-------------CPU6
			|                |
			|                |
			|                |
			|                |
			|                |
			|                |
			CPU5-------------CPU4
			|                |
			|                |
			|                |
			|                |
			|                |
			|                |
			CPU3-------------CPU2
			|                |
			|                |
			|                |
			|                |
			|                |
			|                |
			CPU1-------------CPU0
 CROSS_BAR_47_56:
			CPU7-------------CPU6
			|  \____    ___/ |
			|       \  /     |
			|        \/      |
			|        /\      |
			|       /  \     |
			|  ____/    \___ |
			CPU5             CPU4
			|                |
			|                |
			|                |
			|                |
			|                |
			|                |
			CPU3-------------CPU2
			|                |
			|                |
			|                |
			|                |
			|                |
			|                |
			CPU1-------------CPU0
 */

#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
#include <stdlib.h>
#include "arch/romcc_io.h"

#include "amdk8.h"

#define enable_bsp_routing()	enable_routing(0)

#define NODE_HT(x) PCI_DEV(0,24+x,0)
#define NODE_MP(x) PCI_DEV(0,24+x,1)
#define NODE_MC(x) PCI_DEV(0,24+x,3)

#define DEFAULT 0x00010101	/* default row entry */


#ifndef CROSS_BAR_47_56
	#define CROSS_BAR_47_56 0
#endif

#ifndef TRY_HIGH_FIRST
	#define TRY_HIGH_FIRST 0
#endif

#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
	#define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
#endif

#ifndef K8_HT_CHECK_PENDING_LINK
	#if CONFIG_MAX_PHYSICAL_CPUS >= 4
		#define K8_HT_CHECK_PENDING_LINK 1
	#else
		#define K8_HT_CHECK_PENDING_LINK 0
	#endif
#endif

#ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
	#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
#endif

#ifndef CONFIG_ENABLE_APIC_EXT_ID
	#define CONFIG_ENABLE_APIC_EXT_ID 0
#endif


static inline void print_linkn (const char *strval, uint8_t byteval)
{
	printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}

static void disable_probes(void)
{
	/* disable read/write/fill probes for uniprocessor setup
	 * they don't make sense if only one cpu is available
	 */

	/* Hypetransport Transaction Control Register
	 * F0:0x68
	 * [ 0: 0] Disable read byte probe
	 *         0 = Probes issues
	 *         1 = Probes not issued
	 * [ 1: 1] Disable Read Doubleword probe
	 *         0 = Probes issued
	 *         1 = Probes not issued
	 * [ 2: 2] Disable write byte probes
	 *         0 = Probes issued
	 *         1 = Probes not issued
	 * [ 3: 3] Disable Write Doubleword Probes
	 *         0 = Probes issued
	 *         1 = Probes not issued.
	 * [10:10] Disable Fill Probe
	 *         0 = Probes issued for cache fills
	 *         1 = Probes not issued for cache fills.
	 */

	u32 val;

	print_spew("Disabling read/write/fill probes for UP... ");

	val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
	val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
		HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
		HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
	pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);

	print_spew("done.\n");

}

#if 0
static void enable_apic_ext_id(u8 node)
{
#if CONFIG_ENABLE_APIC_EXT_ID==1
#warning "FIXME Is the right place to enable apic ext id here?"

      u32 val;

	val = pci_read_config32(NODE_HT(node), 0x68);
	val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
	pci_write_config32(NODE_HT(node), 0x68, val);
#endif
}
#endif

static void enable_routing(u8 node)
{
	u32 val;

	/* HT Initialization Control Register
	 * F0:0x6C
	 * [ 0: 0] Routing Table Disable
	 *         0 = Packets are routed according to routing tables
	 *         1 = Packets are routed according to the default link field
	 * [ 1: 1] Request Disable (BSP should clear this)
	 *         0 = Request packets may be generated
	 *         1 = Request packets may not be generated.
	 * [ 3: 2] Default Link (Read-only)
	 *         00 = LDT0
	 *         01 = LDT1
	 *         10 = LDT2
	 *         11 = CPU on same node
	 * [ 4: 4] Cold Reset
	 *         - Scratch bit cleared by a cold reset
	 * [ 5: 5] BIOS Reset Detect
	 *         - Scratch bit cleared by a cold reset
	 * [ 6: 6] INIT Detect
	 *         - Scratch bit cleared by a warm or cold reset not by an INIT
	 *
	 */

	/* Enable routing table */
	print_spew("Enabling routing table for node ");
	print_spew_hex8(node);

	val=pci_read_config32(NODE_HT(node), 0x6c);
	val &= ~((1<<1)|(1<<0));
	pci_write_config32(NODE_HT(node), 0x6c, val);

	print_spew(" done.\n");
}

static void fill_row(u8 node, u8 row, u32 value)
{
	pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
}

#if CONFIG_MAX_PHYSICAL_CPUS > 1
static u8 link_to_register(int ldt)
{
	/*
	 * [ 0: 3] Request Route
	 *     [0] Route to this node
	 *     [1] Route to Link 0
	 *     [2] Route to Link 1
	 *     [3] Route to Link 2
	 */

	if (ldt&0x08) return 0x40;
	if (ldt&0x04) return 0x20;
	if (ldt&0x02) return 0x00;

	/* we should never get here */
	print_spew("Unknown Link\n");
	return 0;
}

static u32 get_row(u8 node, u8 row)
{
	return pci_read_config32(NODE_HT(node), 0x40+(row<<2));
}

static int link_connection(u8 src, u8 dest)
{
	return get_row(src, dest) & 0x0f;
}

static void rename_temp_node(u8 node)
{
	uint32_t val;

	print_spew("Renaming current temporary node to ");
	print_spew_hex8(node);

	val=pci_read_config32(NODE_HT(7), 0x60);
	val &= (~7);  /* clear low bits. */
	val |= node;  /* new node        */
	pci_write_config32(NODE_HT(7), 0x60, val);

	print_spew(" done.\n");
}

static int verify_connection(u8 dest)
{
	/* See if we have a valid connection to dest */
	u32 val;

	/* Verify that the coherent hypertransport link is
	 * established and actually working by reading the
	 * remode node's vendor/device id
	 */
	val = pci_read_config32(NODE_HT(dest),0);
	if(val != 0x11001022)
		return 0;

	return 1;
}

static uint16_t read_freq_cap(device_t dev, uint8_t pos)
{
	/* Handle bugs in valid hypertransport frequency reporting */
	uint16_t freq_cap;
	uint32_t id;

	freq_cap = pci_read_config16(dev, pos);
	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */

#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
    #if CONFIG_K8_REV_F_SUPPORT == 0
	if (!is_cpu_pre_e0())
    #endif
	{
		return freq_cap;
	}
#endif

	id = pci_read_config32(dev, 0);

	/* AMD K8 Unsupported 1Ghz? */
	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
		freq_cap &= ~(1 << HT_FREQ_1000Mhz);
	}

	return freq_cap;
}

static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2)
{
	static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
	static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
	uint16_t freq_cap1, freq_cap2;
	uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
	uint8_t freq, old_freq;
	int needs_reset;
	/* Set link width and frequency */

	/* Initially assume everything is already optimized and I don't need a reset */
	needs_reset = 0;

	/* Get the frequency capabilities */
	freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP);
	freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);

	/* Calculate the highest possible frequency */
	freq = log2(freq_cap1 & freq_cap2);

	/* See if I am changing the link freqency */
	old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
	old_freq &= 0x0f;
	needs_reset |= old_freq != freq;
	old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ);
	old_freq &= 0x0f;
	needs_reset |= old_freq != freq;

	/* Set the Calulcated link frequency */
	pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq);
	pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq);

	/* Get the width capabilities */
	width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH);
	width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH);

	/* Calculate node1's input width */
	ln_width1 = link_width_to_pow2[width_cap1 & 7];
	ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
	if (ln_width1 > ln_width2) {
		ln_width1 = ln_width2;
	}
	width = pow2_to_link_width[ln_width1];
	/* Calculate node1's output width */
	ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
	ln_width2 = link_width_to_pow2[width_cap2 & 7];
	if (ln_width1 > ln_width2) {
		ln_width1 = ln_width2;
	}
	width |= pow2_to_link_width[ln_width1] << 4;

	/* See if I am changing node1's width */
	old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
	old_width &= 0x77;
	needs_reset |= old_width != width;

	/* Set node1's widths */
	pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);

	// * Calculate node2's width */
	width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);

	/* See if I am changing node2's width */
	old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
	old_width &= 0x77;
	needs_reset |= old_width != width;

	/* Set node2's widths */
	pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);

	return needs_reset;
}

static uint8_t get_linkn_first(uint8_t byte)
{
	if(byte & 0x02) { byte = 0; }
	else if(byte & 0x04) { byte = 1; }
	else if(byte & 0x08) { byte = 2; }
	return byte;
}

#if TRY_HIGH_FIRST == 1
static uint8_t get_linkn_last(uint8_t byte)
{
	if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
	if(byte & 0x04) { byte &= 0x0f; byte |= 0x10;  }
	if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
	return byte>>4;
}
#endif

#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
static uint8_t get_linkn_last_count(uint8_t byte)
{
	byte &= 0x0f;
	if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
	if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
	if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
	return byte>>4;
}
#endif

static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
{
	uint8_t linkn;
	uint32_t val;
	val = 1;
	for(linkn = 0; linkn<3; linkn++) {
		uint8_t regpos;
		uint32_t reg;
		regpos = 0x98 + 0x20 * linkn;
		reg = pci_read_config32(NODE_HT(source), regpos);
		if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
		val |= 1<<(linkn+1);
	}
	val <<= 16;
	val |= 0x0101;
	fill_row(source,row, val);
}

static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
{
	uint32_t val;
	uint32_t val_s;
	val = 1<<(linkn+1);
	val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/

	if(((source &1)!=(dest &1))
#if CROSS_BAR_47_56
		&& ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
					       //(6,5) (7,4) should be here
#endif
	){
		val |= (1<<16);
	} else {
		/*for CROSS_BAR_47_56  47, 56, should be here too
			and for 47, 56, 57, 75, 46, 64 we need to substract another link to
				6,  7,  6,  6,  7,  7
		*/
		val_s = get_row(temp, source);
		val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
	}

	fill_row(temp,dest, val );
}

#if CROSS_BAR_47_56
static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
	uint32_t val;
	val = get_row(source, dest);
	val -= link_connection(source, kickout)<<16;
	fill_row(source, dest, val);
}

static void opt_broadcast_rt_group(const u8 *conn, int num) {
	int i;

	for(i=0; i<num; i+=3) {
		opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
	}
}
static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
	uint32_t val;
	val = get_row(source, dest);
	val += link_connection(source, kickout)<<16;
	fill_row(source, dest, val);
}

static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
	int i;

	for(i=0; i<num; i+=3) {
		opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
	}
}
#endif

static void setup_row_direct(u8 source, u8 dest, u8 linkn){
	setup_row_direct_x(source, source, dest, linkn);
}

static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
	setup_row_direct_x(7, source, dest, linkn);
}

static void setup_temp_row(u8 source, u8 dest)
{
	/* copy val from (source, dest) to (source,7) */
	fill_row(source,7,get_row(source,dest));
}

#if 0
static void clear_temp_row(u8 source)
{
	fill_row(source, 7, DEFAULT);
}
#endif

static void setup_remote_node(u8 node)
{
	static const uint8_t pci_reg[] = {
		0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
		0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
		0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
		0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
		0xc4, 0xcc, 0xd4, 0xdc,
		0xc0, 0xc8, 0xd0, 0xd8,
		0xe0, 0xe4, 0xe8, 0xec,
	};
	int i;

	print_spew("setup_remote_node: ");

	/* copy the default resource map from node 0 */
	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
		uint32_t value;
		uint8_t reg;
		reg = pci_reg[i];
		value = pci_read_config32(NODE_MP(0), reg);
		pci_write_config32(NODE_MP(7), reg, value);

	}
	print_spew("done\n");
}

#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/


#if CONFIG_MAX_PHYSICAL_CPUS > 2
#if !CROSS_BAR_47_56
static void setup_row_indirect_x(u8 temp, u8 source, u8 dest)
#else
static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
#endif
{
	/*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
	uint32_t val_s;
	uint32_t val;
#if !CROSS_BAR_47_56
	u8 gateway;
	u8 diff;
	if(source<dest) {
		gateway = source + 2;
	} else {
		gateway = source - 2;
	}
#endif
	val_s = get_row(temp, source);
	val = get_row(temp, gateway);

	val &= 0xffff;
	val_s >>= 16;
	val_s &= 0xfe;

#if !CROSS_BAR_47_56
	diff = ((source&1)!=(dest &1));
#endif

	if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
		val_s -= val &  0xff;
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
		uint8_t byte;
		/* Some node have two links left
		 * don't worry we only have (2, (3 as source need to handle
		 */
		byte = val_s;
		byte = get_linkn_last_count(byte);
		if((byte>>2)>1) { /* make sure not the corner*/
			if(source<dest) {
				val_s-=link_connection(temp, source-2); /* -down*/
			} else {
#if CROSS_BAR_47_56
				#if 0
				if(source==7) {
					val_s-=link_connection(temp, 6);  // for 7,2 via 5
				} else if (source==6){
					val_s-=link_connection(temp, 7);  // for 6,3 via 4
				} else
				#endif
				if (source < gateway) { // for 5, 4 via 7
				  	val_s-=link_connection(temp, source-2);
				} else
#endif
					val_s-=link_connection(temp, source+2); /* -up*/
			}
		}
#endif
		val &= 0xff;
		val |= (val_s<<8);
	}

	if(diff) { /* cross rung?*/
		val |= (1<<16);
	}
	else {
		val_s = get_row(temp, source);
		val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
	}

	fill_row(temp, dest, val);

}

#if !CROSS_BAR_47_56
static void setup_row_indirect(u8 source, u8 dest)
{
	setup_row_indirect_x(source, source, dest);
}
#else
static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
{
	setup_row_indirect_x(source, source, dest, gateway, diff);
}
#endif

static void setup_row_indirect_group(const u8 *conn, int num)
{
	int i;

#if !CROSS_BAR_47_56
	for(i=0; i<num; i+=2) {
		setup_row_indirect(conn[i], conn[i+1]);
#else
	for(i=0; i<num; i+=4) {
		setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif

	}
}

#if !CROSS_BAR_47_56
static void setup_remote_row_indirect(u8 source, u8 dest)
{
	setup_row_indirect_x(7, source, dest);
}
#else
static void setup_remote_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
{
	setup_row_indirect_x(7, source, dest, gateway, diff);
}
#endif

static void setup_remote_row_indirect_group(const u8 *conn, int num)
{
	int i;

#if !CROSS_BAR_47_56
	for(i=0; i<num; i+=2) {
		setup_remote_row_indirect(conn[i], conn[i+1]);
#else
	for(i=0; i<num; i+=4) {
		setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif
	}
}

#endif /*CONFIG_MAX_PHYSICAL_CPUS > 2*/


static void setup_uniprocessor(void)
{
	print_spew("Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1
	unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
	if (tmp>0) return;
#endif
	disable_probes();
}

#if CONFIG_MAX_PHYSICAL_CPUS > 2
static int optimize_connection_group(const u8 *opt_conn, int num) {
	int needs_reset = 0;
	int i;
	for(i=0; i<num; i+=2) {
		needs_reset = optimize_connection(
			NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
			NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
	}
	return needs_reset;
}
#endif

#if CONFIG_MAX_PHYSICAL_CPUS > 1
static unsigned setup_smp2(void)
{
	unsigned nodes;
	u8 byte;
	uint32_t val;
	nodes = 2;

	setup_row_local(0, 0); /* it will update the broadcast RT*/

	val = get_row(0,0);
	byte = (val>>16) & 0xfe;
	if(byte<0x2) { /* no coherent connection so get out.*/
		nodes = 1;
		return nodes;
	}

	/* Setup and check a temporary connection to node 1 */
#if TRY_HIGH_FIRST == 1
	byte = get_linkn_last(byte); /* Max Link to node1 */
#else
	byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/
#endif
	print_linkn("(0,1) link=", byte);
	setup_row_direct(0,1, byte);
	setup_temp_row(0, 1);

	verify_connection(7);

	/* We found 2 nodes so far */
	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /*get default link on node7 to node0*/
	print_linkn("(1,0) link=", byte);
	setup_row_local(7,1);
	setup_remote_row_direct(1, 0, byte);

#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
	val = get_row(7,1);
	byte = (val>>16) & 0xfe;
	byte = get_linkn_last_count(byte);
	if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
		val = get_row(0,0);
		byte = (val>>16) & 0xfe;
#if TRY_HIGH_FIRST == 1
		byte = get_linkn_first(byte); /* Min link to Node1 */
#else
		byte = get_linkn_last(byte);  /* Max link to Node1*/
#endif
		print_linkn("\t-->(0,1) link=", byte);
		setup_row_direct(0,1, byte);
		setup_temp_row(0, 1);

		verify_connection(7);

		/* We found 2 nodes so far */
		val = pci_read_config32(NODE_HT(7), 0x6c);
		byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
		print_linkn("\t-->(1,0) link=", byte);
		setup_row_local(7,1);
		setup_remote_row_direct(1, 0, byte);
	}
#endif

	setup_remote_node(1);  /* Setup the regs on the remote node */
	rename_temp_node(1);    /* Rename Node 7 to Node 1  */
	enable_routing(1);      /* Enable routing on Node 1 */
#if 0
	/*don't need and it is done by clear_dead_links */
	clear_temp_row(0);
#endif

	return nodes;
}
#endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */

#if CONFIG_MAX_PHYSICAL_CPUS > 2

static unsigned setup_smp4(void)
{
	unsigned nodes;
	u8 byte;
	uint32_t val;

	nodes=4;

	/* Setup and check temporary connection from Node 0 to Node 2 */
	val = get_row(0,0);
	byte = ((val>>16) & 0xfe) - link_connection(0,1);
	byte = get_linkn_last_count(byte);

	if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
		nodes = 2;
		return nodes;
	}

	byte &= 3; /* bit [3,2] is count-1*/
	print_linkn("(0,2) link=", byte);
	setup_row_direct(0, 2, byte);  /*(0,2) direct link done*/

	/* We found 3 nodes so far. Now setup a temporary
	* connection from node 0 to node 3 via node 1
	*/
	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
	/* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/
	val = get_row(1,1);
	byte = ((val>>16) & 0xfe) - link_connection(1,0);
	byte = get_linkn_first(byte);
	print_linkn("(1,3) link=", byte);
	setup_row_direct(1,3,byte);  /* (1, 3) direct link done*/

	/* We found 4 nodes so far. Now setup all nodes for 4p */
	// We need to make sure 0,2 and 1,3 link is set already
#if !CROSS_BAR_47_56
	static const u8 conn4_1[] = {
		0,3,
		1,2,
	};
#else
	static const u8 conn4_1[] = {
		0,3,2,1,
		1,2,3,1,
	};
#endif

	setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));

	setup_temp_row(0,2);
	verify_connection(7);
	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
	print_linkn("(2,0) link=", byte);

	setup_row_local(7,2);
	setup_remote_row_direct(2, 0, byte);  /* node 2 to node 0 direct link done */
	setup_remote_node(2);  /* Setup the regs on the remote node */

	rename_temp_node(2);    /* Rename Node 7 to Node 2  */
	enable_routing(2);      /* Enable routing on Node 2 */

	setup_temp_row(0,1);
	setup_temp_row(1,3);
	verify_connection(7);

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
	print_linkn("(3,1) link=", byte);

	setup_row_local(7,3);
	setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
	setup_remote_node(3);  /* Setup the regs on the remote node */

	/* We need to init link between 2, and 3 direct link */
	val = get_row(2,2);
	byte = ((val>>16) & 0xfe) - link_connection(2,0);
	byte = get_linkn_last_count(byte);
	print_linkn("(2,3) link=", byte & 3);

	setup_row_direct(2,3, byte & 0x3);
	setup_temp_row(0,2);
	setup_temp_row(2,3);
	verify_connection(7); /* to 3*/

#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
	/* We need to find out which link is to node3 */
	if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
		val = get_row(7,3);
		if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
			val = get_row(2,2);
			byte = ((val>>16) & 0xfe) - link_connection(2,0);
			byte = get_linkn_first(byte);
			print_linkn("\t-->(2,3) link=", byte);
			setup_row_direct(2,3,byte);
			setup_temp_row(2,3);
			verify_connection(7); /* to 3*/
		}
	}
#endif

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
	print_linkn("(3,2) link=", byte);
	setup_remote_row_direct(3,2, byte);

#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
	/* set link from 3 to 5 before enable it*/
	val = get_row(7,3);
	byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
	byte = get_linkn_last_count(byte);
	if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
		byte &= 3; /*bit [3,2] is count-2*/
		print_linkn("(3,5) link=", byte);
		setup_remote_row_direct(3, 5, byte);
	}

	val = get_row(2,2);
	byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
	byte = get_linkn_last_count(byte);

	if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
		byte &= 3; /* bit [3,2] is count-2*/
		print_linkn("(2,4) link=", byte);
		setup_row_direct(2, 4, byte);
	}
#endif

	//Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
#if !CROSS_BAR_47_56
	static const u8 conn4_3[] = {
		3,0,
	};
#else
	static const u8 conn4_3[] = {
		3,0,1,1,
	};
#endif
	setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));

/* ready to enable RT for Node 3 */
	rename_temp_node(3);
	enable_routing(3);      /* enable routing on node 3 (temp.) */

	// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
#if !CROSS_BAR_47_56
	static const u8 conn4_2[] = {
		2,1,
	};
#else
	static const u8 conn4_2[] = {
		2,1,0,1,
	};
#endif
	setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));

#if 0
	/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
	/* it will be done by clear_dead_links */
	clear_temp_row(0);
	clear_temp_row(1);
#endif

	return nodes;

}

#endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */

#if CONFIG_MAX_PHYSICAL_CPUS > 4

static unsigned setup_smp6(void)
{
	unsigned nodes;
	u8 byte;
	uint32_t val;

	nodes=6;

	/* Setup and check temporary connection from Node 0 to Node 4  through 2*/
	val = get_row(2,2);
	byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
	byte = get_linkn_last_count(byte);

	if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
		nodes = 4;
		return nodes;
	}

	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3*/
	/* set link from 3 to 5 before enable it*/
	val = get_row(3,3);
	byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
	byte = get_linkn_last_count(byte);
	if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
		nodes = 4;
		return nodes;
	}

	/* We found 6 nodes so far. Now setup all nodes for 6p */
#warning "FIXME we need to find out the correct gateway for 6p"
	static const u8 conn6_1[] = {
#if !CROSS_BAR_47_56
		0, 4,
		0, 5,
		1, 4,
		1, 5,
		2, 5,
		3, 4,
#else
		0, 4, 2, 0,
		0, 5, 2, 1,
		1, 4, 3, 1,
		1, 5, 3, 0,
		2, 5, 3, 0,
		3, 4, 2, 0,
#endif
	};

	setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));

	for(byte=0; byte<4; byte+=2) {
		setup_temp_row(byte,byte+2);
	}
	verify_connection(7);
	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
	print_linkn("(4,2) link=", byte);

	setup_row_local(7,4);
	setup_remote_row_direct(4, 2, byte);
	setup_remote_node(4);  /* Setup the regs on the remote node */

	/* Set indirect connection to 0, to 3 */
	//we only need to set 4,0 here
	static const u8 conn6_2[] = {
#if !CROSS_BAR_47_56
		4, 0,
#else
		4, 0, 2, 0,
#endif
	};

	setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));

	rename_temp_node(4);
	enable_routing(4);

	setup_temp_row(0,1);
	for(byte=0; byte<4; byte+=2) {
		setup_temp_row(byte+1,byte+3);
	}
	verify_connection(7);

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
	print_linkn("(5,3) link=", byte);
	setup_row_local(7,5);
	setup_remote_row_direct(5, 3, byte);
	setup_remote_node(5);  /* Setup the regs on the remote node */

#if !CROSS_BAR_47_56
	/* We need to init link between 4, and 5 direct link */
	val = get_row(4,4);
	byte = ((val>>16) & 0xfe) - link_connection(4,2);
	byte = get_linkn_last_count(byte);
	print_linkn("(4,5) link=", byte & 3);

	setup_row_direct(4,5, byte & 0x3);
	setup_temp_row(0,2);
	setup_temp_row(2,4);
	setup_temp_row(4,5);
	verify_connection(7); /* to 5*/

#if CONFIG_MAX_PHYSICAL_CPUS > 6
	/* We need to find out which link is to node5 */

	if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
		val = get_row(7,5);
		if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
			val = get_row(4,4);
			byte = ((val>>16) & 0xfe) - link_connection(4,2);
			byte = get_linkn_first(byte);
			print_linkn("\t-->(4,5) link=", byte);
			setup_row_direct(4,5,byte);
			setup_temp_row(4,5);
			verify_connection(7); /* to 5*/
		}
	}
#endif

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
	print_linkn("(5,4) link=", byte);
	setup_remote_row_direct(5,4, byte);

	//init 5, 7 here
	val = get_row(7,5);
	byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
	byte = get_linkn_last_count(byte);
	if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
		byte &= 3; /*bit [3,2] is count-2*/
		print_linkn("(5,7) link=", byte);
		setup_remote_row_direct(5, 7, byte);
	}

	//init 4,6 here
	val = get_row(4,4);
	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
	byte = get_linkn_last_count(byte);

	if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
		byte &= 3; /* bit [3,2] is count-2*/
		print_linkn("(4,6) link=", byte);
		setup_row_direct(4, 6, byte);
	}

#endif

	//We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
	/* Set indirect connection to 0, to 3  for indirect we will use clockwise routing */
	static const u8 conn6_3[] = {
#if !CROSS_BAR_47_56
		5, 0,
#else
		5, 0, 3, 0,
#endif
	};

	setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));

/* ready to enable RT for 5 */
	rename_temp_node(5);
	enable_routing(5);      /* enable routing on node 5 (temp.) */

	static const u8 conn6_4[] = {
#if !CROSS_BAR_47_56
		4, 1,
		4, 3,

		5, 2,
		5, 1,

#else
		4, 1, 2, 0,
		4, 3, 2, 0,
		4, 5, 2, 0,

		5, 2, 3, 0,
		5, 1, 3, 0,
		5, 4, 3, 0,

#endif
	};

	setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));

#if 0
	/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
	 * It will be done by clear_dead_links
	 */
	for(byte=0; byte<4; byte++) {
		clear_temp_row(byte);
	}
#endif

	return nodes;

}

#endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */

#if CONFIG_MAX_PHYSICAL_CPUS > 6

static unsigned setup_smp8(void)
{
	unsigned nodes;
	u8 byte;
	uint32_t val;

	nodes=8;

	/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
	val = get_row(4,4);
#if CROSS_BAR_47_56
	byte = ((val>>16) & 0xfe) - link_connection(4,2);
#else
	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
	byte = get_linkn_last_count(byte); /* Max link to 6*/
	if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
		nodes = 6;
		return nodes;
	}
#endif

#if CROSS_BAR_47_56
	byte = get_linkn_last_count(byte); /* Max link to 6*/
	if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
		nodes = 6;
		return nodes;
	}
#if TRY_HIGH_FIRST == 1
	byte = ((val>>16) & 0xfe) - link_connection(4,2);
	byte = get_linkn_first(byte);  /*Min link to 6*/
#else
	byte &= 3; /* bit [3,2] is count-1 or 2*/
#endif
	print_linkn("(4,6) link=", byte);
	setup_row_direct(4, 6, byte);
#endif

#if !CROSS_BAR_47_56
	/* Setup and check temporary connection from Node 0 to Node 7  through 1, 3, 5*/
	val = get_row(5,5);
	byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
	byte = get_linkn_last_count(byte);
	if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
		nodes = 6;
		return nodes;
	}
#endif

	/* We found 8 nodes so far. Now setup all nodes for 8p */
	static const u8 conn8_1[] = {
#if !CROSS_BAR_47_56
		0, 6,
		/*0, 7,*/
		1, 6,
		/*1, 7,*/
		2, 6,
		/*2, 7,*/
		3, 6,
		/*3, 7,*/
		/*4, 7,*/
		5, 6,
#else
		0, 6, 2, 0,
		/*0, 7, 2, 0,*/
		1, 6, 3, 0,
		/*1, 7, 3, 0,*/
		2, 6, 4, 0,
		/*2, 7, 4, 0,*/
		3, 6, 5, 1,
		/*3, 7, 5, 0,*/
#endif
	};

	setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));

	for(byte=0; byte<6; byte+=2) {
		setup_temp_row(byte,byte+2);
	}
	verify_connection(7);
	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
	print_linkn("(6,4) link=", byte);

	setup_row_local(7,6);
	setup_remote_row_direct(6, 4, byte);
	setup_remote_node(6);  /* Setup the regs on the remote node */
	/* Set indirect connection to 0, to 3   */
#warning "FIXME we need to find out the correct gateway for 8p"
	static const u8 conn8_2[] = {
#if !CROSS_BAR_47_56
		6, 0,
#else
		6, 0, 4, 0,
#endif
	};

	setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));

#if CROSS_BAR_47_56
	//init 5, 6 here
	/* here init 5, 6 */
	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3, 5*/
	val = get_row(5,5);
	byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
	byte = get_linkn_first(byte);
#else
	byte = get_linkn_last(byte);
#endif
	print_linkn("(5,6) link=", byte);
	setup_row_direct(5, 6, byte);

	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
	for(byte=0; byte<4; byte+=2) {
		setup_temp_row(byte+1,byte+3);
	}
	setup_temp_row(5,6);

	verify_connection(7);

	val = get_row(7,6); // to chect it if it is node6 before renaming
	if( (val>>16) == 1) { // it is real node 7 so swap it
		/* We need to recompute link to 6 */
       		val = get_row(5,5);
	       	byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
		byte = get_linkn_first(byte);
#else
       		byte = get_linkn_last(byte);
#endif
	       	print_linkn("\t-->(5,6) link=", byte);
		setup_row_direct(5, 6, byte);
#if 0
	       	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
		for(byte=0; byte<4; byte+=2) {
       			setup_temp_row(byte+1,byte+3);
	       	}
#endif
		setup_temp_row(5,6);

       		verify_connection(7);
	}
	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
	print_linkn("(6,5) link=", byte);
	setup_remote_row_direct(6, 5, byte);
	/*Till now 56, 65 done */
#endif

	rename_temp_node(6);
	enable_routing(6);

#if !CROSS_BAR_47_56
	setup_temp_row(0,1);
	for(byte=0; byte<6; byte+=2) {
		setup_temp_row(byte+1,byte+3);
	}

	verify_connection(7);

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
	print_linkn("(7,5) link=", byte);
	setup_row_local(7,7);
	setup_remote_row_direct(7, 5, byte);

#else
	val = get_row(4,4);
	byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
	byte = get_linkn_first(byte);
	print_linkn("(4,7) link=", byte);
	setup_row_direct(4, 7, byte);

	/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
	for(byte=0; byte<4; byte+=2) {
		setup_temp_row(byte,byte+2);
	}

	verify_connection(7);

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
	print_linkn("(7,4) link=", byte);
	setup_row_local(7,7);
	setup_remote_row_direct(7, 4, byte);
	/* till now 4-7, 7-4 done. */
#endif
	setup_remote_node(7);  /* Setup the regs on the remote node */

#if CROSS_BAR_47_56
	/* here init 5, 7 */
	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3, 5*/
	val = get_row(5,5);
	byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
	byte = get_linkn_first(byte);
	print_linkn("(5,7) link=", byte);
	setup_row_direct(5, 7, byte);

	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
	for(byte=0; byte<4; byte+=2) {
		setup_temp_row(byte+1,byte+3);
	}

	verify_connection(7);

	val = pci_read_config32(NODE_HT(7), 0x6c);
	byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
	print_linkn("(7,5) link=", byte);
	setup_remote_row_direct(7, 5, byte);
	/*Till now 57, 75 done */

#endif

	/* We need to init link between 6, and 7 direct link */
	val = get_row(6,6);
#if !CROSS_BAR_47_56
	byte = ((val>>16) & 0xfe) - link_connection(6,4);
#else
	byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5);
#endif
	byte = get_linkn_first(byte);
	print_linkn("(6,7) link=", byte);
	setup_row_direct(6,7, byte);

	val = get_row(7,7);
#if !CROSS_BAR_47_56
	byte = ((val>>16) & 0xfe) - link_connection(7,5);
#else
	byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4);
#endif
	byte = get_linkn_first(byte);
	print_linkn("(7,6) link=", byte);
	setup_row_direct(7,6, byte);

	/* Set indirect connection to 0, to 3  for indirect we will use clockwise routing */
	static const u8 conn8_3[] = {
#if !CROSS_BAR_47_56
		0, 7,  /* restore it*/
		1, 7,
		2, 7,
		3, 7,
		4, 7,

		6, 1,
		6, 2,
		6, 3,
		6, 5,

		7, 0,
		7, 1,
		7, 2,
		7, 3,
		7, 4,
#else


		4, 5, 6, 1,
		5, 4, 7, 1,

		6, 1, 5, 0, // or 4, 1
		6, 2, 4, 0,
		6, 3, 5, 0, // or 4, 1

		7, 0, 4, 0, // or 5, 1
		7, 1, 5, 0,
		7, 2, 4, 0, // or 5, 1
		7, 3, 5, 0,

		0, 7, 2, 0, /* restore it*/
		1, 7, 3, 0,
		2, 7, 4, 1,
		3, 7, 5, 0,

		2, 5, 4, 1, /* reset it */
		3, 4, 5, 1,

		4, 1, 2, 1, /* reset it */
		4, 3, 2, 1,

		5, 2, 3, 1, /* reset it */
		5, 0, 3, 1,

#endif
	};

	setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));

#if CROSS_BAR_47_56
	/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
	       6,  7,  6,  6,  7,  7 */
	static const u8 conn8_4[] = {
//direct
		4, 7, 6,
		5, 6, 7,
		5, 7, 6,
		7, 5, 6,
		4, 6, 7,
		6, 4, 7,

//in direct
		0, 6, 1,
		0, 7, 1,

		1, 6, 0,
		1, 7, 0,

		2, 6, 3,
//		2, 7, 3, +

//		3, 6, 1, +
		3, 7, 2,

		6, 0, 7,
		6, 1, 7, // needed for via 5
			6, 1, 4, // ???
		6, 2, 7,
		6, 3, 7, // needed for via 5
			6, 3, 4, //???
		7, 0, 6, // needed for via 4
			7, 0, 5, //???
		7, 1, 6,
		7, 2, 6, // needed for via 4
			7, 2, 5, //???
		7, 3, 6,
	};

	opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));

	static const u8 conn8_5[] = {
		2, 7, 0,

		3, 6, 1,
	};

	opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
#endif



/* ready to enable RT for Node 7 */
	enable_routing(7);      /* enable routing on node 7 (temp.) */

	return nodes;
}

#endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */


#if CONFIG_MAX_PHYSICAL_CPUS > 1

static unsigned setup_smp(void)
{
	unsigned nodes;

	print_spew("Enabling SMP settings\n");

	nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
	if(nodes == 2)
		nodes = setup_smp4();
#endif

#if CONFIG_MAX_PHYSICAL_CPUS > 4
	if(nodes == 4)
		nodes = setup_smp6();
#endif

#if CONFIG_MAX_PHYSICAL_CPUS > 6
	if(nodes == 6)
		nodes = setup_smp8();
#endif

	printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes);

	return nodes;
}

static unsigned verify_mp_capabilities(unsigned nodes)
{
	unsigned node, mask;

	mask = 0x06; /* BigMPCap */

	for (node=0; node<nodes; node++) {
		mask &= pci_read_config32(NODE_MC(node), 0xe8);
	}

	switch(mask) {
#if CONFIG_MAX_PHYSICAL_CPUS > 2
	case 0x02: /* MPCap    */
		if(nodes > 2) {
			print_err("Going back to DP\n");
			return 2;
		}
		break;
#endif
	case 0x00: /* Non SMP */
		if(nodes >1 ) {
			print_err("Going back to UP\n");
			return 1;
		}
		break;
	}

	return nodes;

}


static void clear_dead_routes(unsigned nodes)
{
	int last_row;
	int node, row;
#if CONFIG_MAX_PHYSICAL_CPUS == 8
	if(nodes==8) return;/* don't touch (7,7)*/
#endif
	last_row = nodes;
	if (nodes == 1) {
		last_row = 0;
	}
	for(node = 7; node >= 0; node--) {
		for(row = 7; row >= last_row; row--) {
			fill_row(node, row, DEFAULT);
		}
	}

	/* Update the local row */
	for( node=0; node<nodes; node++) {
		uint32_t val = 0;
		for(row =0; row<nodes; row++) {
			val |= get_row(node, row);
		}
		fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
	}
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */

#if CONFIG_LOGICAL_CPUS==1
static unsigned verify_dualcore(unsigned nodes)
{
	unsigned node, totalcpus, tmp;

	totalcpus = 0;
	for (node=0; node<nodes; node++) {
		tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
		totalcpus += (tmp + 1);
	}

	return totalcpus;

}
#endif

static void coherent_ht_finalize(unsigned nodes)
{
	unsigned node;
#if CONFIG_K8_REV_F_SUPPORT == 0
	int rev_a0;
#endif
#if CONFIG_LOGICAL_CPUS==1
	unsigned total_cpus;

	if ((!CONFIG_HAVE_OPTION_TABLE) ||
	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
		total_cpus = verify_dualcore(nodes);
	}
	else {
		total_cpus = nodes;
	}
#endif

	/* set up cpu count and node count and enable Limit
	 * Config Space Range for all available CPUs.
	 * Also clear non coherent hypertransport bus range
	 * registers on Hammer A0 revision.
	 */

	print_spew("coherent_ht_finalize\n");
#if CONFIG_K8_REV_F_SUPPORT == 0
	rev_a0 = is_cpu_rev_a0();
#endif
	for (node = 0; node < nodes; node++) {
		device_t dev;
		uint32_t val;
		dev = NODE_HT(node);

		/* Set the Total CPU and Node count in the system */
		val = pci_read_config32(dev, 0x60);
		val &= (~0x000F0070);
#if CONFIG_LOGICAL_CPUS==1
		val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
#else
		val |= ((nodes-1)<<16)|((nodes-1)<<4);
#endif
		pci_write_config32(dev, 0x60, val);

		/* Only respond to real cpu pci configuration cycles
		 * and optimize the HT settings
		 */
		val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
		val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
			(HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
			(HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
		val |= HTTC_LIMIT_CLDT_CFG |
			(HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
			(3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
			(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
		pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);

#if CONFIG_K8_REV_F_SUPPORT == 0
		if (rev_a0) {
			pci_write_config32(dev, 0x94, 0);
			pci_write_config32(dev, 0xb4, 0);
			pci_write_config32(dev, 0xd4, 0);
		}
#endif
	}

	print_spew("done\n");
}

static int apply_cpu_errata_fixes(unsigned nodes)
{
	unsigned node;
	int needs_reset = 0;
	for(node = 0; node < nodes; node++) {
#if CONFIG_K8_REV_F_SUPPORT == 0
		device_t dev;
		uint32_t cmd;
		dev = NODE_MC(node);
		if (is_cpu_pre_c0()) {

			/* Errata 66
			 * Limit the number of downstream posted requests to 1
			 */
			cmd = pci_read_config32(dev, 0x70);
			if ((cmd & (3 << 0)) != 2) {
				cmd &= ~(3<<0);
				cmd |= (2<<0);
				pci_write_config32(dev, 0x70, cmd );
				needs_reset = 1;
			}
			cmd = pci_read_config32(dev, 0x7c);
			if ((cmd & (3 << 4)) != 0) {
				cmd &= ~(3<<4);
				cmd |= (0<<4);
				pci_write_config32(dev, 0x7c, cmd );
				needs_reset = 1;
			}
			/* Clock Power/Timing Low */
			cmd = pci_read_config32(dev, 0xd4);
			if (cmd != 0x000D0001) {
				cmd = 0x000D0001;
				pci_write_config32(dev, 0xd4, cmd);
				needs_reset = 1; /* Needed? */
			}

		}
		else if (is_cpu_pre_d0()) { // d0 later don't need it
			uint32_t cmd_ref;
			/* Errata 98
			 * Set Clk Ramp Hystersis to 7
			 * Clock Power/Timing Low
			 */
			cmd_ref = 0x04e20707; /* Registered */
			cmd = pci_read_config32(dev, 0xd4);
			if(cmd != cmd_ref) {
				pci_write_config32(dev, 0xd4, cmd_ref );
				needs_reset = 1; /* Needed? */
			}
		}
#endif
	}
	return needs_reset;
}

static int optimize_link_read_pointers(unsigned nodes)
{
	unsigned node;
	int needs_reset = 0;
	for(node = 0; node < nodes; node++) {
		device_t f0_dev, f3_dev;
		uint32_t cmd_ref, cmd;
		int link;
		f0_dev = NODE_HT(node);
		f3_dev = NODE_MC(node);
		cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc);
		for(link = 0; link < 3; link++) {
			uint32_t link_type;
			unsigned reg;
			/* This works on an Athlon64 because unimplemented links return 0 */
			reg = 0x98 + (link * 0x20);
			link_type = pci_read_config32(f0_dev, reg);
			/* Only handle coherent links */
			if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
				(LinkConnected|InitComplete))
			{
				cmd &= ~(0xff << (link *8));
				cmd |= 0x25 << (link *8);
			}
		}
		if (cmd != cmd_ref) {
			pci_write_config32(f3_dev, 0xdc, cmd);
			needs_reset = 1;
		}
	}
	return needs_reset;
}

static inline unsigned get_nodes(void)
{
	return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
}

static int optimize_link_coherent_ht(void)
{
	int needs_reset = 0;

	unsigned nodes;

	nodes = get_nodes();

#if CONFIG_MAX_PHYSICAL_CPUS > 1
	if(nodes>1) {
		needs_reset |= optimize_connection(
			NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
			NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
	}

#if CONFIG_MAX_PHYSICAL_CPUS > 2
	if(nodes>2) {
	/* optimize physical connections - by LYH */
		static const u8 opt_conn4[] = {
			0,2,
			1,3,
			2,3,
		};
		needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
	}
#endif

#if CONFIG_MAX_PHYSICAL_CPUS > 4
	if(nodes>4) {
		static const uint8_t opt_conn6[] ={
			2, 4,
			3, 5,
	#if !CROSS_BAR_47_56
			4, 5,
	#endif
		};
		needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
	}
#endif

#if CONFIG_MAX_PHYSICAL_CPUS > 6
	if(nodes>6) {
	       static const uint8_t opt_conn8[] ={
		       4, 6,
	#if CROSS_BAR_47_56
		       4, 7,
		       5, 6,
	#endif
		       5, 7,
		       6, 7,
	       };
		needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
	}
#endif

#endif

	needs_reset |= apply_cpu_errata_fixes(nodes);
	needs_reset |= optimize_link_read_pointers(nodes);

	return needs_reset;
}

#if RAMINIT_SYSINFO == 1
static void setup_coherent_ht_domain(void)
#else
static int setup_coherent_ht_domain(void)
#endif
{
	unsigned nodes;
	nodes = 1;

	enable_bsp_routing();

#if CONFIG_MAX_PHYSICAL_CPUS > 1
	nodes = setup_smp();
	nodes = verify_mp_capabilities(nodes);
	clear_dead_routes(nodes);
#endif

	if (nodes == 1) {
		setup_uniprocessor();
	}
	coherent_ht_finalize(nodes);

#if RAMINIT_SYSINFO == 0
	return optimize_link_coherent_ht();
#endif
}