summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/pineview/bootblock.c
blob: 83917c2332051caeebd39f6d2d941d25142d1128 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
/*
 * This file is part of the coreboot project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <arch/bootblock.h>
#include <device/pci_ops.h>
#include "pineview.h"

#define MMCONF_256_BUSSES 16
#define ENABLE 1

void bootblock_early_northbridge_init(void)
{
	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
		CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
}