summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge/early_dmi.c
blob: bcf3e4ce4df0cc07049fc236e5abc1f2f48724a0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
/* SPDX-License-Identifier: GPL-2.0-only */

#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>

void early_init_dmi(void)
{
	int i;

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0914 + (i << 5)) |= (1 << 31);
	}

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000;
		DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11);
	}
	DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30);

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000;
		DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
		DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec;
		DMIBAR32(0x090c + (i << 5));	// !!! = 0x00000208
		DMIBAR32(0x090c + (i << 5)) = 0x00000128;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
	}

	DMIBAR32(0x0c04);	// !!! = 0x2e680008
	DMIBAR32(0x0c04) = 0x2e680008;

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
		DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0910 + (i << 5));	// !!! = 0x00006300
		DMIBAR32(0x0910 + (i << 5)) = 0x00004300;
	}

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042010
		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
	}

	DMIBAR32(0x0c00);	// !!! = 0x29700c08
	DMIBAR32(0x0c00) = 0x29700c08;

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a04 + (i << 4));	// !!! = 0x0c0708f0
		DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0900 + (i << 5));	// !!! = 0x50000000
		DMIBAR32(0x0900 + (i << 5)) = 0x50000000;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
	}

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1842ec
		DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec;
	}

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
	}

	DMIBAR32(0x0c00);	// !!! = 0x29700c08
	DMIBAR32(0x0c00) = 0x29700c08;

	DMIBAR32(0x0c0c);	// !!! = 0x16063400
	DMIBAR32(0x0c0c) = 0x00063400;

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
		DMIBAR32(0x0700 + (i << 5)) = 0x46339008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46339008
		DMIBAR32(0x0700 + (i << 5)) = 0x45339008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45339008
		DMIBAR32(0x0700 + (i << 5)) = 0x453b9008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x453b9008
		DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45bb9008
		DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
		DMIBAR32(0x0914 + (i << 5)) = 0x9021a280;
	}

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
		DMIBAR32(0x0914 + (i << 5)) = 0x9821a280;
	}

	for (i = 0; i < 4; i++) {
		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
		DMIBAR32(0x0a00 + (i << 4)) = 0x03242018;
	}

	DMIBAR32(0x0258);	// !!! = 0x40000600
	DMIBAR32(0x0258) = 0x60000600;

	for (i = 0; i < 2; i++) {
		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1846ec
		DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec;
		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9821a280
		DMIBAR32(0x0914 + (i << 5)) = 0x98200280;
	}

	DMIBAR32(DMIL0SLAT);	// !!! = 0x00c26460
	DMIBAR32(DMIL0SLAT) = 0x00c2403c;

	early_pch_init_native_dmi_pre();

	/* Write once settings */
	DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
			    (2 <<  0) |	// 5GT/s
			    (2 << 12) |	// L0s 128 ns to less than 256 ns
			    (2 << 15);	// L1 2 us to less than 4 us

	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
	while (DMIBAR16(DMILSTS) & TXTRN)
		;

	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
	while (DMIBAR16(DMILSTS) & TXTRN)
		;

	const u8  w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
	const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500;

	printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
	/*
	 * Virtual Channel resources must match settings in RCBA!
	 *
	 * Channel Vp and Vm are documented in:
	 * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium
	 *  Processor Family, and Desktop Intel Celeron Processor Family Vol. 2"
	 */

	/* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */
	DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
	/* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */
	DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
	/* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp  */
	DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1);
	/* Channel m: Enable, Set ID to 0, map TC7 to VCm */
	DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1);

	/* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */
	DMIBAR8(DMIPVCCAP1) |= 1;

	early_pch_init_native_dmi_post();

	/*
	 * BIOS Requirement: Check if DMI VC Negotiation was successful.
	 * Wait for virtual channels negotiation pending.
	 */
	while (DMIBAR16(DMIVC0RSTS) & VC0NP)
		;
	while (DMIBAR16(DMIVC1RSTS) & VC1NP)
		;
	while (DMIBAR16(DMIVCPRSTS) & VCPNP)
		;
	while (DMIBAR16(DMIVCMRSTS) & VCMNP)
		;
}