path: root/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h

/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_DDR_REGS_H__
#define __SOC_BROADCOM_CYGNUS_DDR_REGS_H__

#define CRMU_DDR_PHY_AON_CTRL 0x0301c024
#define CRMU_DDR_PHY_AON_CTRL_BASE 0x024
#define CRMU_DDR_PHY_AON_CTRL_OFFSET 0x0301c024
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN 5
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_RESETVALUE 0x0
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY 4
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_RESETVALUE 0x0
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY 3
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_RESETVALUE 0x0
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI 2
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_RESETVALUE 0x1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_RESETVALUE 0x1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL 0
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_WIDTH 1
#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_RESETVALUE 0x1
#define CRMU_DDR_PHY_AON_CTRL__RESERVED_L 31
#define CRMU_DDR_PHY_AON_CTRL__RESERVED_R 6
#define CRMU_DDR_PHY_AON_CTRL_WIDTH 6
#define CRMU_DDR_PHY_AON_CTRL__WIDTH 6
#define CRMU_DDR_PHY_AON_CTRL_ALL_L 5
#define CRMU_DDR_PHY_AON_CTRL_ALL_R 0
#define CRMU_DDR_PHY_AON_CTRL__ALL_L 5
#define CRMU_DDR_PHY_AON_CTRL__ALL_R 0
#define CRMU_DDR_PHY_AON_CTRL_DATAMASK 0x0000003f
#define CRMU_DDR_PHY_AON_CTRL_RESETVALUE 0x7

#define CRMU_IHOST_POR_WAKEUP_FLAG 0x03024c50
#define CRMU_IHOST_POR_WAKEUP_FLAG_BASE 0xc50
#define CRMU_IHOST_POR_WAKEUP_FLAG_OFFSET 0x03024c50
#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG 0
#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_WIDTH 1
#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_RESETVALUE 0x0
#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_L 31
#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_R 1
#define CRMU_IHOST_POR_WAKEUP_FLAG_WIDTH 1
#define CRMU_IHOST_POR_WAKEUP_FLAG__WIDTH 1
#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_L 0
#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_R 0
#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_L 0
#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_R 0
#define CRMU_IHOST_POR_WAKEUP_FLAG_DATAMASK 0x00000001
#define CRMU_IHOST_POR_WAKEUP_FLAG_RESETVALUE 0x0

#define DDR_DENALI_CTL_00 0x18010000
#define DDR_DENALI_CTL_00_BASE 0x000
#define DDR_DENALI_CTL_00__VERSION_L 31
#define DDR_DENALI_CTL_00__VERSION_R 16
#define DDR_DENALI_CTL_00__VERSION_WIDTH 16
#define DDR_DENALI_CTL_00__VERSION_RESETVALUE 0x2041
#define DDR_DENALI_CTL_00__DRAM_CLASS_L 11
#define DDR_DENALI_CTL_00__DRAM_CLASS_R 8
#define DDR_DENALI_CTL_00__DRAM_CLASS_WIDTH 4
#define DDR_DENALI_CTL_00__DRAM_CLASS_RESETVALUE 0x0
#define DDR_DENALI_CTL_00__START 0
#define DDR_DENALI_CTL_00__START_WIDTH 1
#define DDR_DENALI_CTL_00__START_RESETVALUE 0x0
#define DDR_DENALI_CTL_00__RESERVED_L 15
#define DDR_DENALI_CTL_00__RESERVED_R 12
#define DDR_DENALI_CTL_00_WIDTH 32
#define DDR_DENALI_CTL_00__WIDTH 32
#define DDR_DENALI_CTL_00_ALL_L 31
#define DDR_DENALI_CTL_00_ALL_R 0
#define DDR_DENALI_CTL_00__ALL_L 31
#define DDR_DENALI_CTL_00__ALL_R 0
#define DDR_DENALI_CTL_00_DATAMASK 0xffff0f01
#define DDR_DENALI_CTL_00_RDWRMASK 0x0000f0fe
#define DDR_DENALI_CTL_00_RESETVALUE 0x20410000

#define DDR_DENALI_CTL_56 0x180100e0
#define DDR_DENALI_CTL_56_BASE 0x0e0
#define DDR_DENALI_CTL_56__LP_CMD_L 31
#define DDR_DENALI_CTL_56__LP_CMD_R 24
#define DDR_DENALI_CTL_56__LP_CMD_WIDTH 8
#define DDR_DENALI_CTL_56__LP_CMD_RESETVALUE 0x00
#define DDR_DENALI_CTL_56__CKSRX_F1_L 23
#define DDR_DENALI_CTL_56__CKSRX_F1_R 16
#define DDR_DENALI_CTL_56__CKSRX_F1_WIDTH 8
#define DDR_DENALI_CTL_56__CKSRX_F1_RESETVALUE 0x00
#define DDR_DENALI_CTL_56__CKSRE_F1_L 15
#define DDR_DENALI_CTL_56__CKSRE_F1_R 8
#define DDR_DENALI_CTL_56__CKSRE_F1_WIDTH 8
#define DDR_DENALI_CTL_56__CKSRE_F1_RESETVALUE 0x00
#define DDR_DENALI_CTL_56__CKSRX_F0_L 7
#define DDR_DENALI_CTL_56__CKSRX_F0_R 0
#define DDR_DENALI_CTL_56__CKSRX_F0_WIDTH 8
#define DDR_DENALI_CTL_56__CKSRX_F0_RESETVALUE 0x00
#define DDR_DENALI_CTL_56_WIDTH 32
#define DDR_DENALI_CTL_56__WIDTH 32
#define DDR_DENALI_CTL_56_ALL_L 31
#define DDR_DENALI_CTL_56_ALL_R 0
#define DDR_DENALI_CTL_56__ALL_L 31
#define DDR_DENALI_CTL_56__ALL_R 0
#define DDR_DENALI_CTL_56_DATAMASK 0xffffffff
#define DDR_DENALI_CTL_56_RDWRMASK 0x00000000
#define DDR_DENALI_CTL_56_RESETVALUE 0x0

#define DDR_DENALI_CTL_175 0x180102bc
#define DDR_DENALI_CTL_175_BASE 0x2bc
#define DDR_DENALI_CTL_175__INT_STATUS_L 31
#define DDR_DENALI_CTL_175__INT_STATUS_R 0
#define DDR_DENALI_CTL_175__INT_STATUS_WIDTH 32
#define DDR_DENALI_CTL_175__INT_STATUS_RESETVALUE 0x00000000
#define DDR_DENALI_CTL_175_WIDTH 32
#define DDR_DENALI_CTL_175__WIDTH 32
#define DDR_DENALI_CTL_175_ALL_L 31
#define DDR_DENALI_CTL_175_ALL_R 0
#define DDR_DENALI_CTL_175__ALL_L 31
#define DDR_DENALI_CTL_175__ALL_R 0
#define DDR_DENALI_CTL_175_DATAMASK 0xffffffff
#define DDR_DENALI_CTL_175_RDWRMASK 0x00000000
#define DDR_DENALI_CTL_175_RESETVALUE 0x0

#define DDR_DENALI_CTL_177 0x180102c4
#define DDR_DENALI_CTL_177_BASE 0x2c4
#define DDR_DENALI_CTL_177__INT_ACK_L 31
#define DDR_DENALI_CTL_177__INT_ACK_R 0
#define DDR_DENALI_CTL_177__INT_ACK_WIDTH 32
#define DDR_DENALI_CTL_177__INT_ACK_RESETVALUE 0x00000000
#define DDR_DENALI_CTL_177_WIDTH 32
#define DDR_DENALI_CTL_177__WIDTH 32
#define DDR_DENALI_CTL_177_ALL_L 31
#define DDR_DENALI_CTL_177_ALL_R 0
#define DDR_DENALI_CTL_177__ALL_L 31
#define DDR_DENALI_CTL_177__ALL_R 0
#define DDR_DENALI_CTL_177_DATAMASK 0xffffffff
#define DDR_DENALI_CTL_177_RDWRMASK 0x00000000
#define DDR_DENALI_CTL_177_RESETVALUE 0x0

#define DDR_BistConfig 0x18010c00
#define DDR_BistConfig_BASE 0xc00
#define DDR_BistConfig__bist_finished_period_L 24
#define DDR_BistConfig__bist_finished_period_R 17
#define DDR_BistConfig__bist_finished_period_WIDTH 8
#define DDR_BistConfig__bist_finished_period_RESETVALUE 0x00
#define DDR_BistConfig__clr_bist_last_data_err 16
#define DDR_BistConfig__clr_bist_last_data_err_WIDTH 1
#define DDR_BistConfig__clr_bist_last_data_err_RESETVALUE 0x0
#define DDR_BistConfig__bus16_mode 15
#define DDR_BistConfig__bus16_mode_WIDTH 1
#define DDR_BistConfig__bus16_mode_RESETVALUE 0x0
#define DDR_BistConfig__enable_8_banks_mode 14
#define DDR_BistConfig__enable_8_banks_mode_WIDTH 1
#define DDR_BistConfig__enable_8_banks_mode_RESETVALUE 0x0
#define DDR_BistConfig__disable_col_bank_swapping 13
#define DDR_BistConfig__disable_col_bank_swapping_WIDTH 1
#define DDR_BistConfig__disable_col_bank_swapping_RESETVALUE 0x0
#define DDR_BistConfig__bist_arpriority_L 12
#define DDR_BistConfig__bist_arpriority_R 10
#define DDR_BistConfig__bist_arpriority_WIDTH 3
#define DDR_BistConfig__bist_arpriority_RESETVALUE 0x0
#define DDR_BistConfig__bist_arapcmd 9
#define DDR_BistConfig__bist_arapcmd_WIDTH 1
#define DDR_BistConfig__bist_arapcmd_RESETVALUE 0x0
#define DDR_BistConfig__bist_awuser 8
#define DDR_BistConfig__bist_awuser_WIDTH 1
#define DDR_BistConfig__bist_awuser_RESETVALUE 0x0
#define DDR_BistConfig__bist_awpriority_L 7
#define DDR_BistConfig__bist_awpriority_R 5
#define DDR_BistConfig__bist_awpriority_WIDTH 3
#define DDR_BistConfig__bist_awpriority_RESETVALUE 0x0
#define DDR_BistConfig__bist_awcobuf 4
#define DDR_BistConfig__bist_awcobuf_WIDTH 1
#define DDR_BistConfig__bist_awcobuf_RESETVALUE 0x0
#define DDR_BistConfig__bist_awapcmd 3
#define DDR_BistConfig__bist_awapcmd_WIDTH 1
#define DDR_BistConfig__bist_awapcmd_RESETVALUE 0x0
#define DDR_BistConfig__bist_awcache_0 2
#define DDR_BistConfig__bist_awcache_0_WIDTH 1
#define DDR_BistConfig__bist_awcache_0_RESETVALUE 0x0
#define DDR_BistConfig__axi_port_sel 1
#define DDR_BistConfig__axi_port_sel_WIDTH 1
#define DDR_BistConfig__axi_port_sel_RESETVALUE 0x0
#define DDR_BistConfig__bist_resetb 0
#define DDR_BistConfig__bist_resetb_WIDTH 1
#define DDR_BistConfig__bist_resetb_RESETVALUE 0x0
#define DDR_BistConfig__RESERVED_L 31
#define DDR_BistConfig__RESERVED_R 25
#define DDR_BistConfig_WIDTH 25
#define DDR_BistConfig__WIDTH 25
#define DDR_BistConfig_ALL_L 24
#define DDR_BistConfig_ALL_R 0
#define DDR_BistConfig__ALL_L 24
#define DDR_BistConfig__ALL_R 0
#define DDR_BistConfig_DATAMASK 0x01ffffff
#define DDR_BistConfig_RDWRMASK 0xfe000000
#define DDR_BistConfig_RESETVALUE 0x0

#define DDR_BistGeneralConfigurations 0x18010c08
#define DDR_BistGeneralConfigurations_BASE 0xc08
#define DDR_BistGeneralConfigurations__NumCols_L 6
#define DDR_BistGeneralConfigurations__NumCols_R 4
#define DDR_BistGeneralConfigurations__NumCols_WIDTH 3
#define DDR_BistGeneralConfigurations__NumCols_RESETVALUE 0x2
#define DDR_BistGeneralConfigurations__RESERVED_L 31
#define DDR_BistGeneralConfigurations__RESERVED_R 7
#define DDR_BistGeneralConfigurations_WIDTH 7
#define DDR_BistGeneralConfigurations__WIDTH 7
#define DDR_BistGeneralConfigurations_ALL_L 6
#define DDR_BistGeneralConfigurations_ALL_R 0
#define DDR_BistGeneralConfigurations__ALL_L 6
#define DDR_BistGeneralConfigurations__ALL_R 0
#define DDR_BistGeneralConfigurations_DATAMASK 0x00000070
#define DDR_BistGeneralConfigurations_RDWRMASK 0xffffff8f
#define DDR_BistGeneralConfigurations_RESETVALUE 0x20

#define DDR_PHY_CONTROL_REGS_REVISION 0x18011000
#define DDR_PHY_CONTROL_REGS_REVISION_BASE 0x000
#define DDR_PHY_CONTROL_REGS_REVISION__reserved_L 31
#define DDR_PHY_CONTROL_REGS_REVISION__reserved_R 25
#define DDR_PHY_CONTROL_REGS_REVISION__reserved_WIDTH 7
#define DDR_PHY_CONTROL_REGS_REVISION__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_L 24
#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_R 23
#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_WIDTH 2
#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_L 22
#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_R 20
#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_WIDTH 3
#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_RESETVALUE 0x2
#define DDR_PHY_CONTROL_REGS_REVISION__WB 19
#define DDR_PHY_CONTROL_REGS_REVISION__WB_WIDTH 1
#define DDR_PHY_CONTROL_REGS_REVISION__WB_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_REVISION__BITS_L 18
#define DDR_PHY_CONTROL_REGS_REVISION__BITS_R 16
#define DDR_PHY_CONTROL_REGS_REVISION__BITS_WIDTH 3
#define DDR_PHY_CONTROL_REGS_REVISION__BITS_RESETVALUE 0x2
#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_L 15
#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_R 8
#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_WIDTH 8
#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_RESETVALUE 0xe2
#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_L 7
#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_R 0
#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_WIDTH 8
#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_RESETVALUE 0x01
#define DDR_PHY_CONTROL_REGS_REVISION_WIDTH 32
#define DDR_PHY_CONTROL_REGS_REVISION__WIDTH 32
#define DDR_PHY_CONTROL_REGS_REVISION_ALL_L 31
#define DDR_PHY_CONTROL_REGS_REVISION_ALL_R 0
#define DDR_PHY_CONTROL_REGS_REVISION__ALL_L 31
#define DDR_PHY_CONTROL_REGS_REVISION__ALL_R 0
#define DDR_PHY_CONTROL_REGS_REVISION_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_REVISION_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_REVISION_RESETVALUE 0xa2e201
#define DDR_PHY_CONTROL_REGS_PLL_STATUS 0x18011004
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_BASE 0x004
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_L 23
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_R 20
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_WIDTH 4
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_L 19
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_R 17
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_WIDTH 3
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST 16
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X 15
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X 14
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X 13
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_L 12
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_R 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_WIDTH 12
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_RESETVALUE 0x000
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK 0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_L 31
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_R 24
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_WIDTH 24
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__WIDTH 24
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_L 23
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_L 23
#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_DATAMASK 0x00ffffff
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RDWRMASK 0xff000000
#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG 0x18011008
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_BASE 0x008
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco 27
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_L 26
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_R 25
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_L 24
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_R 23
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_RESETVALUE 0x3
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL 22
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_L 21
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_R 20
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_L 19
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_R 18
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_RESETVALUE 0x3
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD 17
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE 16
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_L 13
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_R 8
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_WIDTH 6
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV 4
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_L 3
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_R 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN 0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_WIDTH 1
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_L 31
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_R 28
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_L 15
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_R 14
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_L 7
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_R 5
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_L 31
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_R 28
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_WIDTH 28
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__WIDTH 28
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_L 27
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_L 27
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_DATAMASK 0x0fff3f1f
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RDWRMASK 0xf000c0e0
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RESETVALUE 0x39d0000

#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS 0x18011018
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_BASE 0x018
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_L 27
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R 20
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH 8
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_RESETVALUE 0x01
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_L 15
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R 12
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH 4
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_L 11
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_R 10
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_WIDTH 2
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_L 9
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R 0
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH 10
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_RESETVALUE 0x20
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_L 31
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_R 28
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_WIDTH 28
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__WIDTH 28
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_L 27
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_L 27
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_R 0
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_DATAMASK 0x0ff0ffff
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RDWRMASK 0xf00f0000
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RESETVALUE 0x101020

#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x1801102c
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_BASE 0x02c
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE 30
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_L 29
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_R 4
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_WIDTH 26
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB 3
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ 2
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESETVALUE 0xa
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x18011030
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_BASE 0x030
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_R 11
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_WIDTH 21
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_L 10
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_WIDTH 11
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x18011034
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_BASE 0x034
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_R 22
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_WIDTH 10
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_L 21
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_WIDTH 22
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__WIDTH 32
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_L 31
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_R 0
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESETVALUE 0x0

#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x1801103c
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_BASE 0x03c
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB 27
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5 26
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR 25
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1 24
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0 23
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT 22
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR 21
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA 20
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2 19
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1 18
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0 17
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1 16
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15 15
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14 14
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13 13
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12 12
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11 11
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10 10
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09 9
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_WIDTH 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_L 8
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_R 2
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_WIDTH 7
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_L 1
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R 0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_WIDTH 2
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_L 31
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_R 28
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_WIDTH 28
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__WIDTH 28
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_L 27
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_R 0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_L 27
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_R 0
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_DATAMASK 0x0fffffff
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RDWRMASK 0xf0000000
#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESETVALUE 0x0

#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x18011200
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_BASE 0x200
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_L 31
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_R 20
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_WIDTH 12
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_RESETVALUE 0x000
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT 19
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_L 18
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_R 17
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_WIDTH 2
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST 16
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3 15
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2 14
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1 13
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0 12
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_L 11
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_R 6
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_WIDTH 6
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_RESETVALUE 0x20
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_L 5
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_R 0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_WIDTH 6
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_RESETVALUE 0x20
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_WIDTH 32
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__WIDTH 32
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_L 31
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_R 0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_L 31
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_R 0
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESETVALUE 0xf820

#define DDR_PHY_CONTROL_REGS_DFI_CNTRL 0x1801123c
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_BASE 0x23c
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_L 31
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_R 10
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_WIDTH 22
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1 9
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0 8
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1 7
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0 6
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N 5
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1 4
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0 3
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE 2
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ 0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_WIDTH 1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_WIDTH 32
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__WIDTH 32
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_L 31
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_R 0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_L 31
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_R 0
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_DATAMASK 0xffffffff
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RDWRMASK 0x00000000
#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RESETVALUE 0xe1

#define DDR_PHY_CONTROL_REGS_ZQ_CAL 0x18011248
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_BASE 0x248
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS 19
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_WIDTH 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS 18
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_WIDTH 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ 17
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_WIDTH 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_L 16
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_R 12
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_WIDTH 5
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_L 11
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_R 7
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_WIDTH 5
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_L 6
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_R 2
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_WIDTH 5
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_RESETVALUE 0x0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_WIDTH 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB 0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_WIDTH 1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_RESETVALUE 0x1
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_L 31
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_R 20
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_WIDTH 20
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__WIDTH 20
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_L 19
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_R 0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_L 19
#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_R 0
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_DATAMASK 0x000fffff
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RDWRMASK 0xfff00000
#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RESETVALUE 0x20003

#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x18011400
#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BASE 0x400

#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x180114c8
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_BASE 0x4c8
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE 31
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved 15
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB 3
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ 2
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P 0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_L 30
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_R 20
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_WIDTH 32
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__WIDTH 32
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_L 31
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_R 0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_L 31
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_R 0
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESETVALUE 0x5000a

#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x180116c8
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_BASE 0x6c8
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE 31
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved 15
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB 3
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ 2
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P 0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_L 30
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_R 20
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_WIDTH 32
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__WIDTH 32
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_L 31
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_R 0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_L 31
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_R 0
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESETVALUE 0x5000a

#define IHOST_SCU_POWER_STATUS 0x19020008
#define IHOST_SCU_POWER_STATUS_BASE 0x008
#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_L 25
#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_R 24
#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_WIDTH 2
#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_RESETVALUE 0x0
#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_L 17
#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_R 16
#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_WIDTH 2
#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_RESETVALUE 0x0
#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_L 9
#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_R 8
#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_WIDTH 2
#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_RESETVALUE 0x0
#define IHOST_SCU_POWER_STATUS__reserved_L 7
#define IHOST_SCU_POWER_STATUS__reserved_R 2
#define IHOST_SCU_POWER_STATUS__reserved_WIDTH 6
#define IHOST_SCU_POWER_STATUS__reserved_RESETVALUE 0x0
#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_L 1
#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_R 0
#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_WIDTH 2
#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_RESETVALUE 0x0
#define IHOST_SCU_POWER_STATUS__RESERVED_0_L 31
#define IHOST_SCU_POWER_STATUS__RESERVED_0_R 26
#define IHOST_SCU_POWER_STATUS__RESERVED_1_L 23
#define IHOST_SCU_POWER_STATUS__RESERVED_1_R 18
#define IHOST_SCU_POWER_STATUS__RESERVED_2_L 15
#define IHOST_SCU_POWER_STATUS__RESERVED_2_R 10
#define IHOST_SCU_POWER_STATUS__RESERVED_L 31
#define IHOST_SCU_POWER_STATUS__RESERVED_R 26
#define IHOST_SCU_POWER_STATUS_WIDTH 26
#define IHOST_SCU_POWER_STATUS__WIDTH 26
#define IHOST_SCU_POWER_STATUS_ALL_L 25
#define IHOST_SCU_POWER_STATUS_ALL_R 0
#define IHOST_SCU_POWER_STATUS__ALL_L 25
#define IHOST_SCU_POWER_STATUS__ALL_R 0
#define IHOST_SCU_POWER_STATUS_DATAMASK 0x030303ff
#define IHOST_SCU_POWER_STATUS_RDWRMASK 0xfcfcfc00
#define IHOST_SCU_POWER_STATUS_RESETVALUE 0x0

#define IHOST_GTIM_GLOB_CTRL 0x19020208
#define IHOST_GTIM_GLOB_CTRL_BASE 0x208
#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_L 15
#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_R 8
#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_WIDTH 8
#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_RESETVALUE 0x00
#define IHOST_GTIM_GLOB_CTRL__reserved_L 7
#define IHOST_GTIM_GLOB_CTRL__reserved_R 4
#define IHOST_GTIM_GLOB_CTRL__reserved_WIDTH 4
#define IHOST_GTIM_GLOB_CTRL__reserved_RESETVALUE 0x0
#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G 3
#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_WIDTH 1
#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_RESETVALUE 0x0
#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G 2
#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_WIDTH 1
#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_RESETVALUE 0x0
#define IHOST_GTIM_GLOB_CTRL__Comp_en_G 1
#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_WIDTH 1
#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_RESETVALUE 0x0
#define IHOST_GTIM_GLOB_CTRL__Timer_en_G 0
#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_WIDTH 1
#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_RESETVALUE 0x0
#define IHOST_GTIM_GLOB_CTRL__RESERVED_L 31
#define IHOST_GTIM_GLOB_CTRL__RESERVED_R 16
#define IHOST_GTIM_GLOB_CTRL_WIDTH 16
#define IHOST_GTIM_GLOB_CTRL__WIDTH 16
#define IHOST_GTIM_GLOB_CTRL_ALL_L 15
#define IHOST_GTIM_GLOB_CTRL_ALL_R 0
#define IHOST_GTIM_GLOB_CTRL__ALL_L 15
#define IHOST_GTIM_GLOB_CTRL__ALL_R 0
#define IHOST_GTIM_GLOB_CTRL_DATAMASK 0x0000ffff
#define IHOST_GTIM_GLOB_CTRL_RDWRMASK 0xffff0000
#define IHOST_GTIM_GLOB_CTRL_RESETVALUE 0x0

#define DDR_S0_IDM_RESET_CONTROL 0xf8101800
#define DDR_S0_IDM_RESET_CONTROL_BASE 0x800
#define DDR_S0_IDM_RESET_CONTROL__RESET 0
#define DDR_S0_IDM_RESET_CONTROL__RESET_WIDTH 1
#define DDR_S0_IDM_RESET_CONTROL__RESET_RESETVALUE 0x0
#define DDR_S0_IDM_RESET_CONTROL__RESERVED_L 31
#define DDR_S0_IDM_RESET_CONTROL__RESERVED_R 1
#define DDR_S0_IDM_RESET_CONTROL_WIDTH 1
#define DDR_S0_IDM_RESET_CONTROL__WIDTH 1
#define DDR_S0_IDM_RESET_CONTROL_ALL_L 0
#define DDR_S0_IDM_RESET_CONTROL_ALL_R 0
#define DDR_S0_IDM_RESET_CONTROL__ALL_L 0
#define DDR_S0_IDM_RESET_CONTROL__ALL_R 0
#define DDR_S0_IDM_RESET_CONTROL_DATAMASK 0x00000001
#define DDR_S0_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
#define DDR_S0_IDM_RESET_CONTROL_RESETVALUE 0x0

#define DDR_S1_IDM_IO_CONTROL_DIRECT 0xf8102408
#define DDR_S1_IDM_IO_CONTROL_DIRECT_BASE 0x408
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master 31
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf 30
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_RESETVALUE 0x1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0 29
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_RESETVALUE 0x1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn 28
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n 27
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb 26
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby 13
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps 12
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_RESETVALUE 0x1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank 11
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_L 10
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_R 9
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_WIDTH 2
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_L 8
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_R 4
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_WIDTH 5
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_RESETVALUE 0xb
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid 3
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_RESETVALUE 0x1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init 2
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_RESETVALUE 0x0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable 0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_WIDTH 1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_RESETVALUE 0x1
#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_L 25
#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_R 14
#define DDR_S1_IDM_IO_CONTROL_DIRECT_WIDTH 32
#define DDR_S1_IDM_IO_CONTROL_DIRECT__WIDTH 32
#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_L 31
#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_R 0
#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_L 31
#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_R 0
#define DDR_S1_IDM_IO_CONTROL_DIRECT_DATAMASK 0xfc003ffd
#define DDR_S1_IDM_IO_CONTROL_DIRECT_RDWRMASK 0x03ffc002
#define DDR_S1_IDM_IO_CONTROL_DIRECT_RESETVALUE 0x600010b9
#define DDR_S1_IDM_IO_STATUS 0xf8102500
#define DDR_S1_IDM_IO_STATUS_BASE 0x500
#define DDR_S1_IDM_IO_STATUS__RESERVED_L 31
#define DDR_S1_IDM_IO_STATUS__RESERVED_R 4
#define DDR_S1_IDM_IO_STATUS__RESERVED_WIDTH 28
#define DDR_S1_IDM_IO_STATUS__RESERVED_RESETVALUE 0x0000000
#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb 3
#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_WIDTH 1
#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_RESETVALUE 0x1
#define DDR_S1_IDM_IO_STATUS__o_phy_ready 2
#define DDR_S1_IDM_IO_STATUS__o_phy_ready_WIDTH 1
#define DDR_S1_IDM_IO_STATUS__o_phy_ready_RESETVALUE 0x0
#define DDR_S1_IDM_IO_STATUS__ddr_type_L 1
#define DDR_S1_IDM_IO_STATUS__ddr_type_R 0
#define DDR_S1_IDM_IO_STATUS__ddr_type_WIDTH 2
#define DDR_S1_IDM_IO_STATUS__ddr_type_RESETVALUE 0x0
#define DDR_S1_IDM_IO_STATUS_WIDTH 32
#define DDR_S1_IDM_IO_STATUS__WIDTH 32
#define DDR_S1_IDM_IO_STATUS_ALL_L 31
#define DDR_S1_IDM_IO_STATUS_ALL_R 0
#define DDR_S1_IDM_IO_STATUS__ALL_L 31
#define DDR_S1_IDM_IO_STATUS__ALL_R 0
#define DDR_S1_IDM_IO_STATUS_DATAMASK 0xffffffff
#define DDR_S1_IDM_IO_STATUS_RDWRMASK 0x00000000
#define DDR_S1_IDM_IO_STATUS_RESETVALUE 0x8
#define DDR_S1_IDM_RESET_CONTROL 0xf8102800
#define DDR_S1_IDM_RESET_CONTROL_BASE 0x800
#define DDR_S1_IDM_RESET_CONTROL__RESET 0
#define DDR_S1_IDM_RESET_CONTROL__RESET_WIDTH 1
#define DDR_S1_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
#define DDR_S1_IDM_RESET_CONTROL__RESERVED_L 31
#define DDR_S1_IDM_RESET_CONTROL__RESERVED_R 1
#define DDR_S1_IDM_RESET_CONTROL_WIDTH 1
#define DDR_S1_IDM_RESET_CONTROL__WIDTH 1
#define DDR_S1_IDM_RESET_CONTROL_ALL_L 0
#define DDR_S1_IDM_RESET_CONTROL_ALL_R 0
#define DDR_S1_IDM_RESET_CONTROL__ALL_L 0
#define DDR_S1_IDM_RESET_CONTROL__ALL_R 0
#define DDR_S1_IDM_RESET_CONTROL_DATAMASK 0x00000001
#define DDR_S1_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
#define DDR_S1_IDM_RESET_CONTROL_RESETVALUE 0x1

#define DDR_S2_IDM_RESET_CONTROL 0xf8103800
#define DDR_S2_IDM_RESET_CONTROL_BASE 0x800
#define DDR_S2_IDM_RESET_CONTROL__RESET 0
#define DDR_S2_IDM_RESET_CONTROL__RESET_WIDTH 1
#define DDR_S2_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
#define DDR_S2_IDM_RESET_CONTROL__RESERVED_L 31
#define DDR_S2_IDM_RESET_CONTROL__RESERVED_R 1
#define DDR_S2_IDM_RESET_CONTROL_WIDTH 1
#define DDR_S2_IDM_RESET_CONTROL__WIDTH 1
#define DDR_S2_IDM_RESET_CONTROL_ALL_L 0
#define DDR_S2_IDM_RESET_CONTROL_ALL_R 0
#define DDR_S2_IDM_RESET_CONTROL__ALL_L 0
#define DDR_S2_IDM_RESET_CONTROL__ALL_R 0
#define DDR_S2_IDM_RESET_CONTROL_DATAMASK 0x00000001
#define DDR_S2_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
#define DDR_S2_IDM_RESET_CONTROL_RESETVALUE 0x1

#define ROM_S0_IDM_IO_STATUS 0xf8104500
#define ROM_S0_IDM_IO_STATUS_BASE 0x500
#define ROM_S0_IDM_IO_STATUS__jump_to_sbl 16
#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_WIDTH 1
#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_RESETVALUE 0x0
#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_L 11
#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_R 8
#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_WIDTH 4
#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_RESETVALUE 0x0
#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_L 3
#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_R 0
#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_WIDTH 4
#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_RESETVALUE 0x0
#define ROM_S0_IDM_IO_STATUS__RESERVED_0_L 31
#define ROM_S0_IDM_IO_STATUS__RESERVED_0_R 17
#define ROM_S0_IDM_IO_STATUS__RESERVED_1_L 15
#define ROM_S0_IDM_IO_STATUS__RESERVED_1_R 12
#define ROM_S0_IDM_IO_STATUS__RESERVED_2_L 7
#define ROM_S0_IDM_IO_STATUS__RESERVED_2_R 4
#define ROM_S0_IDM_IO_STATUS__RESERVED_L 31
#define ROM_S0_IDM_IO_STATUS__RESERVED_R 17
#define ROM_S0_IDM_IO_STATUS_WIDTH 17
#define ROM_S0_IDM_IO_STATUS__WIDTH 17
#define ROM_S0_IDM_IO_STATUS_ALL_L 16
#define ROM_S0_IDM_IO_STATUS_ALL_R 0
#define ROM_S0_IDM_IO_STATUS__ALL_L 16
#define ROM_S0_IDM_IO_STATUS__ALL_R 0
#define ROM_S0_IDM_IO_STATUS_DATAMASK 0x00010f0f
#define ROM_S0_IDM_IO_STATUS_RDWRMASK 0xfffef0f0
#define ROM_S0_IDM_IO_STATUS_RESETVALUE 0x0
#endif /* __SOC_BROADCOM_CYGNUS_DDR_REGS_H__ */