1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
|
#define __SIMPLE_DEVICE__ 1
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/rcba.h>
#include <soc/iobp.h>
#include <soc/pci_devs.h>
#include "pch.h"
#include "usb.h"
int PchStartUsbInit(void *usb_pol, uintptr_t ehcibar, uintptr_t xhcibar, uint8_t revision)
{
printk(BIOS_DEBUG, "%s: revision is %d.\n", __func__, revision);
printk(BIOS_DEBUG, "EHCIBAR is 0x%lx, XHCIBAR is 0x%lx.\n", ehcibar, xhcibar);
if (usb_pol == NULL) {
printk(BIOS_ERR, "usb_pol pointer is NULL!\n");
return 0x80000002;
}
uint32_t rcba_fd = RCBA32(FD);
int ret = CommonUsbInit(usb_pol, ehcibar, xhcibar, 0, RCBA_BASE_ADDRESS, &rcba_fd,
revision);
if (ret < 0) {
printk(BIOS_ERR, "CommonUsbInit returns 0x%x!\n", ret);
}
RCBA32(FD) = rcba_fd;
return ret;
}
static void finalize_ehci(void)
{
/*
if (pch_is_lp()) {
if (EHCI dev is disabled) {
RCBA32_OR(0x3a84, 5);
}
}
*/
pch_iobp_update(0xe5004001,0xffffffff,0xc0);
// if (EHCI1_DEV is disabled) {
//pci_or_config32(EHCI1_DEV, 0xdc, 0x28);
//} else {
pci_or_config32(PCH_DEV_EHCI, 0xdc, 0x27);
//}
pci_or_config32(PCH_DEV_EHCI, 0x78, 3);
/*
if (!pch_is_lp()) {
if (EHCI2_DEV is disabled) {
pci_or_config32(EHCI2_DEV, 0xdc, 0x28);
} else {
pci_or_config32(EHCI2_DEV, 0xdc, 0x27);
}
pci_or_config32(EHCI2_DEV, 0x78, 3);
}
*/
}
void finalize_usb(void)
{
finalize_ehci();
pch_iobp_update(0xe5004001,0xffffffff,0xc0);
uint32_t xhcc = pci_read_config32(PCH_DEV_XHCI, 0x40);
pci_write_config32(PCH_DEV_XHCI, 0x40, xhcc | 0x100);
/* D3IL1E | xHCIL1E | IIL1E >= 1024 bb_cclk */
pci_write_config8(PCH_DEV_XHCI, 0x42, ((xhcc >> 16) & 0x7f) | 0x36);
pci_or_config16(PCH_DEV_XHCI, 0x44, 0x288);
uint32_t orval;
if (!pch_is_lp()) {
orval = 0x40;
} else {
if (!is_wildcat_point_lp()) {
orval = 0x40000;
} else {
orval = 0x40040;
}
}
pci_or_config32(PCH_DEV_XHCI, 0xa0, orval);
if (!is_wildcat_point_lp()) {
if (!pch_is_lp()) {
orval = 0;
} else {
orval = 0x1800;
}
} else {
orval = xhcc;
}
pci_update_config32(PCH_DEV_XHCI, 0xa4, 0xffffdfff, orval);
}
|