blob: f183253443a1a919f7d71428ad8920db484e9d72 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus,
const struct device *dev)
{
const struct soc_intel_cannonlake_config *config;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->i2c[bus];
}
uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
{
return EARLY_I2C_BASE(bus);
}
int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
{
switch (devfn) {
case PCH_DEVFN_I2C0:
return 0;
case PCH_DEVFN_I2C1:
return 1;
case PCH_DEVFN_I2C2:
return 2;
case PCH_DEVFN_I2C3:
return 3;
case PCH_DEVFN_I2C4:
return 4;
case PCH_DEVFN_I2C5:
return 5;
}
return -1;
}
int dw_i2c_soc_bus_to_devfn(unsigned int bus)
{
switch (bus) {
case 0:
return PCH_DEVFN_I2C0;
case 1:
return PCH_DEVFN_I2C1;
case 2:
return PCH_DEVFN_I2C2;
case 3:
return PCH_DEVFN_I2C3;
case 4:
return PCH_DEVFN_I2C4;
case 5:
return PCH_DEVFN_I2C5;
}
return -1;
}
|