summaryrefslogtreecommitdiff
path: root/src/soc/intel/common/Kconfig
blob: 43c52b5478ff28709d77ecd1b7c72be4fd20b862 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
config SOC_INTEL_COMMON
	bool
	help
	  common code for Intel SOCs

if SOC_INTEL_COMMON

config CACHE_MRC_SETTINGS
	bool "Save cached MRC settings"
	default n
	help
	  If CONFIG_USE_FMAP is enabled, it is assumed that a flashmap
	  containing an RW_MRC_CACHE entry that specifies the location and size
	  of the cache will be added to the image and present at runtime.

if CACHE_MRC_SETTINGS

config MRC_SETTINGS_CACHE_BASE
	hex
	depends on !USE_FMAP
	default 0xfffe0000

config MRC_SETTINGS_CACHE_SIZE
	hex
	depends on !USE_FMAP
	default 0x10000

config MRC_SETTINGS_PROTECT
	bool "Enable protection on MRC settings"
	depends on !USE_FMAP
	default n

endif # CACHE_MRC_SETTINGS

config DISPLAY_MTRRS
	bool "MTRRs: Display the MTRR settings"
	default n

config DISPLAY_SMM_MEMORY_MAP
	bool "SMM: Display the SMM memory map"
	default n

config SOC_INTEL_COMMON_FSP_RAM_INIT
	bool "FSP: Use the common raminit.c module"
	default n
	depends on PLATFORM_USES_FSP1_1

config SOC_INTEL_COMMON_FSP_ROMSTAGE
	bool
	default n
	depends on PLATFORM_USES_FSP1_1

config SOC_INTEL_COMMON_RESET
	bool
	default n

config SOC_INTEL_COMMON_STACK
	bool
	default n
	depends on PLATFORM_USES_FSP1_1

config SOC_INTEL_COMMON_STAGE_CACHE
	bool
	default n
	depends on PLATFORM_USES_FSP1_1

config ROMSTAGE_RAM_STACK_SIZE
	hex "Size of the romstage RAM stack in bytes"
	default 0x5000
	depends on SOC_INTEL_COMMON_STACK

config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
	bool
	default n

endif # SOC_INTEL_COMMON