blob: 58e2c7e0540d457ebfc1f607d6c6db3b74a17495 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <commonlib/helpers.h>
#include <intelblocks/systemagent.h>
#include <soc/pci_devs.h>
void bootblock_systemagent_early_init(void)
{
uint32_t reg;
uint8_t pciexbar_length;
/*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
reg = 0;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
/* Get PCI Express Region Length */
switch (CONFIG_SA_PCIEX_LENGTH) {
case 256 * MiB:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
break;
case 128 * MiB:
pciexbar_length = PCIEXBAR_LENGTH_128MB;
break;
case 64 * MiB:
pciexbar_length = PCIEXBAR_LENGTH_64MB;
break;
default:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
}
reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
| PCIEXBAR_PCIEXBAREN;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
/*
* TSEG defines the base of SMM range. BIOS determines the base
* of TSEG memory which must be at or below Graphics base of GTT
* Stolen memory, hence its better to clear TSEG register early
* to avoid power on default non-zero value (if any).
*/
pci_write_config32(SA_DEV_ROOT, TSEG, 0);
}
|
