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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <intelblocks/gpio.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
};
static const struct reset_mapping rst_map_com0[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
};
static const struct pad_group icl_community0_groups[] = {
INTEL_GPP(GPP_G0, GPP_G0, GPP_G7), /* GPP_G */
INTEL_GPP(GPP_G0, GPP_B0, GPP_B23), /* GPP_B */
INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),
INTEL_GPP(GPP_G0, GPP_A0, GPP_A23), /* GPP_A */
};
static const struct pad_group icl_community1_groups[] = {
INTEL_GPP(GPP_H0, GPP_H0, GPP_H23), /* GPP_H */
INTEL_GPP(GPP_H0, GPP_D0, GPIO_RSVD_2), /* GPP_D */
INTEL_GPP(GPP_H0, GPP_F0, GPP_F19), /* GPP_F */
};
static const struct pad_group icl_community2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
};
static const struct pad_group icl_community4_groups[] = {
INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */
INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),
};
static const struct pad_group icl_community5_groups[] = {
INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */
INTEL_GPP(GPP_C0, GPP_S0, GPP_S7), /* GPP_S */
};
static const struct pad_community icl_communities[] = {
{ /* GPP G, B, A */
.port = PID_GPIOCOM0,
.first_pad = GPP_G0,
.last_pad = GPP_A23,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_GBA",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_com0,
.num_reset_vals = ARRAY_SIZE(rst_map_com0),
.groups = icl_community0_groups,
.num_groups = ARRAY_SIZE(icl_community0_groups),
}, { /* GPP H, D, F */
.port = PID_GPIOCOM1,
.first_pad = GPP_H0,
.last_pad = GPP_F19,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_HDF",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = icl_community1_groups,
.num_groups = ARRAY_SIZE(icl_community1_groups),
}, { /* GPD */
.port = PID_GPIOCOM2,
.first_pad = GPD0,
.last_pad = GPD11,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = icl_community2_groups,
.num_groups = ARRAY_SIZE(icl_community2_groups),
}, { /* GPP C, E */
.port = PID_GPIOCOM4,
.first_pad = GPP_C0,
.last_pad = GPP_E23,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_CE",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = icl_community4_groups,
.num_groups = ARRAY_SIZE(icl_community4_groups),
}, { /* GPP R, S */
.port = PID_GPIOCOM5,
.first_pad = GPP_R0,
.last_pad = GPP_S7,
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_RS",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = icl_community5_groups,
.num_groups = ARRAY_SIZE(icl_community5_groups),
}
};
const struct pad_community *soc_gpio_get_community(size_t *num_communities)
{
*num_communities = ARRAY_SIZE(icl_communities);
return icl_communities;
}
const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
{
static const struct pmc_to_gpio_route routes[] = {
{ PMC_GPP_G, GPP_G },
{ PMC_GPP_B, GPP_B },
{ PMC_GPP_A, GPP_A },
{ PMC_GPP_H, GPP_H },
{ PMC_GPP_D, GPP_D },
{ PMC_GPP_F, GPP_F },
{ PMC_GPD, GPD },
{ PMC_GPP_C, GPP_C },
{ PMC_GPP_E, GPP_E },
{ PMC_GPP_R, GPP_R },
{ PMC_GPP_S, GPP_S }
};
*num = ARRAY_SIZE(routes);
return routes;
}
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