summaryrefslogtreecommitdiff
path: root/src/soc/intel/quark/chip.c
blob: 77fb1fda0c2297ed85477bdfa03c5ca09a2095cb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2014 Google Inc.
 * Copyright (C) 2015-2016 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>

/* Cat Trip Clear value must be less than Cat Trip Set value */
#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS	105
#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS	65

static const struct reg_script thermal_init_script[] = {

	/* Setup RMU Thermal sensor registers for Ratiometric mode. */
	REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG,
		~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK
			| B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK
			| B_TSCGF1_CONFIG_ISNSINTERNALVREFEN
			| B_TSCGF1_CONFIG_IBGEN
			| B_TSCGF1_CONFIG_IBGCHOPEN),
		((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE
			<< B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP)
		| (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE
			<< B_TSCGF1_CONFIG_ISNSCHOPSEL_BP)
		| (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE
			<< B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP)
		| (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE
			<< B_TSCGF1_CONFIG_IBGEN_BP)
		| (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE
			<< B_TSCGF1_CONFIG_IBGCHOPEN_BP))),

	REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2,
		~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK
			| B_TSCGF2_CONFIG2_ISPARECTRL_MASK
			| B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK),
		((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE
			<< B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP)
		| (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE
			<< B_TSCGF2_CONFIG2_ISPARECTRL_BP)
		| (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE
			<< B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))),

	REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG,
		~(B_TSCGF2_CONFIG_IDSCONTROL_MASK
			| B_TSCGF2_CONFIG_IDSTIMING_MASK),
		((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE
			<< B_TSCGF2_CONFIG_IDSCONTROL_BP)
		| (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE
			<< B_TSCGF2_CONFIG_IDSTIMING_BP))),

	REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
		~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK,
		V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE
			<< B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP),

	/* Enable RMU Thermal sensor with a Catastrophic Trip point. */

	/* Set up Catastrophic Trip point.
	*
	* Trip Register fields are 8-bit temperature values of granularity 1
	* degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds
	* to 205 degrees C.
	*
	* Add 50 to Celsius values to get values for register fields.
	*/
	REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP,
		~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK),
		(((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50)
			<< TS_CAT_TRIP_SET_THOLD_BP)
		| ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50)
			<< TS_CAT_TRIP_CLEAR_THOLD_BP))),

	/* To enable the TS do the following:
	 *    1)  Take the TS out of reset by setting itsrst to 0x0.
	 *    2)  Enable the TS using RMU Thermal sensor mode register.
	 */
	REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
		~B_TSCGF3_CONFIG_ITSRST),
	REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE),

	/* Lock all RMU Thermal sensor control & trip point registers. */
	REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE
		| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE),
	REG_SCRIPT_END
};

static void chip_init(void *chip_info)
{
	/* Validate the temperature settings */
	ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
	ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
		> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);

	/* Set the temperature settings */
	reg_script_run(thermal_init_script);

	/* Verify that the thermal configuration is locked */
	ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
		& (TS_LOCK_THRM_CTRL_REGS_ENABLE
			| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
		== (TS_LOCK_THRM_CTRL_REGS_ENABLE
			| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));

	/* Perform silicon specific init. */
	fsp_silicon_init();
}

static void pci_domain_set_resources(device_t dev)
{
	assign_resources(dev->link_list);
}

static struct device_operations pci_domain_ops = {
	.read_resources	= pci_domain_read_resources,
	.set_resources	= pci_domain_set_resources,
	.scan_bus	= pci_domain_scan_bus,
	.ops_pci_bus	= pci_bus_default_ops,
};

static void chip_enable_dev(device_t dev)
{

	/* Set the operations if it is a special bus type */
	if (dev->path.type == DEVICE_PATH_DOMAIN)
		dev->ops = &pci_domain_ops;
}

struct chip_operations soc_intel_quark_ops = {
	CHIP_NAME("Intel Quark")
	.init		= &chip_init,
	.enable_dev	= chip_enable_dev,
};