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/*
* This file is part of the coreboot project.
*
* Copyright 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_SKL_PCR_H
#define SOC_INTEL_SKL_PCR_H
/*
* Port ids
*/
#define PID_PSTH 0x89
#define PID_GPIOCOM3 0xAC
#define PID_GPIOCOM2 0xAD
#define PID_GPIOCOM1 0xAE
#define PID_GPIOCOM0 0xAF
#define PID_PSF1 0xBA
#define PID_SCS 0xC0
#define PID_RTC 0xC3
#define PID_ITSS 0xC4
#define PID_LPC 0xC7
#define PID_SERIALIO 0xCB
#define PID_DMI 0xEF
#endif /* SOC_INTEL_SKL_PCR_H */
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