1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <cpu/x86/msr.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/systemagent.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
#include "chip.h"
bool soc_is_vtd_capable(void)
{
struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
return root_dev &&
!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
}
/*
* SoC implementation
*
* Add all known fixed memory ranges for Host Controller/Memory
* controller.
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
};
const struct soc_intel_skylake_config *const config = config_of(dev);
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
ARRAY_SIZE(soc_fixed_resources));
if (!config->ignore_vtd && soc_is_vtd_capable()) {
if (igd_dev && igd_dev->enabled)
sa_add_fixed_mmio_resources(dev, index,
&soc_gfxvt_mmio_descriptor, 1);
sa_add_fixed_mmio_resources(dev, index,
&soc_vtvc0_mmio_descriptor, 1);
}
}
/*
* SoC implementation
*
* Perform System Agent Initialization during Ramstage phase.
*/
void soc_systemagent_init(struct device *dev)
{
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
/* Enable BIOS Reset CPL */
enable_bios_reset_cpl();
/* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
set_power_limits(28);
}
int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
uint64_t *prmrr_mask)
{
msr_t msr;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
*prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
*prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
return 0;
}
|
