summaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp/Kconfig
blob: 49af38454fd57b1a05d7015f9ae7bcf66c77dcc9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
# SPDX-License-Identifier: GPL-2.0-or-later

source "src/soc/intel/xeon_sp/skx/Kconfig"
source "src/soc/intel/xeon_sp/cpx/Kconfig"

config XEON_SP_COMMON_BASE
	bool

config SOC_INTEL_SKYLAKE_SP
	bool
	select XEON_SP_COMMON_BASE
	select PLATFORM_USES_FSP2_0
	help
	  Intel Skylake-SP support

config SOC_INTEL_COOPERLAKE_SP
	bool
	select XEON_SP_COMMON_BASE
	select PLATFORM_USES_FSP2_2
	select CACHE_MRC_SETTINGS
	help
	  Intel Cooperlake-SP support

if XEON_SP_COMMON_BASE

config	CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_ALL_STAGES_X86_32
	select BOOT_DEVICE_SUPPORTS_WRITES
	select CPU_INTEL_COMMON
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_RESET
	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
	select FSP_T_XIP
	select FSP_M_XIP
	select POSTCAR_STAGE
	select IOAPIC
	select PARALLEL_MP
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select SOC_INTEL_COMMON_BLOCK
	select SOC_INTEL_COMMON_BLOCK_CPU
	select SOC_INTEL_COMMON_BLOCK_DMI
	select SOC_INTEL_COMMON_BLOCK_TIMER
	select SOC_INTEL_COMMON_BLOCK_LPC
	select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
	select SOC_INTEL_COMMON_BLOCK_RTC
	select SOC_INTEL_COMMON_BLOCK_SPI
	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
	select SOC_INTEL_COMMON_BLOCK_GPIO
	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
	select SOC_INTEL_COMMON_BLOCK_PCR
	select SOC_INTEL_COMMON_BLOCK_P2SB
	select SOC_INTEL_COMMON_BLOCK_PMC
	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
	select SOC_INTEL_COMMON_BLOCK_SMM
	select SOC_INTEL_COMMON_BLOCK_TCO
	select SOC_INTEL_COMMON_BLOCK_ACPI
	select TSC_MONOTONIC_TIMER
	select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT
	select UDELAY_TSC
	select SUPPORT_CPU_UCODE_IN_CBFS
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select FSP_CAR
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select SMM_TSEG
	select HAVE_SMI_HANDLER
	select X86_SMM_LOADER_VERSION2
	select REG_SCRIPT
	select NO_FSP_TEMP_RAM_EXIT
	select INTEL_CAR_NEM # For postcar only now

config MAINBOARD_USES_FSP2_0
	  bool
	  default y

config USE_FSP2_0_DRIVER
	  def_bool y
	  depends on MAINBOARD_USES_FSP2_0
	  select PLATFORM_USES_FSP2_0
	  select UDK_202005_BINDING
	  select POSTCAR_STAGE

config MAX_SOCKET
	int
	default 2

# For 2S config, the number of cpus could be as high as
# 2 threads * 20 cores * 2 sockets
config MAX_CPUS
	int
	default 80

config PCR_BASE_ADDRESS
	hex
	default 0xfd000000
	help
	  This option allows you to select MMIO Base Address of sideband bus.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x10000

config MMCONF_BASE_ADDRESS
	default 0x80000000

config HEAP_SIZE
	hex
	default 0x80000

endif ## SOC_INTEL_XEON_SP