1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
|
/*
* This file is part of the coreboot project.
*
* Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <gpio.h>
enum {
GPIO_DIRECTION_IN = 0,
GPIO_DIRECTION_OUT = 1,
};
enum {
GPIO_MODE = 0,
};
static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
{
*pos = gpio.id / MAX_GPIO_REG_BITS;
*bit = gpio.id % MAX_GPIO_REG_BITS;
}
static void pos_bit_calc_for_mode(gpio_t gpio, u32 *pos, u32 *bit)
{
*pos = gpio.id / MAX_GPIO_MODE_PER_REG;
*bit = (gpio.id % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
}
static s32 gpio_set_dir(gpio_t gpio, u32 dir)
{
u32 pos;
u32 bit;
u32 *reg;
pos_bit_calc(gpio, &pos, &bit);
if (dir == GPIO_DIRECTION_IN)
reg = &mtk_gpio->dir[pos].rst;
else
reg = &mtk_gpio->dir[pos].set;
write32(reg, 1L << bit);
return 0;
}
void gpio_set_mode(gpio_t gpio, int mode)
{
u32 pos;
u32 bit;
u32 mask = (1L << GPIO_MODE_BITS) - 1;
pos_bit_calc_for_mode(gpio, &pos, &bit);
clrsetbits_le32(&mtk_gpio->mode[pos].val,
mask << bit, mode << bit);
}
int gpio_get(gpio_t gpio)
{
u32 pos;
u32 bit;
u32 *reg;
u32 data;
pos_bit_calc(gpio, &pos, &bit);
reg = &mtk_gpio->din[pos].val;
data = read32(reg);
return (data & (1L << bit)) ? 1 : 0;
}
void gpio_set(gpio_t gpio, int output)
{
u32 pos;
u32 bit;
u32 *reg;
pos_bit_calc(gpio, &pos, &bit);
if (output == 0)
reg = &mtk_gpio->dout[pos].rst;
else
reg = &mtk_gpio->dout[pos].set;
write32(reg, 1L << bit);
}
void gpio_input_pulldown(gpio_t gpio)
{
gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
gpio_set_dir(gpio, GPIO_DIRECTION_IN);
gpio_set_mode(gpio, GPIO_MODE);
}
void gpio_input_pullup(gpio_t gpio)
{
gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
gpio_set_dir(gpio, GPIO_DIRECTION_IN);
gpio_set_mode(gpio, GPIO_MODE);
}
void gpio_input(gpio_t gpio)
{
gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
gpio_set_dir(gpio, GPIO_DIRECTION_IN);
gpio_set_mode(gpio, GPIO_MODE);
}
void gpio_output(gpio_t gpio, int value)
{
gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
gpio_set(gpio, value);
gpio_set_dir(gpio, GPIO_DIRECTION_OUT);
gpio_set_mode(gpio, GPIO_MODE);
}
enum {
MAX_EINT_REG_BITS = 32,
};
static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit)
{
*pos = gpio.id / MAX_EINT_REG_BITS;
*bit = gpio.id % MAX_EINT_REG_BITS;
}
int gpio_eint_poll(gpio_t gpio)
{
u32 pos;
u32 bit;
u32 status;
pos_bit_calc_for_eint(gpio, &pos, &bit);
status = (read32(&mtk_eint->sta.regs[pos]) >> bit) & 0x1;
if (status)
write32(&mtk_eint->ack.regs[pos], 1 << bit);
return status;
}
void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
{
u32 pos;
u32 bit, mask;
pos_bit_calc_for_eint(gpio, &pos, &bit);
mask = 1 << bit;
/* Make it an input first. */
gpio_input_pullup(gpio);
write32(&mtk_eint->d0en[pos], mask);
switch (type) {
case IRQ_TYPE_EDGE_FALLING:
write32(&mtk_eint->sens_clr.regs[pos], mask);
write32(&mtk_eint->pol_clr.regs[pos], mask);
break;
case IRQ_TYPE_EDGE_RISING:
write32(&mtk_eint->sens_clr.regs[pos], mask);
write32(&mtk_eint->pol_set.regs[pos], mask);
break;
case IRQ_TYPE_LEVEL_LOW:
write32(&mtk_eint->sens_set.regs[pos], mask);
write32(&mtk_eint->pol_clr.regs[pos], mask);
break;
case IRQ_TYPE_LEVEL_HIGH:
write32(&mtk_eint->sens_set.regs[pos], mask);
write32(&mtk_eint->pol_set.regs[pos], mask);
break;
}
write32(&mtk_eint->mask_clr.regs[pos], mask);
}
|
