1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
|
/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_MEDIATEK_MT8173_PLL_H
#define SOC_MEDIATEK_MT8173_PLL_H
#include <soc/emi.h>
#include <soc/addressmap.h>
struct mt8173_topckgen_regs {
u32 clk_mode;
u32 dcm_cfg;
u32 reserved1[6];
u32 tst_sel_0; /* 0x020 */
u32 tst_sel_1;
u32 tst_sel_2;
u32 reserved2[5];
u32 clk_cfg_0; /* 0x040 */
u32 clk_cfg_0_set;
u32 clk_cfg_0_clr;
u32 reserved3[1];
u32 clk_cfg_1; /* 0x050 */
u32 clk_cfg_1_set;
u32 clk_cfg_1_clr;
u32 reserved4[1];
u32 clk_cfg_2; /* 0x060 */
u32 clk_cfg_2_set;
u32 clk_cfg_2_clr;
u32 reserved5[1];
u32 clk_cfg_3; /* 0x070 */
u32 clk_cfg_3_set;
u32 clk_cfg_3_clr;
u32 reserved6[1];
u32 clk_cfg_4; /* 0x080 */
u32 clk_cfg_4_set;
u32 clk_cfg_4_clr;
u32 reserved7[1];
u32 clk_cfg_5; /* 0x090 */
u32 clk_cfg_5_set;
u32 clk_cfg_5_clr;
u32 reserved8[1];
u32 clk_cfg_6; /* 0x0a0 */
u32 clk_cfg_6_set;
u32 clk_cfg_6_clr;
u32 reserved9[1];
u32 clk_cfg_7; /* 0x0b0 */
u32 clk_cfg_7_set;
u32 clk_cfg_7_clr;
u32 reserved10[1];
u32 clk_cfg_12; /* 0x0c0 */
u32 clk_cfg_12_set;
u32 clk_cfg_12_clr;
u32 reserved11[1];
u32 clk_cfg_13; /* 0x0d0 */
u32 clk_cfg_13_set;
u32 clk_cfg_13_clr;
u32 reserved12[9];
u32 clk_cfg_8; /* 0x100 */
u32 clk_cfg_9;
u32 clk_cfg_10;
u32 clk_cfg_11;
u32 reserved13[4];
u32 clk_auddiv_0; /* 0x120 */
u32 clk_auddiv_1;
u32 clk_auddiv_2;
u32 clk_auddiv_3;
u32 clk_mjcdiv_0;
u32 reserved14[51];
u32 clk_scp_cfg_0; /* 0x200 */
u32 clk_scp_cfg_1;
u32 reserved15[2];
u32 clk_misc_cfg_0; /* 0x210 */
u32 clk_misc_cfg_1;
u32 clk_misc_cfg_2;
u32 reserved16[1];
u32 clk26cali_0; /* 0x220 */
u32 clk26cali_1;
u32 clk26cali_2;
u32 cksta_reg;
u32 test_mode_cfg;
u32 reserved17[53];
u32 mbist_cfg_0; /* 0x308 */
u32 mbist_cfg_1;
u32 reset_deglitch_key;
u32 mbist_cfg_3; /* 0x314 */
};
check_member(mt8173_topckgen_regs, clk_cfg_0, 0x40);
check_member(mt8173_topckgen_regs, clk_cfg_8, 0x100);
check_member(mt8173_topckgen_regs, clk_scp_cfg_0, 0x200);
check_member(mt8173_topckgen_regs, mbist_cfg_3, 0x314);
struct mt8173_apmixed_regs {
u32 ap_pll_con0;
u32 reserved1[1];
u32 ap_pll_con2; /* 0x008 */
u32 ap_pll_con3;
u32 ap_pll_con4;
u32 ap_pll_con5;
u32 ap_pll_con6;
u32 ap_pll_con7;
u32 clksq_stb_con0;
u32 pll_pwr_con0;
u32 pll_pwr_con1;
u32 pll_iso_con0;
u32 pll_iso_con1;
u32 pll_stb_con0;
u32 div_stb_con0;
u32 pll_chg_con0;
u32 pll_test_con0;
u32 pll_test_con1; /* 0x044 */
u32 reserved2[110];
u32 armca15pll_con0; /* 0x200 */
u32 armca15pll_con1;
u32 armca15pll_con2;
u32 armca15pll_pwr_con0;
u32 armca7pll_con0;
u32 armca7pll_con1;
u32 armca7pll_con2;
u32 armca7pll_pwr_con0;
u32 mainpll_con0;
u32 mainpll_con1;
u32 mainpll_con2;
u32 mainpll_pwr_con0;
u32 univpll_con0;
u32 univpll_con1;
u32 univpll_con2;
u32 univpll_pwr_con0;
u32 mmpll_con0;
u32 mmpll_con1;
u32 mmpll_con2;
u32 mmpll_pwr_con0;
u32 msdcpll_con0;
u32 msdcpll_con1;
u32 msdcpll_con2;
u32 msdcpll_pwr_con0;
u32 vencpll_con0;
u32 vencpll_con1;
u32 vencpll_con2;
u32 vencpll_pwr_con0;
u32 tvdpll_con0;
u32 tvdpll_con1;
u32 tvdpll_con2;
u32 tvdpll_pwr_con0;
u32 mpll_con0;
u32 mpll_con1;
u32 mpll_con2;
u32 mpll_pwr_con0;
u32 vcodecpll_con0;
u32 vcodecpll_con1;
u32 vcodecpll_con2;
u32 vcodecpll_pwr_con0;
u32 apll1_con0;
u32 apll1_con1;
u32 apll1_con2;
u32 apll1_con3;
u32 apll1_pwr_con0;
u32 apll2_con0;
u32 apll2_con1;
u32 apll2_con2;
u32 apll2_con3;
u32 apll2_pwr_con0;
u32 reserved3[2];
u32 lvdspll_con0; /* 0x2d0 */
u32 lvdspll_con1;
u32 lvdspll_con2;
u32 lvdspll_pwr_con0;
u32 lvdspll_ssc_con0;
u32 lvdspll_ssc_con1;
u32 lvdspll_ssc_con2;
u32 reserved4[1];
u32 msdcpll2_con0; /* 0x2f0 */
u32 msdcpll2_con1;
u32 msdcpll2_con2;
u32 msdcpll2_pwr_con0; /* 0x2fc */
};
check_member(mt8173_apmixed_regs, ap_pll_con2, 0x8);
check_member(mt8173_apmixed_regs, armca15pll_con0, 0x200);
check_member(mt8173_apmixed_regs, msdcpll2_pwr_con0, 0x2fc);
static struct mt8173_topckgen_regs *const mt8173_topckgen = (void *)CKSYS_BASE;
static struct mt8173_apmixed_regs *const mt8173_apmixed = (void *)APMIXED_BASE;
/* PLL rate */
enum {
ARMCA15PLL_HZ = 851500 * KHz,
ARMCA7PLL_HZ = 1105 * MHz,
MAINPLL_HZ = 1092 * MHz,
UNIVPLL_HZ = 1248 * MHz,
MMPLL_HZ = 455 * MHz,
MSDCPLL_HZ = 800 * MHz,
VENCPLL_HZ = 660 * MHz,
TVDPLL_HZ = 1782 * MHz,
MPLL_HZ = 1456 * MHz,
VCODECPLL_HZ = 1104 * MHz,
LVDSPLL_HZ = 150 * MHz,
MSDCPLL2_HZ = 800 * MHz,
APLL1_HZ = 180633600,
APLL2_HZ = 196608 * KHz,
};
/* top_div rate */
enum {
AD_HDMITX_CLK_HZ = TVDPLL_HZ / 12,
AD_LVDSPLL_CK_HZ = LVDSPLL_HZ,
APLL1_CK_HZ = APLL1_HZ,
APLL2_CK_HZ = APLL2_HZ,
CLK26M_HZ = 26 * MHz,
CLKRTC_EXT_HZ = 32 * KHz,
MMPLL_CK_HZ = MMPLL_HZ,
MSDCPLL_D4_HZ = MSDCPLL_HZ / 4,
SYSPLL1_D2_HZ = MAINPLL_HZ / 4,
SYSPLL1_D4_HZ = MAINPLL_HZ / 8,
SYSPLL2_D2_HZ = MAINPLL_HZ / 6,
SYSPLL3_D2_HZ = MAINPLL_HZ / 10,
SYSPLL3_D4_HZ = MAINPLL_HZ / 20,
SYSPLL_D2_HZ = MAINPLL_HZ / 2,
TVDPLL_D2_HZ = TVDPLL_HZ / 2,
UNIVPLL1_D2_HZ = UNIVPLL_HZ / 4,
UNIVPLL1_D8_HZ = UNIVPLL_HZ / 16,
UNIVPLL2_D2_HZ = UNIVPLL_HZ / 6,
UNIVPLL2_D4_HZ = UNIVPLL_HZ / 12,
UNIVPLL3_D2_HZ = UNIVPLL_HZ / 10,
UNIVPLL_D52_HZ = UNIVPLL_HZ / 52,
VCODECPLL_CK_HZ = VCODECPLL_HZ / 3,
VENCPLL_D2_HZ = VENCPLL_HZ / 2,
};
/* top_mux rate */
enum {
AXI_HZ = UNIVPLL2_D2_HZ,
MEM_HZ = CLK26M_HZ,
DDRPHYCFG_HZ = CLK26M_HZ,
MM_HZ = VENCPLL_D2_HZ,
PWM_HZ = CLK26M_HZ,
VDEC_HZ = VCODECPLL_CK_HZ,
VENC_HZ = VCODECPLL_CK_HZ,
MFG_HZ = MMPLL_CK_HZ,
CAMTG_HZ = CLK26M_HZ,
UART_HZ = CLK26M_HZ,
SPI_HZ = SYSPLL3_D2_HZ,
USB20_HZ = UNIVPLL1_D8_HZ,
MSDC30_2_HZ = MSDCPLL_D4_HZ,
MSDC30_3_HZ = MSDCPLL_D4_HZ,
AUDIO_HZ = CLK26M_HZ,
AUD_INTBUS_HZ = SYSPLL1_D4_HZ,
PMICSPI_HZ = CLK26M_HZ,
SCP_HZ = SYSPLL1_D2_HZ,
ATB_HZ = CLK26M_HZ,
VENC_LT_HZ = UNIVPLL1_D2_HZ,
DPI0_HZ = TVDPLL_D2_HZ,
IRDA_HZ = UNIVPLL2_D4_HZ,
CCI400_HZ = SYSPLL_D2_HZ,
AUD_1_HZ = APLL1_CK_HZ,
AUD_2_HZ = APLL2_CK_HZ,
MEM_MFG_IN_HZ = MMPLL_CK_HZ,
AXI_MFG_IN_HZ = AXI_HZ,
SCAM_HZ = SYSPLL3_D2_HZ,
SPINFI_IFR_HZ = CLK26M_HZ,
HDMI_HZ = AD_HDMITX_CLK_HZ,
DPILVDS_HZ = AD_LVDSPLL_CK_HZ,
MSDC50_2_H_HZ = SYSPLL2_D2_HZ,
HDCP_HZ = SYSPLL3_D4_HZ,
HDCP_24M_HZ = UNIVPLL_D52_HZ,
RTC_HZ = CLKRTC_EXT_HZ,
USB30_HZ = UNIVPLL3_D2_HZ,
MSDC50_0_H_HZ = SYSPLL2_D2_HZ,
MSDC50_0_HZ = MSDCPLL_D4_HZ,
MSDC30_1_HZ = MSDCPLL_D4_HZ,
};
void mt_pll_post_init(void);
void mt_pll_init(void);
void mt_pll_set_aud_div(u32 rate);
void mt_pll_enable_ssusb_clk(void);
void mt_mem_pll_set_clk_cfg(void);
void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params);
void mt_mem_pll_config_post(void);
void mt_mem_pll_mux(void);
#endif /* SOC_MEDIATEK_MT8173_PLL_H */
|