blob: eaf1cf4a0701ab23c1ecd1529e1d605b8058fa6d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_MEDIATEK_MT8183_DSI_H
#define SOC_MEDIATEK_MT8183_DSI_H
#include <soc/dsi_common.h>
/* DSI features */
#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
#define MTK_DSI_DATA_RATE_MIN_MHZ 125
#define MTK_DSI_HAVE_SIZE_CON 1
#define PIXEL_STREAM_CUSTOM_HEADER 0xb
/* MIPITX is SOC specific and cannot live in common. */
/* MIPITX_REG */
struct mipi_tx_regs {
u32 reserved0[3];
u32 lane_con;
u32 reserved1[6];
u32 pll_pwr;
u32 pll_con0;
u32 pll_con1;
u32 pll_con2;
u32 pll_con3;
u32 pll_con4;
u32 reserved2[65];
u32 d2_sw_ctl_en;
u32 reserved3[63];
u32 d0_sw_ctl_en;
u32 reserved4[56];
u32 ck_ckmode_en;
u32 reserved5[6];
u32 ck_sw_ctl_en;
u32 reserved6[63];
u32 d1_sw_ctl_en;
u32 reserved7[63];
u32 d3_sw_ctl_en;
};
check_member(mipi_tx_regs, pll_con4, 0x3c);
check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
/* Register values */
#define DSI_CK_CKMODE_EN BIT(0)
#define DSI_SW_CTL_EN BIT(0)
#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
#define RG_DSI_PLL_EN BIT(4)
#define RG_DSI_PLL_POSDIV (0x7 << 8)
#endif
|
