summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra/apbmisc.c
blob: 3fc0ef7de18d19b1841143be868346ae7ed5dbf7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/*
 * This file is part of the coreboot project.
 *
 * Copyright 2014 Google Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 */

#include <arch/io.h>
#include <soc/addressmap.h>

#include "apbmisc.h"

static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;

void enable_jtag(void)
{
	write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
}

void clamp_tristate_inputs(void)
{
	write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
}

void tegra_revision_info(struct tegra_revision *id)
{
	uintptr_t gp_hidrev= (uintptr_t)TEGRA_APB_MISC_BASE + MISC_GP_HIDREV;
	uint32_t reg;

	reg = read32((void *)(gp_hidrev));

	id->hid_fam = (reg >> 0) & 0x0f;
	id->chip_id = (reg >> 8) & 0xff;
	id->major = (reg >> 4) & 0x0f;
	id->minor = (reg >> 16) & 0x07;
}