summaryrefslogtreecommitdiff
path: root/src/soc/rockchip/common/gpio.c
blob: a2bc29b22549fa67e03da29fc9ebf2c6ad107c4f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
/*
 * This file is part of the coreboot project.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <device/mmio.h>
#include <assert.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <soc/grf.h>
#include <soc/soc.h>
#include <types.h>

static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir)
{
	clrsetbits32(&gpio_port[gpio.port]->swporta_ddr,
		     1 << gpio.num, dir << gpio.num);
}

static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull)
{
	u32 pull_val = gpio_get_pull_val(gpio, pull);
	if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288))
		clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2),
			     pull_val << (gpio.idx * 2));
	else
		write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2),
			pull_val << (gpio.idx * 2)));
}

void gpio_input(gpio_t gpio)
{
	gpio_set_pull(gpio, GPIO_PULLNONE);
	gpio_set_dir(gpio, GPIO_INPUT);
}

void gpio_input_pulldown(gpio_t gpio)
{
	gpio_set_pull(gpio, GPIO_PULLDOWN);
	gpio_set_dir(gpio, GPIO_INPUT);
}

void gpio_input_pullup(gpio_t gpio)
{
	gpio_set_pull(gpio, GPIO_PULLUP);
	gpio_set_dir(gpio, GPIO_INPUT);
}

void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull)
{
	uint32_t int_polarity, inttype_level;
	uint32_t mask = BIT(gpio.num);

	/* gpio pull only PULLNONE, PULLUP, PULLDOWN status */
	assert(pull <= GPIO_PULLDOWN);

	gpio_set_dir(gpio, GPIO_INPUT);
	gpio_set_pull(gpio, pull);

	int_polarity = inttype_level = 0;
	switch (type) {
		case IRQ_TYPE_EDGE_RISING:
			int_polarity = mask;
			inttype_level = mask;
			break;
		case IRQ_TYPE_EDGE_FALLING:
			inttype_level = mask;
			break;
		case IRQ_TYPE_LEVEL_HIGH:
			int_polarity = mask;
			break;
		case IRQ_TYPE_LEVEL_LOW:
			break;
	}
	clrsetbits32(&gpio_port[gpio.port]->int_polarity,
		     mask, int_polarity);
	clrsetbits32(&gpio_port[gpio.port]->inttype_level,
		     mask, inttype_level);

	setbits32(&gpio_port[gpio.port]->inten, mask);
	clrbits32(&gpio_port[gpio.port]->intmask, mask);
}

int gpio_irq_status(gpio_t gpio)
{
	uint32_t mask = BIT(gpio.num);
	uint32_t int_status = read32(&gpio_port[gpio.port]->int_status);

	if (!(int_status & mask))
		return 0;

	setbits32(&gpio_port[gpio.port]->porta_eoi, mask);
	return 1;
}

int gpio_get(gpio_t gpio)
{
	return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
}

void gpio_set(gpio_t gpio, int value)
{
	clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
							!!value << gpio.num);
}

void gpio_output(gpio_t gpio, int value)
{
	gpio_set(gpio, value);
	gpio_set_dir(gpio, GPIO_OUTPUT);
	gpio_set_pull(gpio, GPIO_PULLNONE);
}