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##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config SOC_ROCKCHIP_RK3288
bool
default n
select ARCH_BOOTBLOCK_ARMV7
select ARCH_VERSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select CPU_HAS_BOOTBLOCK_INIT
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_UART_MEMORY_MAPPED
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
if SOC_ROCKCHIP_RK3288
config BOOTBLOCK_CPU_INIT
string
default "soc/rockchip/rk3288/bootblock.c"
# ROM image layout.
#
# 0x00000 Combined bootblock and ID Block
# 0x08000 Master CBFS header.
# 0x18000 Free for CBFS data.
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
config CBFS_HEADER_ROM_OFFSET
hex
default 0x0010000
config CBFS_ROM_OFFSET
hex
default 0x0010100
endif
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