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# This file is part of the coreboot project.
#
# Copyright (C) 2018 Jonathan Neuschäfer
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
config SOC_SIFIVE_FU540
bool
select ARCH_RISCV
select ARCH_RISCV_RV64
select ARCH_RISCV_S
select ARCH_RISCV_U
select ARCH_RISCV_PMP
select ARCH_BOOTBLOCK_RISCV
select ARCH_VERSTAGE_RISCV
select ARCH_ROMSTAGE_RISCV
select ARCH_RAMSTAGE_RISCV
select DRIVERS_UART_SIFIVE
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select RISCV_USE_ARCH_TIMER
select UART_OVERRIDE_REFCLK
if SOC_SIFIVE_FU540
config RISCV_ARCH
string
default "rv64imac"
config RISCV_ABI
string
default "lp64"
config RISCV_CODEMODEL
string
default "medany"
config MAX_CPUS
int
default 5
config RISCV_WORKING_HARTID
int
default 0
endif
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