summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/amd8111/early_ctrl.c
blob: 2161669f4fdef1a6220bd51f89a3f07ecab3af67 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
#include "amd8111.h"
#include <reset.h>

/* by yhlu 2005.10 */
unsigned get_sbdn(unsigned bus)
{
	pci_devfn_t dev;

	/* Find the device.
	 * There can only be one 8111 on a hypertransport chain/bus.
	 */
	dev = pci_locate_device_on_bus(
		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
		bus);

	return (dev>>15) & 0x1f;

}

static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
{
	pci_devfn_t dev;
	uint8_t byte;

	dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
	/* enable cf9 */
	byte = pci_read_config8(dev, 0x41);
	byte |= (1<<6) | (1<<5);
	pci_write_config8(dev, 0x41, byte);
}

static void enable_cf9(void)
{
	unsigned sblk = get_sblk();
	unsigned sbbusn = get_sbbusn(sblk);
	unsigned sbdn = get_sbdn(sbbusn);

	enable_cf9_x(sbbusn, sbdn);
}

void do_hard_reset(void)
{
	set_bios_reset();
	/* reset */
	enable_cf9();
	outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}

void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
	pci_devfn_t dev;

	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI

	pci_write_config8(dev, 0x74, 4);

	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
	pci_write_config32(dev, 0x70, 2<<12);

}

static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
{
	pci_devfn_t dev;

	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA

	/* Reset */
	set_bios_reset();
	pci_write_config8(dev, 0x47, 1);

}

void do_soft_reset(void)
{

	unsigned sblk = get_sblk();
	unsigned sbbusn = get_sbbusn(sblk);
	unsigned sbdn = get_sbdn(sbbusn);

	return soft_reset_x(sbbusn, sbdn);

}