blob: 4e40dd49f57cec5c0650375c1ff51add8acf2ece (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <watchdog.h>
/*
* Disable PCH watchdog timer
*/
void watchdog_off(void)
{
unsigned int value;
struct device *dev;
/* Get LPC device. */
dev = pcidev_on_root(0x1f, 0);
/* Disable interrupt. */
value = pci_read_config16(dev, PCI_COMMAND);
value |= PCI_COMMAND_INT_DISABLE;
pci_write_config16(dev, PCI_COMMAND, value);
/* Disable the watchdog timer. */
value = read_pmbase16(TCO1_CNT);
value |= TCO_TMR_HLT;
write_pmbase16(TCO1_CNT, value);
/* Clear TCO timeout status. */
write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
write_pmbase16(TCO2_STS, SECOND_TO_STS);
/* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */
printk(BIOS_DEBUG, "PCH: watchdog disabled\n");
}
|
