summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/common/watchdog.c
blob: b43348eda536e01f771afae094cfe2a6c2494e5f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/tco.h>
#include <watchdog.h>

/*
 *  Disable ICH-NM10-PCH watchdog timer
 */
void watchdog_off(void)
{
	unsigned int value;
	struct device *dev;

	/* Get LPC device. */
	dev = pcidev_on_root(0x1f, 0);

	value = pci_read_config16(dev, PCI_COMMAND);

	/* Disable interrupt. */
	value |= PCI_COMMAND_INT_DISABLE;
	pci_write_config16(dev, PCI_COMMAND, value);

	/* Disable the watchdog timer. */
	value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
	value |= TCO_TMR_HLT;
	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);

	/* Clear TCO timeout status. */
	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);

	printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
}