summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801ax/i82801ax_smbus.h
blob: 06d987721f6a86fa3393d5423b4d6a15b89d68aa (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <device/smbus_def.h>

static void smbus_delay(void)
{
	inb(0x80);
}

static int smbus_wait_until_ready(void)
{
	unsigned loops = SMBUS_TIMEOUT;
	unsigned char byte;
	do {
		smbus_delay();
		if (--loops == 0)
			break;
		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
	} while (byte & 1);
	return loops ? 0 : -1;
}

static int smbus_wait_until_done(void)
{
	unsigned loops = SMBUS_TIMEOUT;
	unsigned char byte;
	do {
		smbus_delay();
		if (--loops == 0)
			break;
		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
	return loops ? 0 : -1;
}

static int smbus_wait_until_blk_done(void)
{
	unsigned loops = SMBUS_TIMEOUT;
	unsigned char byte;
	do {
		smbus_delay();
		if (--loops == 0)
			break;
		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
	} while ((byte & (1 << 7)) == 0);
	return loops ? 0 : -1;
}

static int do_smbus_read_byte(unsigned device, unsigned address)
{
	unsigned char global_status_register;
	unsigned char byte;

	if (smbus_wait_until_ready() < 0) {
		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
	}
	/* Setup transaction */
	/* Disable interrupts */
	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
	/* Set the device I'm talking too */
	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
	/* Set the command/address... */
	outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
	/* Set up for a byte data read */
	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
	     (SMBUS_IO_BASE + SMBHSTCTL));
	/* Clear any lingering errors, so the transaction will run */
	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);

	/* Clear the data byte... */
	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);

	/* Start the command */
	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
	     SMBUS_IO_BASE + SMBHSTCTL);

	/* Poll for transaction completion */
	if (smbus_wait_until_done() < 0) {
		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
	}

	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);

	/* Ignore the "In Use" status... */
	global_status_register &= ~(3 << 5);

	/* Read results of transaction */
	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
	if (global_status_register != (1 << 1)) {
		return SMBUS_ERROR;
	}
	return byte;
}

static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
				unsigned data1, unsigned data2)
{
	unsigned char global_control_register;
	unsigned char global_status_register;
	unsigned char byte;
	unsigned char stat;
	int i;

	print_err("Untested smbus_write_block called\n");

	/* Clear the PM timeout flags, SECOND_TO_STS */
	outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66);

	if (smbus_wait_until_ready() < 0) {
		return -2;
	}

	/* Setup transaction */
	/* Obtain ownership */
	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
	for (stat = 0; (stat & 0x40) == 0;) {
		stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
	}
	/* Clear the done bit */
	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
	/* Disable interrupts */
	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);

	/* Set the device I'm talking too */
	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);

	/* Set the command address */
	outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD);

	/* Set the block length */
	outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0);

	/* Try sending out the first byte of data here */
	byte = (data1 >> (0)) & 0x0ff;
	outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
	/* Issue a block write command */
	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
	     SMBUS_IO_BASE + SMBHSTCTL);

	for (i = 0; i < length; i++) {
		/* Poll for transaction completion */
		if (smbus_wait_until_blk_done() < 0) {
			return -3;
		}

		/* Load the next byte */
		if (i > 3)
			byte = (data2 >> (i % 4)) & 0x0ff;
		else
			byte = (data1 >> (i)) & 0x0ff;
		outb(byte, SMBUS_IO_BASE + SMBBLKDAT);

		/* Clear the done bit */
		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
		     SMBUS_IO_BASE + SMBHSTSTAT);
	}

	print_debug("SMBUS Block complete\n");
	return 0;
}