blob: fdbb7d2d0d00ed8ce9bee59df79702413124546f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
#ifndef I82801DX_CHIP_H
#define I82801DX_CHIP_H
struct southbridge_intel_i82801dx_config
{
int enable_usb;
int enable_native_ide;
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
*/
uint8_t pirqa_routing;
uint8_t pirqb_routing;
uint8_t pirqc_routing;
uint8_t pirqd_routing;
uint8_t pirqe_routing;
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
uint8_t ide0_enable;
uint8_t ide1_enable;
};
extern struct chip_operations southbridge_intel_i82801dx_ops;
#endif /* I82801DBM_CHIP_H */
|