summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801er/i82801er.c
blob: 0e4e3b3a56f6c3fdafe7207c070982f056b4766d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801er.h"

void i82801er_enable(device_t dev)
{
	device_t lpc_dev;
	unsigned int index;
	uint16_t reg_old, reg;

//	all 82801er device ares in bus 0
	unsigned int devfn;
	devfn = PCI_DEVFN(0x1f, 0); // lpc
	lpc_dev = dev_find_slot(0, devfn); // 0
	if (!lpc_dev ) {
		return;
	}
#if 0
	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
	    (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) {
		uint32_t id;
		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
		if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) {
			return;
		}
	}
#endif

	index = (dev->path.u.pci.devfn & 7);
        if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f
                if(index==0){   //1f0   
                        index = 14;
                } 
        } else { // D=0x1d
                index += 8;
        }

	reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
	reg = reg_old;
	reg &= ~(1<<index); // enable it
	if (!dev->enabled) {
		reg |= (1<<index);  // disable it
	}
	if (reg != reg_old) {
		pci_write_config16(lpc_dev, FUNC_DIS, reg);
	}
	reg = pci_read_config16(lpc_dev, FUNC_DIS);

}

struct chip_control southbridge_intel_i82801er_control = {
	.name       = "Intel 82801er Southbridge",
	.enable_dev = i82801er_enable,
};