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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <device/device.h>
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
#include "i82801jx.h"
static void pch_smbus_init(struct device *dev)
{
u16 reg16;
/* Enable clock gating */
reg16 = pci_read_config16(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
pci_write_config16(dev, 0x80, reg16);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_write_byte(res->base, device, address, val);
}
static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes,
const u8 *buf)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_block_read(res->base, device, cmd, bytes, buf);
}
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
.block_read = lsmbus_block_read,
.block_write = lsmbus_block_write,
};
static struct pci_operations smbus_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Also add MMIO resource */
res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
}
static struct device_operations smbus_ops = {
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.scan_bus = scan_smbus,
.init = pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
};
static const unsigned short pci_device_ids[] =
{
0x3a30,
0x3a60,
0
};
static const struct pci_driver pch_smbus __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
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