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Some coreboot project code with my work
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path:
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/
src
/
southbridge
/
ti
/
pci1x2x
/
Makefile.inc
blob: 4f2a3d3ec930252760edb68dcf2e027aafc9c8d0 (
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ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) ramstage-y += pci1x2x.c endif