1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <device/cardbus.h>
static void pcixx12_init(struct device *dev)
{
/* cardbus controller function 1 for CF Socket */
printk(BIOS_DEBUG, "TI PCIxx12 init\n");
}
static void pcixx12_read_resources(struct device *dev)
{
cardbus_read_resources(dev);
}
static void pcixx12_set_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
pci_dev_set_resources(dev);
printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev));
}
static struct device_operations ti_pcixx12_ops = {
.read_resources = pcixx12_read_resources,
.set_resources = pcixx12_set_resources,
.enable_resources = cardbus_enable_resources,
.init = pcixx12_init,
.scan_bus = pci_scan_bridge,
};
static const struct pci_driver ti_pcixx12_driver __pci_driver = {
.ops = &ti_pcixx12_ops,
.vendor = 0x104c,
.device = 0x8039,
};
static void southbridge_init(struct device *dev)
{
}
struct chip_operations southbridge_ti_pcixx12_ops = {
CHIP_NAME("Texas Instruments PCIxx12 Cardbus Controller")
.enable_dev = southbridge_init,
};
|