summaryrefslogtreecommitdiff
path: root/src/superio/acpi/pnp_generic.asl
blob: 8f8d137c55877c8012ba82b96eed25dd1f7a0685 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2013 secunet Security Networks AG
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/* =================== Generic PnP Device =================== */

/*
 * Generic setup for PnP devices.
 *
 * Controlled by the following preprocessor defines:
 *
 * SUPERIO_CHIP_NAME	The name of the super i/o chip (unique, required)
 * SUPERIO_PNP_LDN	The logical device number on the super i/o
 *			chip for this device (required)
 * SUPERIO_PNP_DDN	A string literal that identifies the dos device
 *                      name (DDN) of this device (e.g. "COM1", optional)
 * SUPERIO_PNP_PM_REG	Identifier of a 1-bit register to power down
 *			the logical device (optional)
 * SUPERIO_PNP_PM_VAL	The value for SUPERIO_PNP_PM_REG to power the logical
 *			device down (required if SUPERIO_PNP_PM_REG is defined)
 * SUPERIO_PNP_PM_LDN	The logical device number to access the PM_REG
 *			bit (required if SUPERIO_PNP_PM_REG is defined)
 * SUPERIO_PNP_IO0	The alignment and length of the first PnP i/o
 *			resource (comma seperated, e.g. `0x02, 0x08`,
 *			optional)
 * SUPERIO_PNP_IO1	The alignment and length of the second PnP i/o
 *			resource (comma seperated, e.g. `0x02, 0x08`,
 *			optional)
 * SUPERIO_PNP_IRQ0	If defined, the first PnP IRQ register is enabled
 * SUPERIO_PNP_IRQ1	If defined, the second PnP IRQ register is enabled
 * SUPERIO_PNP_DMA	If defined, the PnP DMA register is enabled
 */

#include "pnp.asl"

#ifndef SUPERIO_CHIP_NAME
# error "SUPERIO_CHIP_NAME is not defined."
#endif

#ifndef SUPERIO_PNP_LDN
# error "SUPERIO_PNP_LDN is not defined."
#endif

Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
	Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */
	Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN))
	#ifdef SUPERIO_PNP_DDN
	Name (_DDN, SUPERIO_PNP_DDN)
	#endif

	Method (_STA)
	{
		PNP_GENERIC_STA(SUPERIO_PNP_LDN)
	}

	Method (_DIS)
	{
		PNP_GENERIC_DIS(SUPERIO_PNP_LDN)
	}

#ifdef SUPERIO_PNP_PM_REG
	Method (_PSC) {
		PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
	}

	Method (_PS0) {
		PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
	}

	Method (_PS1) {
		PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
	}
#else
	Method (_PSC) {
		PNP_DEFAULT_PSC
	}
#endif

	Method (_CRS)
	{
		Name (CRS, ResourceTemplate () {
#ifdef SUPERIO_PNP_IO0
			IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
#endif
#ifdef SUPERIO_PNP_IO1
			IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
#endif
#ifdef SUPERIO_PNP_IRQ0
			IRQNoFlags (IR0) {}
#endif
#ifdef SUPERIO_PNP_IRQ1
			IRQNoFlags (IR1) {}
#endif
#ifdef SUPERIO_PNP_DMA
			DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
#endif
		})
		ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
#ifdef SUPERIO_PNP_IO0
		  PNP_READ_IO(PNP_IO0, CRS, IO0)
#endif
#ifdef SUPERIO_PNP_IO1
		  PNP_READ_IO(PNP_IO1, CRS, IO1)
#endif
#ifdef SUPERIO_PNP_IRQ0
		  PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
#endif
#ifdef SUPERIO_PNP_IRQ1
		  PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
#endif
#ifdef SUPERIO_PNP_DMA
		  PNP_READ_DMA(PNP_DMA0, CRS, DM0)
#endif
		EXIT_CONFIG_MODE ()
		Return (CRS)
	}

	Method (_SRS, 1, Serialized)
	{
		Name (TMPL, ResourceTemplate () {
#ifdef SUPERIO_PNP_IO0
			IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
#endif
#ifdef SUPERIO_PNP_IO1
			IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
#endif
#ifdef SUPERIO_PNP_IRQ0
			IRQNoFlags (IR0) {}
#endif
#ifdef SUPERIO_PNP_IRQ1
			IRQNoFlags (IR1) {}
#endif
#ifdef SUPERIO_PNP_DMA
			DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
#endif
		})
		ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
#ifdef SUPERIO_PNP_IO0
		  PNP_WRITE_IO(PNP_IO0, Arg0, IO0)
#endif
#ifdef SUPERIO_PNP_IO1
		  PNP_WRITE_IO(PNP_IO1, Arg0, IO1)
#endif
#ifdef SUPERIO_PNP_IRQ0
		  PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
#endif
#ifdef SUPERIO_PNP_IRQ1
		  PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
#endif
#ifdef SUPERIO_PNP_DMA
		  PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0)
#endif
		  Store (One, PNP_DEVICE_ACTIVE)
		EXIT_CONFIG_MODE ()
	}
}