1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
|
/* $NoKeywords:$ */
/**
* @file
*
* Install of family 15h support
*
* This file generates the defaults tables for family 15h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_15H_INSTALL_H_
#define _OPTION_FAMILY_15H_INSTALL_H_
#include <Proc/CPU/cpuFamilyTranslation.h>
/*
* Pull in family specific services based on entry point
*/
/*
* Common Family 15h routines
*/
extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
/*
* Install family 15h model 0 support
*/
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
extern F_CPU_DISABLE_PSTATE F15DisablePstate;
extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
extern F_CPU_GET_TSC_RATE F15GetTscRate;
extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
/**
* Core Pair and core pair primary determination table.
*
* The two fields from the core pair hardware register can be used to determine whether
* even number cores are primary or all cores are primary. It can be extended if it is
* decided to have other configs as well. The other logically possible value sets are BitMapMapping,
* but they are currently not supported by the processor.
*/
CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
{
{1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
{3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
{7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores
{0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores
{1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
{3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
{7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core
{0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core
{HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
};
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F15PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F15OrMultiLinkPciRegisterTable,
&F15OrSingleLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F15OrPciRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F15OrEarlySamplePciRegisterTable,
#endif
#endif
#if BASE_FAMILY_MSR == TRUE
&F15MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F15OrMsrRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F15OrEarlySampleMsrRegisterTable,
#endif
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F15OrSharedMsrRegisterTable,
&F15OrSharedMsrCuRegisterTable,
&F15OrSharedMsrWorkaroundTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F15OrEarlySampleSharedMsrRegisterTable,
&F15OrEarlySampleSharedMsrWorkaroundTable,
#endif
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F15OrHtPhyRegisterTable,
#endif
#if BASE_FAMILY_WORKAROUNDS == TRUE
&F15OrWorkaroundsTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F15OrEarlySampleWorkaroundsTable,
#endif
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
{HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
{TokenPciRegister, SetRegisterForTokenPciEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
{CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
{
0,
#if DISABLE_PSTATE == TRUE
F15DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F15TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F15OrGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F15GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetMinMaxNbFrequency,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F15CommonGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F15LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F15OrGetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F15OrGetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F15OrSetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F15OrGetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F15OrTransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F15CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
// F15OrSaveFeatures,
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
// F15OrWriteFeatures,
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F15SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F15GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF15OrMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF15OrMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF15CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF15OrSysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF15WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F15IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15NextLinkHasHtPhyFeats,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F15GetNextHtLinkFeatures,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F15OrRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
(PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
#else
NULL,
#endif
(CORE_PAIR_MAP *) &HtFam15CorePairMapping,
InitCacheEnabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF15OrEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define OR_SOCKETS 8
#define OR_MODULES 2
#define OR_RECOVERY_SOCKETS 1
#define OR_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
#define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES OR_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < OR_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES OR_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F15_OR_UCODE_17_UNENC
#define F15_OR_UCODE_11F_UNENC
#define F15_OR_UCODE_425
#define F15_OR_UCODE_509
#define F15_OR_UCODE_602
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000602 [];
#undef F15_OR_UCODE_602
#define F15_OR_UCODE_602 CpuF15OrMicrocodePatch06000602,
#endif
CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] =
{
F15_OR_UCODE_602
F15_OR_UCODE_509
F15_OR_UCODE_425
F15_OR_UCODE_11F_UNENC
F15_OR_UCODE_17_UNENC
NULL
};
CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart;
extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd;
extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch;
extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded;
CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
{
F15OrEarlySamplesAvoidNbCyclesStart,
F15OrEarlySamplesAvoidNbCyclesEnd,
F15OrEarlySamplesLoadMicrocodePatch,
F15OrEarlySamplesAfterPatchLoaded
};
#else
CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
{
(PF_F15_OR_ES_AVOID_NB_CYCLES_START) CommonVoid,
(PF_F15_OR_ES_AVOID_NB_CYCLES_END) CommonVoid,
(PF_F15_OR_ES_LOAD_MCU_PATCH) LoadMicrocodePatch,
(PF_F15_OR_ES_AFTER_PATCH_LOADED) CommonVoid
};
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
F15OrHtcInitEarlySampleHook,
#else
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
#endif
};
#else
CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
#else
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
#endif
};
#endif
#define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
#else // OPTION_FAMILY15H_OR == TRUE
#define OPT_F15_OR_CPU
#define OPT_F15_OR_ID
#endif // OPTION_FAMILY15H_OR == TRUE
#else // defined (OPTION_FAMILY15H_OR)
#define OPT_F15_OR_CPU
#define OPT_F15_OR_ID
#endif // defined (OPTION_FAMILY15H_OR)
/*
* Install family 15h model 10h - 1Fh support
*/
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax;
extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax;
extern F_CPU_DISABLE_PSTATE F15DisablePstate;
extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
extern F_CPU_GET_TSC_RATE F15GetTscRate;
extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency;
extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency;
extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware;
extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
extern F_IS_NB_PSTATE_ENABLED F15TnIsNbPstateEnabled;
extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister;
extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable;
extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable;
extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
/**
* Core Pair and core pair primary determination table.
*
* The two fields from the core pair hardware register can be used to determine whether
* even number cores are primary or all cores are primary. It can be extended if it is
* decided to have other configs as well. The other logically possible value sets are BitMapMapping,
* but they are currently not supported by the processor.
*/
CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] =
{
{1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
{3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
{1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
{3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
{HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
};
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F15PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F15TnPciRegisterTable,
&F15TnPciWorkaroundTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F15MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F15TnMsrRegisterTable,
&F15TnMsrWorkaroundTable,
&F15TnSharedMsrRegisterTable,
&F15TnSharedMsrCuRegisterTable,
&F15TnSharedMsrWorkaroundTable,
&F15TnPerNodeMsrWorkaroundTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices =
{
0,
#if DISABLE_PSTATE == TRUE
F15DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F15TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F15TnGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F15GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15TnGetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15TnGetMinMaxNbFrequency,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15TnGetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F15CommonGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F15LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F15TnGetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F15TnGetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F15TnGetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F15CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F15SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F15GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF15TnMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF15TnMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF15CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF15TnSysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF15WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F15TnIsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15NextLinkHasHtPhyFeats,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F15GetNextHtLinkFeatures,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F15TnRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
(CORE_PAIR_MAP *) &HtFam15TnCorePairMapping,
InitCacheEnabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF15TnEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define TN_SOCKETS 1
#define TN_MODULES 1
#define TN_RECOVERY_SOCKETS 1
#define TN_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev;
#define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES TN_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < TN_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES TN_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F15_TN_UCODE_10F
#define F15_TN_UCODE_0E
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [];
#undef F15_TN_UCODE_10F
#define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc,
#endif
CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] =
{
F15_TN_UCODE_10F
F15_TN_UCODE_0E
NULL
};
CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1);
#endif
#define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices},
#else // OPTION_FAMILY15H_TN == TRUE
#define OPT_F15_TN_CPU
#define OPT_F15_TN_ID
#endif // OPTION_FAMILY15H_TN == TRUE
#else // defined (OPTION_FAMILY15H_TN)
#define OPT_F15_TN_CPU
#define OPT_F15_TN_ID
#endif // defined (OPTION_FAMILY15H_TN)
/*
* Install unknown family 15h support
*/
#ifdef OPTION_FAMILY15H_UNKNOWN
#if OPTION_FAMILY15H_UNKNOWN == TRUE
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F15PciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F15MsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
{HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F15DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F15TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
(PF_CPU_GET_IDD_MAX) CommonReturnFalse,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F15GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F15LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F15CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
// F15SaveFeatures,
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
// F15WriteFeatures,
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F15SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F15GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF15WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F15IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15NextLinkHasHtPhyFeats,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#endif
#if BASE_FAMILY_PCI == TRUE
F15GetNextHtLinkFeatures,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F15UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
NULL,
InitCacheEnabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define OPT_F15_UNKNOWN_CPU {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &cpuF15UnknownServices},
#else // OPTION_FAMILY15H_UNKNOWN == TRUE
#define OPT_F15_UNKNOWN_CPU
#define OPT_F15_UNKNOWN_ID
#endif // OPTION_FAMILY15H_UNKNOWN == TRUE
#else // defined OPTION_FAMILY15H_UNKNOWN
#define OPT_F15_UNKNOWN_CPU
#define OPT_F15_UNKNOWN_ID
#endif // defined OPTION_FAMILY15H_UNKNOWN
// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
#endif
#undef OPT_F15_ID_TABLE
#define OPT_F15_ID_TABLE {0x15, {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , (AMD_FAMILY_UNKNOWN | AMD_F15_OR_B2 | AMD_F15_TN_A0 | 0x0000000000100000ull ) }, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
#undef OPT_F15_TABLE
#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_TN_CPU {0, NULL}, OPT_F15_UNKNOWN_CPU
#if OPTION_G34_SOCKET_SUPPORT == TRUE
#define F15_G34_BRANDSTRING1 NULL,
#define F15_G34_BRANDSTRING2 NULL,
#else
#define F15_G34_BRANDSTRING1
#define F15_G34_BRANDSTRING2
#endif
#if OPTION_C32_SOCKET_SUPPORT == TRUE
#define F15_C32_BRANDSTRING1 NULL,
#define F15_C32_BRANDSTRING2 NULL,
#else
#define F15_C32_BRANDSTRING1
#define F15_C32_BRANDSTRING2
#endif
#if OPTION_AM3_SOCKET_SUPPORT == TRUE
#define F15_AM3_BRANDSTRING1 NULL,
#define F15_AM3_BRANDSTRING2 NULL,
#else
#define F15_AM3_BRANDSTRING1
#define F15_AM3_BRANDSTRING2
#endif
#if OPTION_FS1_SOCKET_SUPPORT == TRUE
#define F15_FS1_BRANDSTRING1 NULL,
#define F15_FS1_BRANDSTRING2 NULL,
#else
#define F15_FS1_BRANDSTRING1
#define F15_FS1_BRANDSTRING2
#endif
#if OPTION_FM2_SOCKET_SUPPORT == TRUE
#define F15_FM2_BRANDSTRING1 NULL,
#define F15_FM2_BRANDSTRING2 NULL,
#else
#define F15_FM2_BRANDSTRING1
#define F15_FM2_BRANDSTRING2
#endif
#if OPTION_FP2_SOCKET_SUPPORT == TRUE
#define F15_FP2_BRANDSTRING1 NULL,
#define F15_FP2_BRANDSTRING2 NULL,
#else
#define F15_FP2_BRANDSTRING1
#define F15_FP2_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
{
F15_G34_BRANDSTRING1
F15_C32_BRANDSTRING1
F15_AM3_BRANDSTRING1
F15_FS1_BRANDSTRING1
NULL,
F15_FM2_BRANDSTRING1
NULL,
F15_FP2_BRANDSTRING1
};
CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
{
F15_G34_BRANDSTRING2
F15_C32_BRANDSTRING2
F15_AM3_BRANDSTRING2
F15_FS1_BRANDSTRING2
NULL,
F15_FM2_BRANDSTRING2
NULL,
F15_FP2_BRANDSTRING2
};
CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
{
OPT_F15_OR_ID
OPT_F15_TN_ID
NULL
};
#endif // _OPTION_FAMILY_15H_INSTALL_H_
|
