blob: ca3215756841e456c0221cf34fe52869eecd861c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
##
##
##
## SPDX-License-Identifier: GPL-2.0-only
config CAVIUM_BDK
def_bool n
select HAVE_DEBUG_RAM_SETUP
help
Build Cavium's BDK in romstage.
if CAVIUM_BDK
menu "BDK"
config CAVIUM_BDK_VERBOSE_INIT
bool "Enable verbose init"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose init code.
config CAVIUM_BDK_VERBOSE_DRAM
bool "Enable verbose dram init"
default y if DEBUG_RAM_SETUP
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose dram init code.
config CAVIUM_BDK_VERBOSE_DRAM_TEST
bool "Enable verbose raminit tests"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose DRAM testing code.
config CAVIUM_BDK_VERBOSE_QLM
bool "Enable verbose qlm init"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose QLM code.
config CAVIUM_BDK_VERBOSE_PCIE_CONFIG
bool "Enable verbose pcie config"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose PCIe config code.
config CAVIUM_BDK_VERBOSE_PCIE
bool "Enable verbose pcie init"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose PCIe code.
config CAVIUM_BDK_VERBOSE_PHY
bool "Enable verbose phy init"
depends on CAVIUM_BDK
help
Build Cavium's BDK with verbose PHY code.
config CAVIUM_BDK_DDR_TUNE_HW_OFFSETS
bool "Hardware assisted DLL read offset tuning"
default n
depends on CAVIUM_BDK
help
Automatically tune the data byte DLL read offsets.
Always done by default, but allow use of HW-assist.
NOTE: HW-assist will also tune the ECC byte.
config CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS
bool "Automatically tune the data byte DLL write offsets"
default n
depends on CAVIUM_BDK
config CAVIUM_BDK_DDR_TUNE_ECC_ENABLE
bool "Automatically tune the ECC byte DLL read offsets"
default n
depends on CAVIUM_BDK
endmenu
endif
|
