index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
util
/
riscv
Mode
Name
Size
-rwxr-xr-x
make-spike-elf.sh
720
log
plain
-rwxr-xr-x
sifive-gpt.py
6145
log
plain
-rw-r--r--
spike-elf.ld
153
log
plain
