Upgrade core to UDK2018

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: Guo Mang <mang.guo@intel.com>

12 files changed, 98 insertions, 46 deletions

diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
index d8d664b258..bd3a7b6498 100644
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
@@ -8,16 +8,12 @@ echo.
 ::**********************************************************************

 :: Initial Setup

 ::**********************************************************************

-set WORKSPACE=%CD%

-if %WORKSPACE:~-1%==\ (

-  set WORKSPACE=%WORKSPACE:~0,-1%

-)

-set CORE_PATH=%WORKSPACE%\Core

-set PLATFORM_PATH=Platform\BroxtonPlatformPkg

-set SILICON_PATH=Silicon\BroxtonSoC

+

+set CORE_PATH=%WORKSPACE%\edk2

+set PLATFORM_PATH=edk2-platforms\Platform\BroxtonPlatformPkg

+set SILICON_PATH=edk2-platforms\Silicon\BroxtonSoC

 set AslPath=%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\Iasl\iasl.exe

-set PACKAGES_PATH=%CORE_PATH%;%WORKSPACE%\Silicon\;%WORKSPACE%\Platform;%WORKSPACE%\%PLATFORM_PATH%;%WORKSPACE%\%SILICON_PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common ;

-set EDK_TOOLS_BIN=%WORKSPACE%\BaseTools\Bin\Win32

+set PACKAGES_PATH=%CORE_PATH%;%WORKSPACE%\edk2-platforms;%WORKSPACE%\edk2-platforms\Silicon\;%WORKSPACE%\edk2-platforms\Platform;%WORKSPACE%\%PLATFORM_PATH%;%WORKSPACE%\%SILICON_PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common ;

 set /a build_threads=1

 set "Nasm_Flags=-D ARCH_IA32 -D DEBUG_PORT80"

 set "Build_Flags= "

@@ -44,13 +40,15 @@ if exist conf\.cache rmdir /q/s conf\.cache
 :: Override tools_def.txt

 echo Creating Conf folder and build config files...

 if not exist %WORKSPACE%\Conf md %WORKSPACE%\Conf

-copy /y %WORKSPACE%\BaseTools\Conf\*.template %WORKSPACE%\Conf\*.txt

 

 :: Setup EDK environment. Edksetup puts new copies of target.txt, tools_def.txt, build_rule.txt in WorkSpace\Conf

 :: Also run edksetup as soon as possible to avoid it from changing environment variables we're overriding

 set "VCINSTALLDIR="

-set EDK_TOOLS_PATH=%WORKSPACE%\BaseTools

-call edksetup.bat

+set PYTHON_HOME=C:\Python27

+@call %CORE_PATH%\edksetup.bat --nt32

+@if defined PYTHON_HOME (

+  @nmake -f %BASE_TOOLS_PATH%\Makefile

+)

 @echo off

 

 set Minnow_RVP=MINN

@@ -68,9 +66,7 @@ set FSP_WRAPPER=FALSE
 set EFI_SOURCE=%CD%

 set EDK_SOURCE=%CD%

 set PLATFORM_NAME=BxtPlatformPkg

-set PLATFORM_PACKAGE=%PLATFORM_PATH%\BxtPlatformPkg

-set PLATFORM_RC_PACKAGE=Silicon\BroxtonSoC\BroxtonSiPkg

-set COMMON_PLATFORM_PACKAGE=%PLATFORM_PATH%\BxtPlatformPkg

+set PLATFORM_RC_PACKAGE=%SILICON_PATH%\BroxtonSiPkg

 set FSP_BIN_PKG_NAME=BroxtonFspBinPkg

 set STITCH_PATH=%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\Stitch

 

@@ -449,7 +445,7 @@ echo *_VS2015x86_*_ASL_PATH = %AslPath% >> Conf\tools_def.txt
 

 echo.

 echo Invoking normal EDK2 build...

-build %Build_Flags%

+call build %Build_Flags%

 if ErrorLevel 1 goto BldFail

 

 set WORKSPACE=%SaveWorkSpace%

@@ -505,13 +501,13 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv  %Storage_Folder% >nul
 

 if /i "%FSP_WRAPPER%" == "TRUE" (

 ::  0xFEF7A000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)

-    pushd  %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin

-    python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f Fsp.fd -c m -b 0xFEF7A000 -o .\ -n ApolloLakeFsp.fd

-    python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f ApolloLakeFsp.fd -o .\ -n FSP.Fv

+    pushd  %SILICON_PATH%\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin

+    python %CORE_PATH%\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f Fsp.fd -c m -b 0xFEF7A000 -o .\ -n ApolloLakeFsp.fd

+    python %CORE_PATH%\IntelFsp2Pkg\Tools\SplitFspBin.py split -f ApolloLakeFsp.fd -o .\ -n FSP.Fv

     popd

-    copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv

-    copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_M.Fv %Storage_Folder%\FSP_M.Fv

-    copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_S.Fv %Storage_Folder%\FSP_S.Fv

+    copy /y/b %SILICON_PATH%\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv

+    copy /y/b %SILICON_PATH%\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_M.Fv %Storage_Folder%\FSP_M.Fv

+    copy /y/b %SILICON_PATH%\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_S.Fv %Storage_Folder%\FSP_S.Fv

 )

 

 echo Get NvStorage Base and Size...

diff --git a/Platform/BroxtonPlatformPkg/BuildIFWI.bat b/Platform/BroxtonPlatformPkg/BuildIFWI.bat
index 99b3569c95..f4c887dc39 100644
--- a/Platform/BroxtonPlatformPkg/BuildIFWI.bat
+++ b/Platform/BroxtonPlatformPkg/BuildIFWI.bat
@@ -10,14 +10,17 @@ set SkipUsageFlag=FALSE
 set FabId=B
 set BoardId=MN
 set buildthread=
+cd ..
 set WORKSPACE=%CD%
 if %WORKSPACE:~-1%==\ (
   set WORKSPACE=%WORKSPACE:~0,-1%
 )
-set CORE_PATH=%WORKSPACE%\Core
-set PLATFORM_PATH=Platform\BroxtonPlatformPkg
-set SILICON_PATH=Silicon\Src\BroxtonSoC
-set STITCH_PATH=%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\Stitch
+echo %WORKSPACE%
+set CORE_PATH=%WORKSPACE%\edk2
+set EDK_TOOLS_PATH=%CORE_PATH%\BaseTools
+set PLATFORM_PATH=edk2-platforms\Platform\BroxtonPlatformPkg
+set SILICON_PATH=edk2-platforms\Silicon\BroxtonSoC
+set STITCH_PATH=%PLATFORM_PATH%\Common\Tools\Stitch
 
 set Minnow_RVP=MINN
 
@@ -188,8 +191,8 @@ echo.
 echo BIOS ROM input:  %BIOS_Name%
 echo.
 pushd %STITCH_PATH%
-   echo  - call IFWIStitch_Simple.bat %STITCH_PATH%\%BIOS_Name% %FabId% %BoardId%
-   call %STITCH_PATH%\IFWIStitch_Simple.bat %STITCH_PATH%\%BIOS_Name% %FabId% %BoardId%
+   echo  - call IFWIStitch_Simple.bat %WORKSPACE%\%STITCH_PATH%\%BIOS_Name% %FabId% %BoardId%
+   call IFWIStitch_Simple.bat %WORKSPACE%\%STITCH_PATH%\%BIOS_Name% %FabId% %BoardId%
    @echo off
 popd
 if ErrorLevel 1 (
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/GenericIch.h b/Platform/BroxtonPlatformPkg/Common/Include/GenericIch.h
new file mode 100644
index 0000000000..697ea049ee
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Include/GenericIch.h
@@ -0,0 +1,55 @@
+/** @file

+  Generic definitions for registers in the Intel Ich devices.

+

+  These definitions should work for any version of Ich.

+

+  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef _GENERIC_ICH_H_

+#define _GENERIC_ICH_H_

+

+/** GenericIchDefs  Generic ICH Definitions.

+

+Definitions beginning with "R_" are registers.

+Definitions beginning with "B_" are bits within registers.

+Definitions beginning with "V_" are meaningful values of bits within the registers.

+**/

+///@{

+

+/// IchPciAddressing  PCI Bus Address for ICH.

+///@{

+#define PCI_BUS_NUMBER_ICH                0x00  ///< ICH is on PCI Bus 0.

+#define PCI_DEVICE_NUMBER_ICH_LPC           31  ///< ICH is Device 31.

+#define PCI_FUNCTION_NUMBER_ICH_LPC          0  ///< ICH is Function 0.

+///@}

+

+/// IchAcpiCntr   Control for the ICH's ACPI Counter.

+///@{

+#define R_ICH_LPC_ACPI_BASE                   0x40

+#define   B_ICH_LPC_ACPI_BASE_BAR                 0x0000FF80

+#define R_ICH_LPC_ACPI_CNT                    0x44

+#define   B_ICH_LPC_ACPI_CNT_ACPI_EN              0x80

+///@}

+

+/// IchAcpiTimer  The ICH's ACPI Timer.

+///@{

+#define R_ACPI_PM1_TMR                        0x08

+#define   V_ACPI_TMR_FREQUENCY                    3579545

+#define   V_ACPI_PM1_TMR_MAX_VAL                  0x1000000 ///< The timer is 24 bit overflow.

+///@}

+

+/// Macro to generate the PCI address of any given ICH Register.

+#define PCI_ICH_LPC_ADDRESS(Register) \

+  ((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Register)))

+

+///@}

+#endif  // _GENERIC_ICH_H_

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.c
index 4e90f4eaea..49d38eb45c 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.c
@@ -17,7 +17,7 @@
 

   A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].

 

-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution. The full text of the license may be found at

@@ -32,7 +32,6 @@
 #include <Library/UefiBootServicesTableLib.h>

 #include <Library/UefiLib.h>

 #include <Library/DebugLib.h>

-#include <Guid/TscFrequency.h>

 #include "TscTimerLibInternal.h"

 

 UINT64 mTscFrequency;

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.inf b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.inf
index a2ff9d05dd..1f77907470 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/DxeTscTimerLib.inf
@@ -12,7 +12,7 @@
 #  TSC reads are much more efficient and do not incur the overhead associated with a ring transition or

 #  access to a platform resource.

 #

-#  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -44,7 +44,6 @@
 

 [Packages]

   MdePkg/MdePkg.dec

-  PerformancePkg/PerformancePkg.dec

   BroxtonSiPkg/BroxtonSiPkg.dec

   BroxtonPlatformPkg/PlatformPkg.dec

 

@@ -61,6 +60,6 @@
   gEfiTscFrequencyGuid                          ## CONSUMES ## SystemTable

 

 [Pcd.common]

-  gPerformancePkgTokenSpaceGuid.PcdPerfPkgAcpiIoPortBaseAddress   ## SOMETIMES_CONSUMES

+  gPlatformModuleTokenSpaceGuid.PcdPerfPkgAcpiIoPortBaseAddress   ## SOMETIMES_CONSUMES

   gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress

 

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.c
index caf1925748..397502bc92 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.c
@@ -17,7 +17,7 @@
 

   A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].

 

-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -31,7 +31,6 @@
 

 #include <PiPei.h>

 #include <Library/HobLib.h>

-#include <Guid/TscFrequency.h>

 #include "TscTimerLibInternal.h"

 

 

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.inf b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.inf
index 0821983139..3b17cef70d 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/PeiTscTimerLib.inf
@@ -12,7 +12,7 @@
 #  TSC reads are much more efficient and do not incur the overhead associated with a ring transition or

 #  access to a platform resource.

 #

-#  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -43,7 +43,7 @@
 

 [Packages]

   MdePkg/MdePkg.dec

-  PerformancePkg/PerformancePkg.dec

+  BroxtonPlatformPkg/PlatformPkg.dec

   BroxtonSiPkg/BroxtonSiPkg.dec

 

 [LibraryClasses]

@@ -57,6 +57,6 @@
   gEfiTscFrequencyGuid                          ## PRODUCES ## HOB

 

 [Pcd.common]

-  gPerformancePkgTokenSpaceGuid.PcdPerfPkgAcpiIoPortBaseAddress     ## SOMETIMES_CONSUMES

+  gPlatformModuleTokenSpaceGuid.PcdPerfPkgAcpiIoPortBaseAddress     ## SOMETIMES_CONSUMES

   gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress

 

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/TscTimerLibInternal.h b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/TscTimerLibInternal.h
index 99f6fcdee4..272c763ed6 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/TscTimerLibInternal.h
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformTscTimerLib/TscTimerLibInternal.h
@@ -1,7 +1,7 @@
 /** @file

   Internal header file for TscTimerLib instances.

 

-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -16,7 +16,7 @@
 #ifndef _TSC_TIMER_LIB_INTERNAL_H_

 #define _TSC_TIMER_LIB_INTERNAL_H_

 

-#include <Ich/GenericIch.h>

+#include <GenericIch.h>

 #include <Library/TimerLib.h>

 #include <Library/BaseLib.h>

 #include <Library/IoLib.h>

diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
index 8ace30f8db..351ccd8555 100644
--- a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
+++ b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
@@ -8,9 +8,8 @@ copy /y nul Stitching.log >nul
 

 :: Set tool env

 set WORKSPACE=%CD%

-set CORE_TOOLS_PATH=%WORKSPACE%\..\..\..\..\..\BaseTools\Bin\Win32

 if %WORKSPACE:~-1%==\ set WORKSPACE=%WORKSPACE:~0,-1%

-PATH=%PATH%;%WORKSPACE%\Tools;%WORKSPACE%\Tools\VLV_Merge_Tools;%WORKSPACE%\;%CORE_TOOLS_PATH%

+PATH=%PATH%;%WORKSPACE%\Tools;%WORKSPACE%\Tools\VLV_Merge_Tools;%WORKSPACE%\;

 

 :: Set default Suffix as:  YYYY_MM_DD_HHMM

 set hour=%time: =0%

diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
index 2320d2f9c6..c756b381d1 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
@@ -1,7 +1,7 @@
 ## @file

 #  Library classes Description.

 #

-#  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -273,5 +273,5 @@
    BltLib|$(PLATFORM_PACKAGE_COMMON)/Library/FrameBufferBltLib/FrameBufferBltLib.inf

 

    UefiBootManagerLib | MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf

-   PlatformBootManagerLib | Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

+   PlatformBootManagerLib | $(PLATFORM_PACKAGE_COMMON)/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

    BootLogoLib | MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
\ No newline at end of file
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
index aed59fee99..683d92f4ac 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
@@ -109,6 +109,7 @@
   gHiiExportDatabaseGuid                      = { 0x1b838190, 0x4625, 0x4ead, { 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }}

 

   gEfiHtBistHobGuid              = { 0xBE644001, 0xE7D4, 0x48B1, { 0xB0, 0x96, 0x8B, 0xA0, 0x47, 0xBC, 0x7A, 0xE7 }}

+  gEfiTscFrequencyGuid                = { 0xdba6a7e3, 0xbb57, 0x4be7, { 0x8a, 0xf8, 0xd5, 0x78, 0xdb, 0x7e, 0x56, 0x87 }}

 

 [Ppis]

   gDebugServicePpiGuid                    = { 0xb781df4c, 0xdc36, 0x4230, { 0xb5, 0x6d, 0xa0, 0x1,  0xb6, 0x8c, 0x15, 0xc7 } }

@@ -314,6 +315,7 @@
   gClientCommonModuleTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By O.E.M."|VOID*|0x00000308

   gClientCommonModuleTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By O.E.M."|VOID*|0x00000309

   gClientCommonModuleTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By O.E.M."|VOID*|0x0000030A

+  gPlatformModuleTokenSpaceGuid.PcdPerfPkgAcpiIoPortBaseAddress|0x400|UINT16|1

 

 [PcdsPatchableInModule]

 

diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index 6a538fb449..a964477614 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -168,9 +168,9 @@
   $(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)

   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize

   !if $(SECURE_BOOT_ENABLE)

-      FILE = $(WORKSPACE)/Platform/$(PLATFORM_PACKAGE_COMMON)/Binaries/Prebuild/X64/VpdBlockSecBoot.bin

+      FILE = $(WORKSPACE)/edk2-platforms/Platform/$(PLATFORM_PACKAGE_COMMON)/Binaries/Prebuild/X64/VpdBlockSecBoot.bin

   !else

-      FILE = $(WORKSPACE)/Platform/$(PLATFORM_PACKAGE_COMMON)/Binaries/Prebuild/X64/VpdBlock.bin

+      FILE = $(WORKSPACE)/edk2-platforms/Platform/$(PLATFORM_PACKAGE_COMMON)/Binaries/Prebuild/X64/VpdBlock.bin

   !endif

 

   $(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)