diff options
| author | zwei4 <david.wei@intel.com> | 2017-09-21 11:24:14 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-09-21 11:28:27 +0800 |
| commit | 390cf8dd3c89eb3784ac4aa27437f9125cce0db3 (patch) | |
| tree | f411490d108c8b1f6088060ded239c51f9b7022d | |
| parent | 8086a8f8f63a24618309429ce545cb6a39972b15 (diff) | |
| download | edk2-platforms-390cf8dd3c89eb3784ac4aa27437f9125cce0db3.tar.xz | |
Calibrate PMIC IMON.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>
3 files changed, 59 insertions, 4 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c index bfed3bf1ac..7d003e466b 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c @@ -311,6 +311,53 @@ BXTPolicyInit ( return EFI_SUCCESS;
}
+VOID
+ConfigurePmicIMON (
+ VOID
+ )
+{
+ UINTN PciD0F0RegBase = 0;
+ UINTN MchBar = 0;
+ UINT32 Data;
+ UINT16 StallCount;
+ UINT64 PkgPwrSKU;
+
+ PciD0F0RegBase = MmPciAddress (0,SA_MC_BUS,SA_MC_DEV,SA_MC_FUN,0);
+ MchBar = MmioRead32 (PciD0F0RegBase + R_SA_MCHBAR_REG) &~BIT0;
+ PkgPwrSKU = AsmReadMsr64 (MSR_PACKAGE_POWER_SKU);
+
+ StallCount = 0;
+ while (StallCount < 1000) {
+ Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);
+ if ((Data & BIT31) == BIT31) {
+ MicroSecondDelay (1);
+ } else {
+ break;
+ }
+ StallCount++;
+ }
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xfa0d04a4);
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000011d);
+
+ StallCount = 0;
+ while (StallCount < 1000) {
+ Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);
+ if ((Data & BIT31) == BIT31) {
+ MicroSecondDelay (1);
+ } else {
+ break;
+ }
+ StallCount++;
+ }
+
+ if ((PkgPwrSKU & 0x07FFF) >= 0x0903){
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xe8330466);
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d);
+ } else {
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xed3303b3);
+ MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d);
+ }
+}
/**
Platform Init PEI module entry point
@@ -363,6 +410,8 @@ PlatformInitEntryPoint ( }
PWM_Fan_Start ();
+
+ ConfigurePmicIMON();
//
// Initialize PlatformInfo HOB
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi index 32eea2005d..f8b4b47ec0 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi @@ -1,7 +1,7 @@ // /** @file
// UnCore Setup formset.
//
-// Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -104,8 +104,8 @@ form formid = UNCORE_FORM_ID, oneof varid = Setup.EnableRenderStandby,
prompt = STRING_TOKEN(STR_VIDEO_RS2_PROMPT),
help = STRING_TOKEN(STR_VIDEO_RS2_HELP),
- option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
- option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
+ option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
+ option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
endoneof;
oneof varid = Setup.GTTSize,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h index 5dd8440926..e985e75c48 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h @@ -15,7 +15,7 @@ Registers / bits of new devices introduced in a SA generation will be just named
as "_SA_" without [generation_name] inserted.
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -60,6 +60,12 @@ #define R_SA_MCHBAR_REG 0x48
//
+// IA-Punit Mailbox on MCH BAR
+//
+#define R_BIOS_MAILBOX_DATA 0x7080
+#define R_BIOS_MAILBOX_INTERFACE 0x7084
+
+//
// Silicon Steppings
//
#define V_SA_MC_RID_0 0x00
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