diff options
| author | zwei4 <david.wei@intel.com> | 2018-01-05 15:59:56 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2018-01-05 15:59:56 +0800 |
| commit | 88d98451d5ffb3bb20d6c639afc4bb5e927e2559 (patch) | |
| tree | 683eaaedf218f5b5fbb43714808fcb20ec8714b7 | |
| parent | ec31c689fc59a59c4ffaeb06c48660872edd64e1 (diff) | |
| download | edk2-platforms-88d98451d5ffb3bb20d6c639afc4bb5e927e2559.tar.xz | |
Aurora Glacier Code.
Add board specific code for Aurora Glacier.
Build command is "BuildBIOS /AG /A /vs13 Broxton Release".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>
34 files changed, 2891 insertions, 24 deletions
diff --git a/BuildBIOS.bat b/BuildBIOS.bat index 96c34f9d85..dab34d2b87 100644 --- a/BuildBIOS.bat +++ b/BuildBIOS.bat @@ -60,6 +60,7 @@ echo /D Set FabId to D echo /MN MinnowBoard 3(default: MN)
echo /MX MinnowBoard 3 Module
echo /BG Benson Glacier Board
+echo /AG Aurora Glacier Board
echo /LH LeafHill CRB Board
echo PlatformName: Broxton
echo BuildTargets: Release, Debug
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c new file mode 100644 index 0000000000..e948594c83 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c @@ -0,0 +1,68 @@ +/** @file
+ Board specific functions in DXE phase to be set as dynamic PCD and consumed by
+ commmon platform code.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitDxe.h"
+
+GET_BOARD_NAME mAuroraGetBoardNamePtr = AuroraGetBoardName;
+
+CHAR16*
+EFIAPI
+AuroraGetBoardName (
+ IN UINT8 BoardId
+ )
+{
+ STATIC CHAR16 BoardName[40];
+
+ DEBUG ((EFI_D_INFO, "BoardInitDxe: GetBoardName - Aurora Glacier\n"));
+
+ UnicodeSPrint (BoardName, sizeof (BoardName), L"Aurora Glacier ");
+
+ if (BoardId != (UINT8) BOARD_ID_AURORA) {
+ return NULL;
+ } else {
+ return BoardName;
+ }
+}
+
+
+/**
+ Set PCDs for board specific functions.
+
+ @param[in] ImageHandle ImageHandle of the loaded driver.
+ @param[in] SystemTable Pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The handlers were registered successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraBoardInitDxeConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT8 BoardId;
+
+ BoardId = PcdGet8 (PcdBoardId);
+ if (BoardId != (UINT8) BOARD_ID_AURORA) {
+ return EFI_SUCCESS;
+ }
+
+ PcdSet64 (PcdGetBoardNameFunc, (UINT64) mAuroraGetBoardNamePtr);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.h new file mode 100644 index 0000000000..364d71a926 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.h @@ -0,0 +1,37 @@ +/** @file
+ The internal header file includes the common header files, defines
+ internal structure and functions used by ImageVerificationLib.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __AURORA_BOARD_INIT_DXE_H__
+#define __AURORA_BOARD_INIT_DXE_H__
+
+#include <BoardFunctionsDxe.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Guid/PlatformInfo_Aplk.h>
+
+CHAR16*
+EFIAPI
+AuroraGetBoardName (
+ IN UINT8 BoardId
+ );
+
+#endif
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf new file mode 100644 index 0000000000..62899f61e8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf @@ -0,0 +1,52 @@ +## @file
+# Board specific functions in DXE phase to be set as dynamic PCD and consumed by
+# commmon platform code.
+#
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AuroraBoardInitDxe
+ FILE_GUID = 5FFC0339-D9DB-451D-A508-B7998173EF36
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ CONSTRUCTOR = AuroraBoardInitDxeConstructor
+
+[Sources]
+ BoardInitDxe.c
+ BoardInitDxe.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ DebugLib
+ PcdLib
+ PrintLib
+
+[Protocols]
+
+[Guids]
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdGetBoardNameFunc
+ gPlatformModuleTokenSpaceGuid.PcdBoardId
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.c new file mode 100644 index 0000000000..9cf3d1e992 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.c @@ -0,0 +1,265 @@ +/** @file
+ Gpio setting for multiplatform.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardGpios.h"
+#include <Library/GpioLib.h>
+#include <Library/SteppingLib.h>
+
+
+/**
+ Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+AuroraMultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ DEBUG ((DEBUG_INFO, "AuroraMultiPlatformGpioTableInit()...\n"));
+ DEBUG ((DEBUG_INFO, "PlatformInfoHob->BoardId: 0x%02X\n", PlatformInfoHob->BoardId));
+
+ //
+ // Select/modify the GPIO initialization data based on the Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_AURORA:
+ PlatformInfoHob->PlatformGpioSetting_SW = &mAuroraGpioInitData_SW[0];
+ PlatformInfoHob->PlatformGpioSetting_W = &mAuroraGpioInitData_W[0];
+ PlatformInfoHob->PlatformGpioSetting_NW = &mAuroraGpioInitData_NW[0];
+ PlatformInfoHob->PlatformGpioSetting_N = &mAuroraGpioInitData_N[0];
+ break;
+ default:
+ PlatformInfoHob->PlatformGpioSetting_SW = &mAuroraGpioInitData_SW[0];
+ PlatformInfoHob->PlatformGpioSetting_W = &mAuroraGpioInitData_W[0];
+ PlatformInfoHob->PlatformGpioSetting_NW = &mAuroraGpioInitData_NW[0];
+ PlatformInfoHob->PlatformGpioSetting_N = &mAuroraGpioInitData_N[0];
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Set GPIO Lock for security.
+
+**/
+VOID
+AuroraSetGpioPadCfgLock (
+ VOID
+ )
+{
+ UINT32 Data32;
+
+ Data32 = 0;
+
+ //
+ // JTAG
+ //
+ GpioLockPadCfg (N_TCK);
+ GpioLockPadCfg (N_TRST_B);
+ GpioLockPadCfg (N_TMS);
+ GpioLockPadCfg (N_TDI);
+ GpioLockPadCfg (N_TDO);
+
+ //
+ // Power
+ //
+ GpioLockPadCfg (NW_PMIC_THERMTRIP_B);
+ GpioLockPadCfg (NW_PROCHOT_B);
+
+ //
+ // Touch
+ //
+ GpioLockPadCfg (NW_GPIO_118);
+ GpioLockPadCfg (NW_GPIO_119);
+ GpioLockPadCfg (NW_GPIO_120);
+ GpioLockPadCfg (NW_GPIO_121);
+ GpioLockPadCfg (NW_GPIO_122);
+ GpioLockPadCfg (NW_GPIO_123);
+
+ //
+ // SPI
+ //
+ GpioLockPadCfg (NW_GPIO_97);
+ GpioLockPadCfg (NW_GPIO_98);
+ GpioLockPadCfg (NW_GPIO_99);
+ GpioLockPadCfg (NW_GPIO_100);
+ GpioLockPadCfg (NW_GPIO_101);
+ GpioLockPadCfg (NW_GPIO_102);
+ GpioLockPadCfg (NW_GPIO_103);
+ GpioLockPadCfg (NW_FST_SPI_CLK_FB);
+
+ //
+ // SMBus
+ // Set SMBus GPIO PAD_CFG.PADRSTCFG to Powergood
+ //
+ Data32 = GpioPadRead (SW_SMB_ALERTB);
+ Data32 &= ~(BIT31 | BIT30);
+ GpioPadWrite (SW_SMB_ALERTB, Data32);
+
+ Data32 = GpioPadRead (SW_SMB_CLK);
+ Data32 &= ~(BIT31 | BIT30);
+ GpioPadWrite (SW_SMB_CLK, Data32);
+
+ Data32 = GpioPadRead (SW_SMB_DATA);
+ Data32 &= ~(BIT31 | BIT30);
+ GpioPadWrite (SW_SMB_DATA, Data32);
+
+ GpioLockPadCfg (SW_SMB_ALERTB);
+ GpioLockPadCfg (SW_SMB_CLK);
+ GpioLockPadCfg (SW_SMB_DATA);
+}
+
+
+/**
+ Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+AuroraMultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINTN VariableSize;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+
+ (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+
+ VariableServices->GetVariable (
+ VariableServices,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+ DEBUG ((DEBUG_INFO, "AuroraMultiPlatformGpioProgram()...\n"));
+
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_AURORA:
+ //
+ // PAD programming
+ //
+ DEBUG ((DEBUG_INFO, "PAD programming, Board ID: 0x%X\n", PlatformInfoHob->BoardId));
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_N) / sizeof (mAuroraGpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_NW) / sizeof (mAuroraGpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_W) / sizeof (mAuroraGpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_SW) / sizeof (mAuroraGpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+
+ if (SystemConfiguration.ScIshEnabled == 0) {
+ DEBUG ((DEBUG_INFO, "Switch ISH_I2C0 & ISH_I2C1 to LPSS_I2C5 and LPSS I2C6. \n" ));
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_LPSS_I2C) / sizeof (mAuroraGpioInitData_LPSS_I2C[0]), mAuroraGpioInitData_LPSS_I2C);
+ }
+ break;
+ default:
+ //
+ // PAD programming
+ //
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_N) / sizeof (mAuroraGpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_NW) / sizeof (mAuroraGpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_W) / sizeof (mAuroraGpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_SW) / sizeof (mAuroraGpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+
+ if (SystemConfiguration.TDO == 2) { //Auto
+ if (BxtA0 == BxtStepping()) {
+ DEBUG ((DEBUG_INFO, " BxtA0 TDO disable\n" ));
+ }
+ } else if (SystemConfiguration.TDO == 0) { // Disable
+ DEBUG ((DEBUG_INFO, " Setup option to disable TDO\n" ));
+ }
+
+ if (SystemConfiguration.ScHdAudioIoBufferOwnership == 3) {
+ DEBUG ((DEBUG_INFO, "HD Audio IO Buffer Ownership is I2S. Change GPIO pin settings for it. \n" ));
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_Audio_SSP6) / sizeof (mAuroraGpioInitData_Audio_SSP6[0]), mAuroraGpioInitData_Audio_SSP6);
+ }
+
+ if (SystemConfiguration.PcieRootPortEn[4] == FALSE) {
+ DEBUG ((DEBUG_INFO, "Onboard LAN disable. \n" ));
+ GpioPadConfigTable (sizeof (AuroraLomDisableGpio) / sizeof (AuroraLomDisableGpio[0]), AuroraLomDisableGpio);
+ }
+
+ if (SystemConfiguration.EPIEnable == 1) {
+ DEBUG ((DEBUG_INFO, "Overriding GPIO 191 for EPI\n"));
+ GpioPadConfigTable (sizeof (mAuroraGpioInitData_EPI_Override) / sizeof (mAuroraGpioInitData_EPI_Override[0]), mAuroraGpioInitData_EPI_Override);
+ }
+ if (SystemConfiguration.GpioLock == TRUE) {
+ AuroraSetGpioPadCfgLock ();
+ }
+ DEBUG ((DEBUG_INFO, "No board ID available for this board ....\n"));
+ break;
+ }
+
+ //
+ // Dump Community registers
+ //
+ DumpGpioCommunityRegisters (NORTH);
+ DumpGpioCommunityRegisters (NORTHWEST);
+ DumpGpioCommunityRegisters (WEST);
+ DumpGpioCommunityRegisters (SOUTHWEST);
+
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_AURORA:
+ //
+ // PAD programming
+ //
+ DEBUG ((DEBUG_INFO, "Dump Community pad registers, Board ID: 0x%X\n", PlatformInfoHob->BoardId));
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_N) / sizeof (mAuroraGpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_NW) / sizeof (mAuroraGpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_W) / sizeof (mAuroraGpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_SW) / sizeof (mAuroraGpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+ break;
+ default:
+ //
+ // Dump Community pad registers
+ //
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_N) / sizeof (mAuroraGpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_NW) / sizeof (mAuroraGpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_W) / sizeof (mAuroraGpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ DumpGpioPadTable (sizeof (mAuroraGpioInitData_SW) / sizeof (mAuroraGpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.h new file mode 100644 index 0000000000..6e5313028e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardGpios.h @@ -0,0 +1,378 @@ +/** @file
+ GPIO setting for Broxton.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_BOARDGPIOS_H_
+#define _AURORA_BOARDGPIOS_H_
+
+#include <PiPei.h>
+#include"ChipsetAccess.h"
+#include"PlatformBaseAddresses.h"
+#include "BoardInitMiscs.h"
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo_Aplk.h>
+#include <Library/GpioLib.h>
+
+/**
+GPIO input pin interrupt type configuration:
+
+Interrupt type GPI Route Host SW Enable/Status Comment
+ GPI None GPIO Driver Mode GPI Interrupt Status\Enable GPIO driver to handle it.
+ Direct IRQ GPIROUTIOXAPIC ACPI Mode IRQ number is fixed to each GPIO pin in N and NW communities.
+ SCI/GPE GPIROUTSCI ACPI Mode GPI General Purpose Events Status\Enable SCI is not supported in BXT A0. The reason is because the PMC lacks the ACPI registers and status tunneling. This will be fixed in derivatives.
+ SMI GPIROUTSMI ACPI Mode SMI Status\Enable Don't enable SMI for BXT0. It is currently unsupported by the PMC.
+ NMI GPIROUTNMI ACPI Mode Not supported on BXT.
+
+Interrupt trigger type Configuration Comment
+ Rising edge Edge+No_invert
+ Falling edge Edge+Invert
+ Both edge BothEdge+Invert
+ Level high Level+No_invert Direct IRQ pin mostly use this config.Wake pin MUST use it.
+ Level low Level+Invert
+
+HostSw:
+ * All GPIO pins which are 'M0' PMode, have to set HostSw to GPIO_D, indicating GPIO driver owns it.
+ * Others, such as Native function(M1,M2,M3..) and SCI/SMI/NMI/Direct IRQ, need to set it to ACPI_D or NA.
+ * Default is ACPI_D for NA
+
+IOSstate:
+ * For interrupt or wake pin, need to set it to TxDRxE.
+
+Wake_Enabled:
+ * It is for direct IRQ only.
+
+**/
+
+//
+// North Community
+//
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_N[] =
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset ,Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_0", M0 , GPO , GPIO_D ,HI , NA , Wake_Disabled, P_5K_L , NA , NA,NA , NA , GPIO_PADBAR+0x0000, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_1", M0 , GPO , GPIO_D ,HI , NA , Wake_Disabled, P_5K_L , NA , NA,NA , NA , GPIO_PADBAR+0x0008, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0010, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_3", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0018, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_4", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0020, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_5", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0028, NORTH),//Mux with CSE_PG based on the SW3 switch
+ BXT_GPIO_PAD_CONF(L"GPIO_6", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0030, NORTH),//Mux with DISP1_RST_N based on the SW3 switch
+ BXT_GPIO_PAD_CONF(L"GPIO_7", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0038, NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
+ BXT_GPIO_PAD_CONF(L"GPIO_8", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0040, NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
+ BXT_GPIO_PAD_CONF(L"GPIO_9", M0 , GPO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0048, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPO , NA , NA , NA , Wake_Enabled , P_20K_L, Inverted,IOAPIC, TxDRxE , NA, GPIO_PADBAR+0x0050, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_11", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0058, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_12", M1 , NA , NA , NA , NA , Wake_Enabled , P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0060, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_13", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0068, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA , NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch: SIM_CON_CD1, falling edge trigger
+ BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
+ BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00B0, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0
+ BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D , NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch: SATA_ODD_DA_IN
+ BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN
+ BXT_GPIO_PAD_CONF(L"GPIO_27", M0 , GPO ,GPIO_D , HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00D8, NORTH),//Feature:DFU Net in Sch: NFC_DFU
+ BXT_GPIO_PAD_CONF(L"GPIO_28", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00E0, NORTH),// Net in Sch: ISH_GPIO10
+ BXT_GPIO_PAD_CONF(L"GPIO_29", M0 , GPO ,GPIO_D , HI , NA , Wake_Disabled, P_NONE, NA , NA, NA , NA, GPIO_PADBAR+0x00E8, NORTH),// SOC_M2_RST
+ //BXT_GPIO_PAD_CONF(L"GPIO_30", M0 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00F0, NORTH),// FAB ID, Programmed by earlier FAB ID detection code.
+ BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00F8, NORTH),//Feature: SUSCLK1
+ BXT_GPIO_PAD_CONF(L"GPIO_32", M5 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0100, NORTH),// Net in Sch: SUSCLK2
+ BXT_GPIO_PAD_CONF(L"GPIO_33", M5 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0108, NORTH),//Feature: SUSCLK3
+ BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x0110, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_5K_H , NA , NA, NA , NA, GPIO_PADBAR+0x0118, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x0120, NORTH),//Feature: PWM
+ BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,DisPuPd, GPIO_PADBAR+0x0130, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M0 , GPI , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,DisPuPd, GPIO_PADBAR+0x0138, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_40 LPSS_UART0_RTS_B", M0 , GPI , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,DisPuPd, GPIO_PADBAR+0x0140, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_41 LPSS_UART0_CTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,DisPuPd, GPIO_PADBAR+0x0148, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_42 LPSS_UART1_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,DisPuPd, GPIO_PADBAR+0x0150, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_43 LPSS_UART1_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I,DisPuPd, GPIO_PADBAR+0x0158, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_44 LPSS_UART1_RTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,DisPuPd, GPIO_PADBAR+0x0160, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_45 LPSS_UART1_CTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA, HizRx0I,DisPuPd, GPIO_PADBAR+0x0168, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_46 LPSS_UART1_CTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA, HizRx0I,DisPuPd, GPIO_PADBAR+0x0170, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_47 LPSS_UART1_CTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA, HizRx0I,DisPuPd, GPIO_PADBAR+0x0178, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_48 LPSS_UART2_RTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0180, NORTH),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0188, NORTH),//Feature: LPSS_UART1
+ BXT_GPIO_PAD_CONF(L"GPIO_62 GP_CAMERASB00", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x0190, NORTH),//CAM_FLASH_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_63 GP_CAMERASB01", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x0198, NORTH),//CAM_FLASH_TORCH
+ BXT_GPIO_PAD_CONF(L"GPIO_64 GP_CAMERASB02", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01A0, NORTH),//CAM_FLASH_TRIG
+ BXT_GPIO_PAD_CONF(L"GPIO_65 GP_CAMERASB03", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01A8, NORTH),//CAM_GRP1_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_66 GP_CAMERASB04", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01B0, NORTH),//CAM_GRP2_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_67 GP_CAMERASB05", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01B8, NORTH),//CAM_GRP3_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_68 GP_CAMERASB06", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01C0, NORTH),//CAM_GRP4_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_69 GP_CAMERASB07", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01C8, NORTH),//CAM_XENON_CHRG
+ BXT_GPIO_PAD_CONF(L"GPIO_70 GP_CAMERASB08", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01D0, NORTH),//CAM_AFLED_TRIG
+ BXT_GPIO_PAD_CONF(L"GPIO_71 GP_CAMERASB09", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01D8, NORTH),//CAM_SPARE
+ BXT_GPIO_PAD_CONF(L"GPIO_72 GP_CAMERASB10", M0 , GPI , GPIO_D, NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01E0, NORTH),//CAM_SPARE
+ BXT_GPIO_PAD_CONF(L"GPIO_73 GP_CAMERASB11", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, NA, GPIO_PADBAR+0x01E8, NORTH),//CAM_SPARE
+ BXT_GPIO_PAD_CONF(L"TCK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x01F0, NORTH),
+ BXT_GPIO_PAD_CONF(L"TRST_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x01F8, NORTH),
+ BXT_GPIO_PAD_CONF(L"TMS", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0200, NORTH),
+ BXT_GPIO_PAD_CONF(L"TDI", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0208, NORTH),
+ BXT_GPIO_PAD_CONF(L"CX_PMODE", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0210, NORTH),
+ BXT_GPIO_PAD_CONF(L"CX_PREQ_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0218, NORTH),
+ BXT_GPIO_PAD_CONF(L"JTAGX", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0220, NORTH),
+ BXT_GPIO_PAD_CONF(L"CX_PRDY_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0228, NORTH),
+ BXT_GPIO_PAD_CONF(L"TDO", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0230, NORTH),
+ BXT_GPIO_PAD_CONF(L"CNV_BRI_DT", M0 , GPI , GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0238, NORTH),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_217 CNV_BRI_RSP", M0 , GPI , GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0240, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_218 CNV_RGI_DT", M0 , GPO , GPIO_D, HI , NA , Wake_Disabled, P_1K_H , NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTH),
+ BXT_GPIO_PAD_CONF(L"GPIO_219 CNV_RGI_RSP", M1 , NA , NA, HI , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0250, NORTH),//EMMC Reset
+ BXT_GPIO_PAD_CONF(L"SVID0_ALERT_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0258, NORTH),
+ BXT_GPIO_PAD_CONF(L"SVID0_DATA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0260, NORTH),
+ BXT_GPIO_PAD_CONF(L"SVID0_CLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0268, NORTH),
+};
+
+//
+// North West Community
+//
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_NW [] =
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_187 HV_DDI0_DDC_SDA", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx0I , SAME, GPIO_PADBAR+0x0000, NORTHWEST),//DDI0_CTRL_DATA
+ BXT_GPIO_PAD_CONF(L"GPIO_188 HV_DDI0_DDC_SCL", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx0I , SAME, GPIO_PADBAR+0x0008, NORTHWEST),//DDI0_CTRL_CLK
+ BXT_GPIO_PAD_CONF(L"GPIO_189 HV_DDI1_DDC_SDA", M1 , NA , NA , NA , NA ,Wake_Disabled, P_2K_H, NA , NA ,NA , NA, GPIO_PADBAR+0x0010, NORTHWEST),//DDI1_CTRL_DATA
+ BXT_GPIO_PAD_CONF(L"GPIO_190 HV_DDI1_DDC_SCL", M1 , NA , NA , NA , NA ,Wake_Disabled, P_2K_H, NA , NA ,NA , NA, GPIO_PADBAR+0x0018, NORTHWEST),//DDI1_CTRL_CLK
+ BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M0 , HI_Z ,GPIO_D, HI , NA ,Wake_Disabled, P_20K_H, NA , NA ,NA , NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: SD_I2C MUX SEL Net in Sch: INA_MUX_SEL // Due to Silicon bug, unable to set GPIO to 1 - changed to HI_Z
+ BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M0 , GPO ,GPIO_D, LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: Codec Power Down PD Net in Sch: SOC_CODEC_PD_N
+ BXT_GPIO_PAD_CONF(L"GPIO_193 PANEL0_VDDEN", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , SAME, GPIO_PADBAR+0x0030, NORTHWEST),//DISP0_VDDEN
+ BXT_GPIO_PAD_CONF(L"GPIO_194 PANEL0_BKLTEN", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , SAME, GPIO_PADBAR+0x0038, NORTHWEST),//DISP0_BKLTEN
+ BXT_GPIO_PAD_CONF(L"GPIO_195 PANEL0_BKLTCTL", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , SAME, GPIO_PADBAR+0x0040, NORTHWEST),//DISP0_BLTCTL
+ BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN
+ BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN
+ BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL
+ BXT_GPIO_PAD_CONF(L"GPIO_199 DBI_CSX", M2 , NA , NA , NA , NA ,Wake_Disabled, P_NONE, NA , NA ,NA , NA, GPIO_PADBAR+0x0060, NORTHWEST),//HDMI_HPD
+ BXT_GPIO_PAD_CONF(L"GPIO_200 DBI_RESX", M2 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,NA , NA, GPIO_PADBAR+0x0068, NORTHWEST),//EDP_HPD
+ BXT_GPIO_PAD_CONF(L"GPIO_201 GP_INTD_DSI_TE1", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , SAME, GPIO_PADBAR+0x0070, NORTHWEST),//DISP_INTD_TE1
+ BXT_GPIO_PAD_CONF(L"GPIO_202 GP_INTD_DSI_TE2", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , SAME, GPIO_PADBAR+0x0078, NORTHWEST),//DISP_INTD_TE2
+ BXT_GPIO_PAD_CONF(L"GPIO_203 USB_OC0_B", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0080, NORTHWEST),//HOST_USB_OC_N
+ BXT_GPIO_PAD_CONF(L"GPIO_204 USB_OC1_B", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0088, NORTHWEST),//OTG_USB_OC_N, PMIC_GPIO0_P0_UIBT
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_FS0", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x0090, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_FS1", M2 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x0098, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_FS2", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00A0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_RXD", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00A8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_TXD", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00B0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMC_SPI_CLK", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00B8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMIC_PWRGOOD", M0 , GPO ,GPIO_D, HI , NA ,Wake_Disabled, P_1K_H , NA , NA ,NA , NA, GPIO_PADBAR+0x00C0, NORTHWEST),//Feature: Reset Net in Sch: GNSS_RST_N
+ BXT_GPIO_PAD_CONF(L"PMIC_RESET_B", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x00C8, NORTHWEST),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_213 PMIC_SDWN_B", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00D0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_214 PMIC_BCUDISW2", M0 , GPO ,GPIO_D, HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x00D8, NORTHWEST),//Feature: BT WAKE to Device Net in Sch: NGFF_BT_DEV_WAKE_N
+ BXT_GPIO_PAD_CONF(L"GPIO_215 PMIC_BCUDISCRIT", M0 , GPO ,GPIO_D, HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x00E0, NORTHWEST),//Feature: RF_KILL_GPS Net in Sch: RF_KILL_GPS_1P8_N
+ BXT_GPIO_PAD_CONF(L"PMIC_THERMTRIP_B", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, SAME, GPIO_PADBAR+0x00E8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMIC_STDBY", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x00F0, NORTHWEST),//Feature: WIFI_Disable Net in Sch: WIFI_DISABLE1_1P8_N
+ BXT_GPIO_PAD_CONF(L"PROCHOT_B", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I , SAME, GPIO_PADBAR+0x00F8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMIC_I2C_SCL", M1 , NA , NA , NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0100, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"PMIC_I2C_SDA", M1 , NA , NA , NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0108, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:AVS_I2S1_MCLK
+ BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:AVS_I2S1_BCLK
+ BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0 , GPO ,GPIO_D, HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0120, NORTHWEST),//Feature:Wake
+ BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPI , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:LPE Hdr
+ BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPI ,GPIO_D ,NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:LPE Hdr
+ BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , SAME, GPIO_PADBAR+0x0138, NORTHWEST),// FAB B DMIC
+ BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , SAME, GPIO_PADBAR+0x0140, NORTHWEST),// FAB B DMIC
+ BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0148, NORTHWEST),// FAB B DMIC
+ BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M0 , GPI ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0150, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_83 AVS_M_DATA_2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0158, NORTHWEST),// FAB B DMIC
+ BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net in Sch:HDA_RSTB
+ BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0168, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0170, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0178, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0180, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_89 AVS_I2S3_BCLK", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0188, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_90 AVS_I2S3_WS_SYNC", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x0190, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_91 AVS_I2S3_SDI", M1 , NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , EnPd, GPIO_PADBAR+0x0198, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_92 AVS_I2S3_SDO", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01A0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_97 FST_SPI_CS0_B", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01A8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_98 FST_SPI_CS1_B", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01B0, NORTHWEST),//TPM_SPI_CS1
+ BXT_GPIO_PAD_CONF(L"GPIO_99 FST_SPI_MOSI_IO0", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01B8, NORTHWEST), //Default for BXT is Native
+ BXT_GPIO_PAD_CONF(L"GPIO_100 FST_SPI_MISO_IO1",M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01C0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_101 FST_SPI_IO2", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01C8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_102 FST_SPI_IO3", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01D0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_103 FST_SPI_CLK", M1 , NA , NA , NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01D8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"FST_SPI_CLK_FB", M1 , NA , NA , NA , NA ,Wake_Disabled, P_NONE , NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+0x01E0, NORTHWEST),//no pin out
+ BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x01E8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x01F0, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M0 , GPI , GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x01F8, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0200, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0208, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0218, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPO ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr
+ BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPIO , GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr
+ BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0238, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0240, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0250, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0258, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0260, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA
+ BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL
+ BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN
+ BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN
+ BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL
+};
+
+//
+// West Community
+//
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_W [] =
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_124 LPSS_I2C0_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0000, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_125 LPSS_I2C0_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0008, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_126 LPSS_I2C1_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0010, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_127 LPSS_I2C1_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0018, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_128 LPSS_I2C2_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0020, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_129 LPSS_I2C2_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0028, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_130 LPSS_I2C3_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0030, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_131 LPSS_I2C3_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0038, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_132 LPSS_I2C4_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0040, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_133 LPSS_I2C4_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, EnPu, GPIO_PADBAR+0x0048, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_138 LPSS_I2C7_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, EnPu, GPIO_PADBAR+0x0070, WEST),// RFKILL_N
+ BXT_GPIO_PAD_CONF(L"GPIO_139 LPSS_I2C7_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, EnPu, GPIO_PADBAR+0x0078, WEST),//HALL_STATE
+ BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0080, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0088, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0090, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0098, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00A0, WEST),//Feature: AVS_I2S5_BCLK
+ BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00A8, WEST),//Feature: RF_KILL_WWAN Net in Sch: NGFF_WWAN_RF_KILL_1P8_N
+ BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00B0, WEST),//Feature: AVS_I2S5_SDI
+ BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00B8, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00C0, WEST),//Feature: BT_Disable Net in Sch: BT_DISABLE2_1P8_N
+ BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9", M0 , GPI ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00C8, WEST),//CG2000 PDB: If PDB = 0: power-down; If PDB = 1: power-up, it is the same in ISH/LPSS mode
+ BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00D0, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00D8, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_211 PCIE_CLKREQ2_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00E0, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_212 PCIE_CLKREQ3_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00E8, WEST),
+ BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00F0, WEST),
+ BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00F8, WEST),
+ BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x0100, WEST),
+ BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_3", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x0108, WEST),
+ BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_4", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x0110, WEST),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"PMU_AC_PRESENT", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0118, WEST),//Check, OBS
+ BXT_GPIO_PAD_CONF(L"PMU_BATLOW_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0120, WEST),//Check, OBS
+ BXT_GPIO_PAD_CONF(L"PMU_PLTRST_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0128, WEST),
+ BXT_GPIO_PAD_CONF(L"PMU_PWRBTN_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0130, WEST),
+ BXT_GPIO_PAD_CONF(L"PMU_RESETBUTTON_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0138, WEST),
+ BXT_GPIO_PAD_CONF(L"PMU_SLP_S0_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0140, WEST),//Check, OBS
+ BXT_GPIO_PAD_CONF(L"PMU_SLP_S3_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0148, WEST),//Check, OBS
+ BXT_GPIO_PAD_CONF(L"PMU_SLP_S4_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0150, WEST),
+ BXT_GPIO_PAD_CONF(L"PMU_SUSCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0158, WEST),
+ BXT_GPIO_PAD_CONF(L"PMU_WAKE_B", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0160, WEST),//Power cycling for EMMC/RVP
+ BXT_GPIO_PAD_CONF(L"SUS_STAT_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0168, WEST),
+ BXT_GPIO_PAD_CONF(L"SUSPWRDNACK", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0170, WEST),
+};
+
+ //
+ // South West Community
+ //
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_SW[]=
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_205 PCIE_WAKE0_B", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked,SAME ,GPIO_PADBAR+0x0000 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_206 PCIE_WAKE1_B", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked,SAME ,GPIO_PADBAR+0x0008 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_207 PCIE_WAKE2_B", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked,SAME ,GPIO_PADBAR+0x0010 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_208 PCIE_WAKE3_B", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked,SAME ,GPIO_PADBAR+0x0018 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_156 EMMC0_CLK", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I ,SAME ,GPIO_PADBAR+0x0020 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_157 EMMC0_D0", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0028 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_158 EMMC0_D1", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0030 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_159 EMMC0_D2", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0038 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_160 EMMC0_D3", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0040 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_161 EMMC0_D4", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0048 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_162 EMMC0_D5", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0050 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_163 EMMC0_D6", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0058 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_164 EMMC0_D7", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0060 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_165 EMMC0_CMD", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0068 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_166 SDIO_CLK", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I ,SAME ,GPIO_PADBAR+0x0070 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_167 SDIO_D0", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0078 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_168 SDIO_D1", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0080 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_169 SDIO_D2", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0088 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_170 SDIO_D3", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0090 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_171 SDIO_CMD", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x0098 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_172 SDCARD_CLK", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx1I ,DisPuPd,GPIO_PADBAR+0x00A0 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_179 SDCARD_CLK_FB", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA ,NA ,GPIO_PADBAR+0x00A8 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_173 SDCARD_D0", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,DisPuPd,GPIO_PADBAR+0x00B0 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_174 SDCARD_D1", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x00B8 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_175 SDCARD_D2", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x00C0 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_176 SDCARD_D3", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,SAME ,GPIO_PADBAR+0x00C8 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D , NA , Edge ,Wake_Disabled, P_NONE, NA , NA ,TxDRxE , NA, GPIO_PADBAR+ 0x00D0 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_178 SDCARD_CMD", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I ,DisPuPd,GPIO_PADBAR+0x00D8 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M0, GPI , GPIO_D , NA , Edge ,Wake_Disabled, P_20K_L,Inverted , NA ,Last_Value, SAME,GPIO_PADBAR+0x00E0 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_182 EMMC0_STROBE", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I ,SAME ,GPIO_PADBAR+0x00E8 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_183 SDIO_PWR_DOWN_B", M0, GPO , GPIO_D , LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA ,NA ,GPIO_PADBAR+0x00F0 , SOUTHWEST),// Feature:Power Enable Net in Sch:SD_CARD_PWR_EN_N
+ BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M1, NA , NA , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+ 0x00F8 , SOUTHWEST),//Feature: SMB_ALERTB
+ BXT_GPIO_PAD_CONF(L"LPC_AD0", M0, GPO , GPIO_D , LO , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+ 0x0128 , SOUTHWEST),
+ BXT_GPIO_PAD_CONF(L"LPC_AD1", M0, GPO , GPIO_D , LO , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, SAME, GPIO_PADBAR+ 0x0130 , SOUTHWEST),
+};
+
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_Audio_SSP6 []=
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IOSTerm,MMIO_Offset, Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0080, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0088, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0090, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x0098, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net in Sch:HDA_RSTB
+ BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M0 , GPI , NA , NA , Level , Wake_Disabled, P_20K_H, NA ,IOAPIC,TxDRxE , NA , GPIO_PADBAR+0x0228, NORTHWEST),//Feature: Interrput Net in Sch: SOC_CODEC_IRQ
+ BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M0 , HI_Z ,GPIO_D, HI , NA , Wake_Disabled, P_2K_H, NA , NA,NA , NA , GPIO_PADBAR+0x0028, NORTHWEST),//Feature: Codec Power Down PD Net in Sch: SOC_CODEC_PD_N
+};
+
+//
+// GPIO 191 is only used if EPI reworks are applied on the board. This GPIO switches between SD Card data (if set to 1) and EPI data (if set to 0).
+//
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_EPI_Override[] =
+{
+ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset ,Community
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M0, GPO, GPIO_D,LO, NA, Wake_Disabled,P_20K_L, NA, NA, NA, NA, GPIO_PADBAR + 0x0020, NORTHWEST),//Feature: SD_I2C MUX SEL Net in Sch: INA_MUX_SEL
+};
+
+BXT_GPIO_PAD_INIT mAuroraGpioInitData_LPSS_I2C[] =
+{
+ BXT_GPIO_PAD_CONF(L"GPIO_134 LPSS_I2C5_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x0050, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_135 LPSS_I2C5_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x0058, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_136 LPSS_I2C6_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x0060, WEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_137 LPSS_I2C6_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x0068, WEST),
+};
+
+
+BXT_GPIO_PAD_INIT AuroraLomDisableGpio[] =
+{
+ //
+ // LAN
+ //
+ BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x00D8, WEST), // CLKREQ#
+ BXT_GPIO_PAD_CONF(L"GPIO_37 PWM3", M0 , GPO , GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x0128, NORTH), // PERST#
+};
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c new file mode 100644 index 0000000000..2f33bfe21e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c @@ -0,0 +1,183 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInit.h"
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPostMemInitCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mAuroraGlacierPostMemNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPostMemInitStartGuid,
+ AuroraGlacierPostMemInitCallback
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAuroraGlacierPostMemDonePpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPostMemInitDoneGuid,
+ NULL
+};
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPostMemInitCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ VOID *Instance;
+ UINT8 BoardId;
+ UINT8 FabId;
+ UINT8 ResetType;
+ UINTN BufferSize;
+ UINT8 MaxPkgCState;
+ UINTN VariableSize;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+
+ (*PeiServices)->LocatePpi (
+ (CONST EFI_PEI_SERVICES **)PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+
+ VariableServices->GetVariable (
+ VariableServices,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+ Status = PeiServicesLocatePpi (
+ &gBoardPostMemInitDoneGuid,
+ 0,
+ NULL,
+ &Instance
+ );
+ if (!EFI_ERROR (Status)) {
+ return EFI_SUCCESS;
+ }
+
+ BoardId = (UINT8) PcdGet8 (PcdBoardId);
+ FabId = (UINT8) PcdGet8 (PcdFabId);
+ DEBUG ((EFI_D_INFO, "PostMemInit: BoardId == 0x%X, FabId == 0x%X\n", BoardId, FabId));
+ if (BoardId != (UINT8) BOARD_ID_AURORA) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "Aurora Glacier Post Mem Init callback\n"));
+
+ //
+ // Set init function PCD
+ //
+ PcdSet64 (PcdBoardPostMemInitFunc, (UINT64) (UINTN) AuroraMultiPlatformInfoInit);
+
+ //
+ // Set Reset Type according to different Board
+ //
+ ResetType = V_RST_CNT_HARDRESET;
+ PcdSet8 (PcdResetType, (UINT8) ResetType);
+
+ //
+ // Board specific VBT table.
+ //
+ BufferSize = sizeof (EFI_GUID);
+ PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiAuroraGlacierVbtGuid);
+
+ //
+ // Set PcdSueCreek
+ //
+ if (SystemConfiguration.SueCreekBypass) {
+ PcdSetBool (PcdSueCreek, FALSE);
+ PcdSetBool (PcdTi3100AudioCodecEnable, TRUE);
+ DEBUG ((EFI_D_INFO, "Bypass SueCreek \n"));
+ } else {
+ PcdSetBool (PcdSueCreek, TRUE);
+ PcdSetBool (PcdTi3100AudioCodecEnable, FALSE);
+ DEBUG ((EFI_D_INFO, "Use SueCreek \n"));
+ }
+
+ //
+ // Set PcdMaxPkgCState
+ //
+ MaxPkgCState = MAX_PKG_CSTATE_C2;
+ PcdSet8 (PcdMaxPkgCState, (UINT8) MaxPkgCState);
+
+ //
+ // Set PcdeMMCHostMaxSpeed
+ //
+ PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) (SystemConfiguration.ScceMMCHostMaxSpeed));
+
+ //
+ // I2S NHLT Virtual Bus ID
+ //
+ PcdSet8(HdaEndpointBtRenderVirtualBusId, 0x0F); // N/A
+ PcdSet8(HdaEndpointBtCaptureVirtualBusId, 0x0F); // N/A
+ PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 1); // I2S2
+ PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 1); // I2S2
+ PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1); // I2S2
+
+ //
+ // Add init steps here
+ //
+ //
+ // Install a flag signalling a board's post mem init is done
+ //
+ Status = PeiServicesInstallPpi (&mAuroraGlacierPostMemDonePpi);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraGlacierInitConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "AuroraGlacier Post Mem Init Constructor \n"));
+
+ DEBUG ((EFI_D_INFO, "Notify on Post Mem Init Start PPI \n"));
+ Status = PeiServicesNotifyPpi (&mAuroraGlacierPostMemNotifyList);
+
+ return Status;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.h new file mode 100644 index 0000000000..8d6fcbadec --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.h @@ -0,0 +1,41 @@ +/** @file
+ GPIO setting for Aurora.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_BOARDINIT_H_
+#define _AURORA_BOARDINIT_H_
+
+#include <PiPei.h>
+
+#include <Guid/PlatformInfo_Aplk.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/TimerLib.h>
+
+#include <Ppi/BoardInitSignalling.h>
+
+#include "BoardInitMiscs.h"
+#include <ScRegs/RegsPcu.h>
+
+VOID AuroraGpioTest (VOID);
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.c new file mode 100644 index 0000000000..37dcdf8acb --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.c @@ -0,0 +1,213 @@ +/** @file
+ This file does Multiplatform initialization.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitMiscs.h"
+
+/**
+ Configure GPIO group GPE tier.
+
+ @param[in] PlatformInfo
+
+ @retval none.
+
+**/
+VOID
+AuroraGpioGroupTierInit (
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ DEBUG ((DEBUG_INFO, "AuroraGpioGroupTierInit Start\n"));
+ switch (PlatformInfoHob->BoardId) {
+ default:
+ GpioSetGroupToGpeDwX (GPIO_BXTP_GROUP_7, // map group 7 to GPE 0 ~ 31
+ GPIO_BXTP_GROUP_0, // map group 0 to GPE 32 ~ 63 // We don't have SCI pin in Group0 as of now, but still need to assign a unique group to this field.
+ GPIO_BXTP_GROUP_1); // map group 1 to GPE 64 ~ 95 // We don't have SCI pin in Group1 as of now, but still need to assign a unique group to this field.
+ break;
+ }
+
+ DEBUG ((DEBUG_INFO, "AuroraGpioGroupTierInit End\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+AuroraMultiPlatformInfoInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT8 Data8;
+ EFI_STATUS Status;
+
+#if (ENBDT_PF_ENABLE == 1)
+ DEBUG ((EFI_D_INFO, "Platform BoardId:%x FabId%x\n", PlatformInfoHob->BoardId, PlatformInfoHob->FABID));
+#endif
+
+ //
+ // Device ID
+ //
+ PlatformInfoHob->IohSku = MmPci16 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PCI_DEVICE_ID_OFFSET);
+
+ PlatformInfoHob->IohRevision = MmPci8 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PCI_REVISION_ID_OFFSET);
+
+ //
+ // Don't support BASE above 4GB currently
+ //
+ PlatformInfoHob->PciData.PciExpressSize = 0x04000000;
+ PlatformInfoHob->PciData.PciExpressBase = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+
+ PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
+ PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
+
+ PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
+ PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
+ PlatformInfoHob->CpuData.CpuAddressWidth = 36;
+
+ PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
+ PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
+
+ PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
+
+ //
+ // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base
+ //
+ if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
+ } else {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
+ }
+ PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
+
+ //
+ // Platform PCI MMIO Size in unit of 1MB
+ //
+ PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16) (PlatformInfoHob->MemData.MemMaxTolm >> 20);
+
+ //
+ // Enable ICH IOAPIC
+ //
+ PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
+
+ DEBUG ((EFI_D_INFO, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor, FlavorTablet, FlavorMobile, FlavorDesktop));
+
+ //
+ // Get Platform Info and fill the Hob
+ //
+ PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
+
+ //
+ // Get GPIO table
+ //
+ Status = AuroraMultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Program GPIO
+ //
+ Status = AuroraMultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
+
+ if (GetBxtSeries () == BxtP) {
+ AuroraGpioGroupTierInit (PlatformInfoHob);
+ }
+
+ //
+ // Update OemId
+ //
+ Status = AuroraInitializeBoardOemId (PeiServices, PlatformInfoHob);
+ Status = AuroraInitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
+
+ //
+ // TypeC MUX AUX mode
+ //
+
+ //
+ // Set P0-P4 to input mode
+ //
+ Data8 = 0x1F;
+ Status = ByteWriteI2C (0x05, 0x38, 0x03, 1, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Setting button MUX into GPI mode returned %r\n", __FUNCTION__, __LINE__, Status));
+
+ //
+ // Set P0-P4 to inverted mode
+ //
+ Data8 = 0x1F;
+ Status = ByteWriteI2C (0x05, 0x38, 0x02, 1, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Setting button MUX into inverted mode returned %r\n", __FUNCTION__, __LINE__, Status));
+
+ //
+ // Dump switch state
+ //
+ Data8 = 0x00;
+ Status = ByteReadI2C (0x05, 0x38, 0x00, 1, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - ByteReadI2C[0] returned %r\n", __FUNCTION__, __LINE__, Status));
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Input register = %02x\n", __FUNCTION__, __LINE__, Data8));
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Volume + = %a\n", __FUNCTION__, __LINE__, (Data8 & BIT0) ? "Pressed" : "Not pressed"));
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Volume - = %a\n", __FUNCTION__, __LINE__, (Data8 & BIT1) ? "Pressed" : "Not pressed"));
+ DEBUG ((DEBUG_INFO, "%a(#%d) - BT Pair = %a\n", __FUNCTION__, __LINE__, (Data8 & BIT2) ? "Pressed" : "Not pressed"));
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Mic Mute = %a\n", __FUNCTION__, __LINE__, (Data8 & BIT3) ? "Pressed" : "Not pressed"));
+ DEBUG ((DEBUG_INFO, "%a(#%d) - Speaker Mute = %a\n", __FUNCTION__, __LINE__, (Data8 & BIT4) ? "Pressed" : "Not pressed"));
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+AuroraInitializeBoardOemId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT64 OemId;
+ UINT64 OemTableId;
+
+ //
+ // Set OEM ID according to Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+ default:
+ OemId = EFI_ACPI_OEM_ID_DEFAULT;
+ OemTableId = EFI_ACPI_OEM_TABLE_ID_DEFAULT;
+ break;
+ }
+
+ PlatformInfoHob->AcpiOemId = OemId;
+ PlatformInfoHob->AcpiOemTableId = OemTableId;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+AuroraInitializeBoardSsidSvid (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT32 SsidSvidValue = 0;
+
+ //
+ // Set OEM ID according to Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+ default:
+ SsidSvidValue = SUBSYSTEM_SVID_SSID; //SUBSYSTEM_SVID_SSID_DEFAULT;
+ break;
+ }
+ PlatformInfoHob->SsidSvid = SsidSvidValue;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.h new file mode 100644 index 0000000000..f91550542a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitMiscs.h @@ -0,0 +1,152 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_MULTIPLATFORM_LIB_H_
+#define _AURORA_MULTIPLATFORM_LIB_H_
+
+#define LEN_64M 0x4000000
+//
+// Default PCI32 resource size
+//
+#define RES_MEM32_MIN_LEN 0x38000000
+
+#define RES_IO_BASE 0x0D00
+#define RES_IO_LIMIT 0xFFFF
+
+#include <PiDxe.h>
+#include <FrameworkPei.h>
+
+#include "CMOSMap.h"
+#include "CpuRegs.h"
+#include "Platform.h"
+#include "PlatformBaseAddresses.h"
+#include "PlatformBootMode.h"
+#include "ScAccess.h"
+#include "SetupMode.h"
+
+#include <Guid/Capsule.h>
+#include <Guid/EfiVpdData.h>
+#include <Guid/FirmwareFileSystem.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/PlatformInfo_Aplk.h>
+#include <Guid/RecoveryDevice.h>
+#include <Guid/SetupVariable.h>
+
+#include <IndustryStandard/Pci22.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SteppingLib.h>
+#include <Library/TimerLib.h>
+
+#include <Ppi/AtaController.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/Capsule.h>
+#include <Ppi/DeviceRecoveryModule.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Ppi/MasterBootMode.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/Reset.h>
+#include <Ppi/Stall.h>
+
+#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', ' ', ' ') // max 6 chars
+#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ') // max 6 chars
+#define EFI_ACPI_OEM_ID2 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '2', ' ', ' ') // max 6 chars
+
+#define EFI_ACPI_OEM_TABLE_ID_DEFAULT SIGNATURE_64('E', 'D', 'K', '2', ' ', ' ', ' ', ' ')
+#define EFI_ACPI_OEM_TABLE_ID1 SIGNATURE_64('E', 'D', 'K', '2', '_', '1', ' ', ' ')
+#define EFI_ACPI_OEM_TABLE_ID2 SIGNATURE_64('E', 'D', 'K', '2', '_', '2', ' ', ' ')
+
+//
+// Default Vendor ID and Subsystem ID
+//
+#define SUBSYSTEM_VENDOR_ID1 0x8086
+#define SUBSYSTEM_DEVICE_ID1 0x1999
+#define SUBSYSTEM_SVID_SSID1 (SUBSYSTEM_VENDOR_ID1 + (SUBSYSTEM_DEVICE_ID1 << 16))
+
+#define SUBSYSTEM_VENDOR_ID2 0x8086
+#define SUBSYSTEM_DEVICE_ID2 0x1888
+#define SUBSYSTEM_SVID_SSID2 (SUBSYSTEM_VENDOR_ID2 + (SUBSYSTEM_DEVICE_ID2 << 16))
+
+#define SUBSYSTEM_VENDOR_ID 0x8086
+#define SUBSYSTEM_DEVICE_ID 0x1234
+#define SUBSYSTEM_SVID_SSID (SUBSYSTEM_VENDOR_ID + (SUBSYSTEM_DEVICE_ID << 16))
+
+//
+// MaxPkgCState identifier.
+//
+#define MAX_PKG_CSTATE_C0 0x00
+#define MAX_PKG_CSTATE_C1 0x01
+#define MAX_PKG_CSTATE_C2 0x02
+
+EFI_STATUS
+AuroraGetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ );
+
+EFI_STATUS
+AuroraMultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+AuroraMultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+AuroraMultiPlatformInfoInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+AuroraInitializeBoardOemId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+AuroraInitializeBoardSsidSvid (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+VOID
+DumpMux (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+SetupTypecMuxAux (
+ VOID
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf new file mode 100644 index 0000000000..f47cb4f285 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf @@ -0,0 +1,93 @@ +## @file
+# Board detected module for Intel(R) Atom(TM) E3900 Processor Series.
+# It will detect the board ID.
+#
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = AuroraGlacierInitPostMem
+ FILE_GUID = EF883035-D771-438C-9D02-ACF102AA7D13
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = AuroraGlacierInitConstructor
+
+[Sources]
+ BoardInit.c
+ BoardInit.h
+ BoardInitMiscs.c
+ BoardInitMiscs.h
+ PlatformInfoHob.c
+ BoardGpios.c
+ BoardGpios.h
+ TypeC.c
+ TypeC.h
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+ DebugLib
+ HeciMsgLib
+ HobLib
+ IoLib
+ SteppingLib
+ GpioLib
+ I2cLibPei
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid
+ gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress
+ gPlatformModuleTokenSpaceGuid.PcdBoardPostMemInitFunc
+ gPlatformModuleTokenSpaceGuid.PcdBoardId
+ gPlatformModuleTokenSpaceGuid.PcdFabId
+ gPlatformModuleTokenSpaceGuid.PcdResetType
+ gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
+ gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
+ gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
+ gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed
+ gEfiBxtTokenSpaceGuid.HdaEndpointBtRenderVirtualBusId
+ gEfiBxtTokenSpaceGuid.HdaEndpointBtCaptureVirtualBusId
+ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId
+ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId
+ gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gEfiAuthenticatedVariableGuid
+ gEfiVariableGuid
+ gPeiVariableCacheHobGuid
+ gEfiTpmDeviceSelectedGuid
+ gEfiTpmDeviceInstanceNoneGuid
+ gEfiTpmDeviceInstanceTpm12Guid
+ gEfiTpmDeviceInstanceTpm20DtpmGuid
+ gTpmDeviceInstanceTpm20PttPtpGuid
+ gPeiAuroraGlacierVbtGuid
+
+[Ppis]
+ gBoardPostMemInitStartGuid
+ gBoardPostMemInitDoneGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gSeCfTPMPolicyPpiGuid
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/PlatformInfoHob.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/PlatformInfoHob.c new file mode 100644 index 0000000000..592e29af26 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/PlatformInfoHob.c @@ -0,0 +1,58 @@ +/** @file
+ This file does Multiplatform initialization.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitMiscs.h"
+
+/**
+ Returns the Platform Info of the platform from the HOB.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PlatformInfoHob Pointer to the PLATFORM_INFO_HOB Pointer
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND PlatformInfoHob data doesn't exist, use default instead.
+
+**/
+EFI_STATUS
+AuroraGetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ )
+{
+ EFI_PEI_HOB_POINTERS GuidHob;
+
+ //
+ // Find the PlatformInfo HOB
+ //
+ GuidHob.Raw = GetHobList ();
+ if (GuidHob.Raw == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {
+ *PlatformInfoHob = GET_GUID_HOB_DATA (GuidHob.Guid);
+ }
+
+ //
+ // PlatformInfo PEIM should provide this HOB data, if not ASSERT and return error.
+ //
+ ASSERT_EFI_ERROR (*PlatformInfoHob != NULL);
+ if (!(*PlatformInfoHob)) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.c new file mode 100644 index 0000000000..36419ec230 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.c @@ -0,0 +1,288 @@ +/** @file
+ This file does TypeC initialization.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "TypeC.h"
+
+static MUX_PROGRAMMING_TABLE mAuroraMuxTable[] = {
+ // Address Register Data String
+ //====================================================================================
+ {A_GENERAL, R_FIRMWARE_VERSION, MUX_TABLE_NULL, "Firmware Version Number"},
+ {A_STATUS, R_CC_STATUS_1, MUX_TABLE_NULL, "CC_Status_1"},
+ {A_STATUS, R_CC_STATUS_2, MUX_TABLE_NULL, "CC_Status_2"},
+ {A_STATUS, R_CC_STATUS_3, MUX_TABLE_NULL, "CC_Status_3"},
+ {A_STATUS, R_MUX_HPD_ASSERT, MUX_TABLE_NULL, "MUX_In_HPD_Assertion"},
+ {A_STATUS, R_MUX_STATUS, MUX_TABLE_NULL, "MUX Status"},
+ {A_STATUS, R_MUX_DP_TRAINING, MUX_TABLE_NULL, "MUX_DP_Training_Disable"},
+ {A_STATUS, R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, "MUX_DP_AUX_Interception_Disable"},
+ {A_STATUS, R_MUX_DP_EQ_CONFIG, MUX_TABLE_NULL, "MUX_DP_EQ_Configuration"},
+ {A_STATUS, R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, "MUX_DP_Output_Configuration"}
+};
+
+VOID
+PrintChar (
+ IN UINTN DebugMask,
+ IN UINTN Count,
+ IN CHAR16 *Char
+)
+{
+ UINTN Index;
+
+ for (Index = 0; Index < Count; Index++) {
+ DEBUG ((DebugMask, "%s", Char));
+ }
+}
+
+#define DIVIDING_LINE "+----------------------------------------------------+------------------+\n"
+
+VOID
+DumpParagraph (
+ IN UINTN DebugMask,
+ IN VOID *Ptr,
+ IN UINTN Count
+ )
+{
+ CHAR8 AsciiBuffer[17];
+ UINT8 *Data;
+ UINTN Index;
+ UINTN Paragraphs;
+ UINTN PlaceHolder;
+ UINTN PlaceHolders;
+
+ //
+ // Use a different pointer so that the one passed in doesn't change
+ //
+ Data = (UINT8 *) Ptr;
+ //
+ // Calcualte the number of paragraphs
+ //
+ Paragraphs = Count / 16;
+ if ((Paragraphs * 16) < Count) {
+ Paragraphs++;
+ }
+ //
+ // Calculate the number of columns
+ //
+ PlaceHolder = Paragraphs;
+ PlaceHolders = 0;
+ while (PlaceHolder > 0) {
+ PlaceHolders++;
+ PlaceHolder >>= 4;
+ }
+
+ //
+ // Dump the buffer
+ //
+ if (Count > 0 ) {
+ //
+ // Print header
+ //
+ PrintChar (DebugMask, PlaceHolders + 5, L" ");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ PrintChar (DebugMask, PlaceHolders + 5, L" ");
+ DEBUG ((DebugMask, "| x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF | String |\n"));
+ DEBUG ((DebugMask, " +"));
+ PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ //
+ // Print data
+ //
+ for (Index = 0; Index < (Paragraphs * 16); Index++) {
+ //
+ // Print divider
+ //
+ if (Index % 0x10 == 0x00) {
+ if ((Index > 0) && ((Index / 0x10) % 0x04 == 0x00) && (Paragraphs > 6)) {
+ DEBUG ((DebugMask, " +"));
+ PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ }
+ DEBUG ((DebugMask, " | %0*xx | ", PlaceHolders, (Index / 0x10)));
+ }
+ //
+ // Print the data or a filler
+ //
+ if (Index < Count) {
+ DEBUG ((DebugMask, "%02x ", Data[Index]));
+ if ((Data[Index] < 32) || (Data[Index] > 126)) {
+ //
+ // Not printable
+ //
+ AsciiBuffer[(Index % 0x10)] = '.';
+ } else {
+ //
+ // Printable
+ //
+ AsciiBuffer[(Index % 0x10)] = Data[Index];
+ }
+ } else {
+ DEBUG ((DebugMask, " "));
+ AsciiBuffer[(Index % 0x10)] = ' ';
+ }
+ //
+ // Print break or line end if needed
+ //
+ if (Index % 0x10 == 0x0F) {
+ AsciiBuffer[16] = 0x00;
+ DEBUG ((DebugMask, "| %a |\n", AsciiBuffer));
+ } else if (Index % 0x04 == 0x03) {
+ DEBUG ((DebugMask, " "));
+ }
+ }
+ //
+ // Print footer
+ //
+ DEBUG ((DebugMask, " +"));
+ PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ }
+}
+
+EFI_STATUS
+EFIAPI
+ReadMux (
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ OUT UINT8 *Data
+ )
+{
+ UINT8 RetryCount;
+ EFI_STATUS Status;
+
+ RetryCount = MUX_RETRY_COUNT;
+ do {
+ *Data = 0x00;
+ Status = ByteReadI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
+ } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+WriteMux (
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ OUT UINT8 *Data
+ )
+{
+ UINT8 RetryCount;
+ EFI_STATUS Status;
+
+ RetryCount = MUX_RETRY_COUNT;
+ do {
+ Status = ByteWriteI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
+ } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
+
+ return Status;
+}
+
+VOID
+DumpMux (
+ VOID
+ )
+{
+ UINT8 Data[256];
+ UINT16 Offset;
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 SlaveAddress;
+ EFI_STATUS Status;
+
+ //
+ // Loop thru device and dump it all
+ //
+ DEBUG ((DEBUG_INFO, "\n%a(#%d) - Dump the PS8750 I2C data\n", __FUNCTION__, __LINE__));
+ for (SlaveAddress = 0x08; SlaveAddress <= 0x0E; SlaveAddress++) {
+ for (Offset = 0x00; Offset <= 0xFF; Offset++) {
+ Status = ReadMux (SlaveAddress, (UINT8) Offset, &Data[Offset]);
+ if (EFI_ERROR (Status)) Data[Offset] = 0xFF;
+ }
+ DEBUG ((DEBUG_INFO, "\nSlaveAddress = 0x%02x\n", (SlaveAddress << 1)));
+ DumpParagraph (DEBUG_INFO, Data, 256);
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ padConfg0.padCnf0 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - GPIO_199 (DDI1 HPD) Rx = %d RxInv = %d\n\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+}
+
+EFI_STATUS
+EFIAPI
+SetupTypecMuxAux (
+ VOID
+ )
+{
+ UINT8 Data8;
+ UINTN index;
+ MUX_DATA_TABLE MuxData;
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 *Ptr;
+ EFI_STATUS Status;
+
+ //
+ // Read/write MUX info
+ //
+ Ptr = (UINT8 *) &MuxData;
+ for (index = 0; index < (sizeof (mAuroraMuxTable) / sizeof (mAuroraMuxTable[0])); index++) {
+ Status = ReadMux (mAuroraMuxTable[index].Address, mAuroraMuxTable[index].Register, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mAuroraMuxTable[index].String, (mAuroraMuxTable[index].Address << 1), mAuroraMuxTable[index].Register, Data8, Status));
+ Ptr[index] = Data8;
+ if ((mAuroraMuxTable[index].Data != MUX_TABLE_NULL) && (!EFI_ERROR (Status))) {
+ Data8 = (UINT8) (mAuroraMuxTable[index].Data & 0x00FF);
+ Status = WriteMux (mAuroraMuxTable[index].Address, mAuroraMuxTable[index].Register, &Data8);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a(#%d) - ERROR: ByteWriteI2C returned %r for %a = 0x%02x\n", __FUNCTION__, __LINE__, Status, mAuroraMuxTable[index].String, Data8));
+ } else {
+ Status = ReadMux (mAuroraMuxTable[index].Address, mAuroraMuxTable[index].Register, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mAuroraMuxTable[index].String, (mAuroraMuxTable[index].Address << 1), mAuroraMuxTable[index].Register, Data8, Status));
+ Ptr[index] = Data8;
+ }
+ }
+ }
+
+ //
+ // Display HPD
+ //
+ padConfg0.padCnf0 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - GPIO_199 (DDI1 HPD) Rx = %d RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+
+ //
+ // See if we need to assert the HPD on the MUX
+ //
+ if ((MuxData.MuxStatus & BIT7) == BIT7) {
+ //
+ // We are in DP mode
+ //
+ if ((MuxData.HpdAssert & BIT7) != BIT7) {
+ //
+ // We need to assert the MUX HPD
+ //
+ Data8 = MuxData.HpdAssert | BIT7;
+ Status = WriteMux (A_STATUS, R_MUX_HPD_ASSERT, &Data8);
+
+ //
+ // Display HPD
+ //
+ padConfg0.padCnf0 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (NW_GPIO_199 + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%d) - GPIO_199 (DDI1 HPD) Rx = %d RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.h new file mode 100644 index 0000000000..9e9c8a852f --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/TypeC.h @@ -0,0 +1,79 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_TYPEC_LIB_H_
+#define _AURORA_TYPEC_LIB_H_
+
+#include <PiDxe.h>
+#include <FrameworkPei.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/I2CLib.h>
+
+//
+// Parade Tech PS8750 TypeC MUX
+//
+#define PARADE_MUX_I2C_BUS 0x01
+#define A_GENERAL 0x08
+#define R_FIRMWARE_VERSION 0x90
+#define A_STATUS 0x09
+#define R_DP_AUX_SNOOP_BW 0x10
+#define R_DP_AUX_SNOOP_LC 0x11
+#define R_DP_AUX_SNOOP_L0 0x12
+#define R_DP_AUX_SNOOP_L1 0x13
+#define R_DP_AUX_SNOOP_L2 0x14
+#define R_DP_AUX_SNOOP_L3 0x15
+#define R_DP_AUX_SNOOP_D3 0x1E
+#define R_MUX_STATUS 0x80
+#define R_MUX_DP_TRAINING 0x83
+#define R_MUX_DP_AUX_INTERCEPT 0x85
+#define R_MUX_DP_EQ_CONFIG 0x86
+#define R_MUX_DP_OUTPUT_CONFIG 0x87
+#define R_MUX_HPD_ASSERT 0xBC
+#define R_CC_STATUS_1 0xEC
+#define R_CC_STATUS_2 0xED
+#define R_CC_STATUS_3 0xEE
+#define MUX_TABLE_NULL 0xFFFF
+#define MUX_RETRY_COUNT 0x03
+#define MUX_TABLE_STRING_LENGTH 32
+
+typedef struct {
+ UINT8 Address;
+ UINT8 Register;
+ UINT16 Data;
+ CHAR8 String[MUX_TABLE_STRING_LENGTH];
+} MUX_PROGRAMMING_TABLE;
+
+typedef struct {
+ //
+ // These UINT8 elements need to match the MUX_PROGRAMMING_TABLE list so we can use the Index to reference them
+ //
+ UINT8 FirmwareVersion; // Offset 0
+ UINT8 CcStatus1; // Offset 1
+ UINT8 CcStatus2; // Offset 2
+ UINT8 CcStatus3; // Offset 3
+ UINT8 MuxStatus; // Offset 4
+ UINT8 HpdAssert; // Offset 5
+ UINT8 DpTraining; // Offset 6
+ UINT8 DpAuxIntercept; // Offset 7
+ UINT8 DpEqConfig; // Offset 8
+ UINT8 DpOutputConfig; // Offset 9
+} MUX_DATA_TABLE;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c new file mode 100644 index 0000000000..bda774cb2a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c @@ -0,0 +1,183 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInit.h"
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ );
+
+static PEI_BOARD_PRE_MEM_INIT_PPI mAuroraPreMemInitPpiInstance = {
+ AuroraGlacierPreMemInit
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAuroraGlacierPreMemInitPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitPpiGuid,
+ &mAuroraPreMemInitPpiInstance
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAuroraGlacierPreMemInitDonePpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitDoneGuid,
+ NULL
+};
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ )
+{
+ EFI_STATUS Status;
+ VOID *Instance;
+ UINT8 BoardId;
+ UINT8 FabId;
+
+ BoardId = 0;
+ FabId = 0;
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ NULL,
+ &Instance
+ );
+ if (!EFI_ERROR (Status)) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Pre Mem Board Init
+ //
+ Status = AuroraGetBoardId (PeiServices, &BoardId);
+
+ if (BoardId != (UINT8) BOARD_ID_AURORA) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "This is Aurora Glacier board.\n"));
+
+ //
+ //Status = AuroraGetFabId (PeiServices, &FabId);
+ //if (FabId == 1) {
+ // DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB B.\n"));
+ //} else if (FabId == 0) {
+ // DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB A.\n"));
+ //}
+ //
+ FabId = 0;
+
+ PcdSet8 (PcdBoardId, BoardId);
+ PcdSet8 (PcdFabId, FabId);
+
+ //
+ // Set board specific function as dynamic PCD to be called by common platform code
+ //
+ PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mAuroraUpdateFspmUpdPtr);
+ PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mAuroraDramCreatePolicyDefaultsPtr);
+
+ //
+ // Install a flag signalling a board is detected and pre-mem init is done
+ //
+ Status = PeiServicesInstallPpi (&mAuroraGlacierPreMemInitDonePpi);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraGlacierInitConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *Ppi;
+ EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
+ UINTN Instance;
+
+ DEBUG ((EFI_D_INFO, "AuroraGlacier Pre Mem Init Constructor \n"));
+
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Board detection previously done, so this is a re-invocation shadowed in memory.
+ // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM.
+ //
+ //
+ // Reinstall PreMemInit Done PPI
+ //
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mAuroraGlacierPreMemInitDonePpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Reinstall all instances of Pre Mem Init PPIs.
+ // These PPIs are no longer used so it doesn't matter which board's instance is finally installed.
+ // According to PeiServicesReInstallPpi behavior:
+ // The first run of this loop would replace all descrioptors with a singe in-RAM descriptor;
+ // Subsequent runs of this loop will only replace the first (already in-RAM) descriptor.
+ // As long as all descriptors are in ram, we are fine.
+ //
+ Instance = 0;
+ do {
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitPpiGuid,
+ Instance,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (Status == EFI_NOT_FOUND) {
+ break;
+ }
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mAuroraGlacierPreMemInitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Instance++;
+ } while (TRUE);
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n"));
+ Status = PeiServicesInstallPpi (&mAuroraGlacierPreMemInitPpi);
+ return Status;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h new file mode 100644 index 0000000000..1cec6b18ac --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h @@ -0,0 +1,41 @@ +/** @file
+ GPIO setting for CherryView.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_BOARDINIT_H_
+#define _AURORA_BOARDINIT_H_
+
+#include <PiPei.h>
+
+#include <Guid/PlatformInfo_Aplk.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/TimerLib.h>
+
+#include <Ppi/BoardInitSignalling.h>
+
+#include "BoardInitMiscs.h"
+#include "PlatformId.h"
+
+VOID AuroraGpioTest (VOID);
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c new file mode 100644 index 0000000000..64f1bdef59 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c @@ -0,0 +1,332 @@ +/** @file
+ This file does Multiplatform initialization.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitMiscs.h"
+#include "MmrcData.h"
+
+UPDATE_FSPM_UPD_FUNC mAuroraUpdateFspmUpdPtr = AuroraUpdateFspmUpd;
+DRAM_CREATE_POLICY_DEFAULTS_FUNC mAuroraDramCreatePolicyDefaultsPtr = AuroraDramCreatePolicyDefaults;
+
+//
+// Aurora Glacier swizzling
+//
+UINT8 ChSwizzleAurora[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {
+ {9,11,10,12,14,15,8,13,0,3,5,1,2,6,7,4,28,25,27,26,29,30,31,24,17,22,23,18,19,20,21,16}, // Channel 0
+ {0,1,5,4,3,6,7,2,12,13,10,14,15,8,9,11,20,23,22,17,21,19,18,16,26,28,29,24,31,25,30,27}, // Channel 1
+ {13,9,15,8,11,10,12,14,2,3,7,4,1,6,0,5,31,29,26,28,25,24,30,27,21,23,16,18,20,19,17,22}, // Channel 2
+ {3,1,6,7,2,5,4,0,8,9,11,10,12,14,13,15,21,17,18,19,23,22,16,20,29,27,25,30,28,24,31,26} // Channel 3
+};
+
+EFI_STATUS
+EFIAPI
+AuroraUpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
+ DRAM_POLICY_PPI *DramPolicy;
+ EFI_STATUS Status;
+ MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VariableSize;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gDramPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &DramPolicy
+ );
+
+ if (!EFI_ERROR (Status)) {
+ FspUpdRgn->FspmConfig.Package = DramPolicy->Package;
+ FspUpdRgn->FspmConfig.Profile = DramPolicy->Profile;
+ FspUpdRgn->FspmConfig.MemoryDown = DramPolicy->MemoryDown;
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.MemorySizeLimit = DramPolicy->SystemMemorySizeLimit;
+ FspUpdRgn->FspmConfig.DIMM0SPDAddress = DramPolicy->SpdAddress[0];
+ FspUpdRgn->FspmConfig.DIMM1SPDAddress = DramPolicy->SpdAddress[1];
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.HighMemoryMaxValue = DramPolicy->HighMemMaxVal;
+ FspUpdRgn->FspmConfig.LowMemoryMaxValue = DramPolicy->LowMemMaxVal;
+ FspUpdRgn->FspmConfig.DisableFastBoot = DramPolicy->DisableFastBoot;
+ FspUpdRgn->FspmConfig.RmtMode = DramPolicy->RmtMode;
+ FspUpdRgn->FspmConfig.RmtCheckRun = DramPolicy->RmtCheckRun;
+ FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold = DramPolicy->RmtMarginCheckScaleHighThreshold;
+ FspUpdRgn->FspmConfig.MsgLevelMask = DramPolicy->MsgLevelMask;
+
+ FspUpdRgn->FspmConfig.ChannelHashMask = DramPolicy->ChannelHashMask;
+ FspUpdRgn->FspmConfig.SliceHashMask = DramPolicy->SliceHashMask;
+ FspUpdRgn->FspmConfig.ChannelsSlicesEnable = DramPolicy->ChannelsSlicesEnabled;
+ FspUpdRgn->FspmConfig.ScramblerSupport = DramPolicy->ScramblerSupport;
+ FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode;
+ FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled;
+ FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled;
+
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+
+ if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
+ ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
+ MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));
+ MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
+ CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ }
+
+ }
+
+ DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
+ Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (Hob.Raw != NULL);
+ PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);
+
+ DEBUG ((DEBUG_INFO, "**** Aurora - UpdateFspmUpd,BoardId = 0x%02x\n", PlatformInfo->BoardId));
+ if (PlatformInfo->BoardId != BOARD_ID_AURORA) {
+ //
+ // ASSERT false if BoardId isn't Aurora
+ //
+ ASSERT (FALSE);
+ }
+
+ //
+ // Overrides for Aurora Glacier (Micron #MT53B512M32D2NP-062 AIT:C) from Platfrom4 profile
+ //
+ FspUpdRgn->FspmConfig.Package = 0x01;
+ FspUpdRgn->FspmConfig.Profile = 0x0B; // LPDDR4_2400_24_22_22
+ FspUpdRgn->FspmConfig.MemoryDown = 0x01;
+ FspUpdRgn->FspmConfig.DualRankSupportEnable = 0x01;
+
+ FspUpdRgn->FspmConfig.Ch0_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch0_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch0_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch0_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch1_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch1_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch1_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch1_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch2_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch2_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch2_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch2_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch3_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch3_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch3_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch3_Option = 0x03;
+
+ //
+ // Swizzling
+ //
+ if (ChSwizzleAurora != NULL) {
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzleAurora[0], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzleAurora[1], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzleAurora[2], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzleAurora[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ }
+
+ //
+ // Disable NPK based on DciEn
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ if (!EFI_ERROR (Status)) {
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+ if (!EFI_ERROR (Status)) {
+ if (SystemConfiguration.DciEn == 0) {
+ FspUpdRgn->FspmConfig.NpkEn = 0;
+ } else if (SystemConfiguration.DciAutoDetect == 1) {
+ FspUpdRgn->FspmConfig.NpkEn = 3;
+ } else {
+ FspUpdRgn->FspmConfig.NpkEn = 1;
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ DramCreatePolicyDefaults creates the default setting of Dram Policy.
+
+ @param[out] DramPolicyPpi The pointer to get Dram Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraDramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ )
+{
+ DRAM_POLICY_PPI *DramPolicy;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VariableSize;
+ EFI_STATUS Status;
+ DRP_DRAM_POLICY *DrpPtr;
+ UINT8 (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
+ PlatfromDramConf *DramConfig;
+ BOOLEAN ReadSetupVars;
+
+ DEBUG ((EFI_D_INFO, "*** Aurora Glacier DramCreatePolicyDefaults\n"));
+ DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));
+ if (DramPolicy == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ReadSetupVars = FALSE;
+ DrpPtr = NULL;
+ ChSwizlePtr = NULL;
+ DramConfig = NULL;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+#if !(ONLY_USE_SMIP_DRAM_POLICY == 1)
+ Status = EFI_UNSUPPORTED;
+#endif
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n"));
+ ReadSetupVars = TRUE;
+ DramPolicy->ChannelHashMask = SystemConfiguration.ChannelHashMask;
+ DramPolicy->SliceHashMask = SystemConfiguration.SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = SystemConfiguration.ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = SystemConfiguration.ScramblerSupport;
+ DramPolicy->InterleavedMode = SystemConfiguration.InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = SystemConfiguration.MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = SystemConfiguration.DualRankSupportEnabled;
+ }
+
+ DramConfig = &(DramConfigData->PlatformDram4);
+
+ DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData->Platform_override));
+ switch (DramConfigData->Platform_override) {
+ case 0:
+ DramConfig = &(DramConfigData->PlatformDram0);
+ break;
+ case 1:
+ DramConfig = &(DramConfigData->PlatformDram1);
+ break;
+ case 2:
+ DramConfig = &(DramConfigData->PlatformDram2);
+ break;
+ case 3:
+ DramConfig = &(DramConfigData->PlatformDram3);
+ break;
+ case 4:
+ DramConfig = &(DramConfigData->PlatformDram4);
+ break;
+ default:
+ //
+ // Do nothing if the override value does not exist. 0xFF is the
+ // default Platform_override value when no override is selected
+ //
+ break;
+ }
+
+ DramPolicy->Package = DramConfig->Package;
+ DramPolicy->Profile = DramConfig->Profile;
+ DramPolicy->MemoryDown = DramConfig->MemoryDown;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->SystemMemorySizeLimit = DramConfig->MemorySizeLimit;
+ DramPolicy->SpdAddress[0] = DramConfig->SpdAddress0;
+ DramPolicy->SpdAddress[1] = DramConfig->SpdAddress1;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->HighMemMaxVal = DramConfig->HighMemMaxVal;
+ DramPolicy->LowMemMaxVal = DramConfig->LowMemMaxVal;
+ DramPolicy->DisableFastBoot = DramConfig->DisableFastBoot;
+ DramPolicy->RmtMode = DramConfig->RmtMode;
+ DramPolicy->RmtCheckRun = DramConfig->RmtCheckRun;
+ DramPolicy->RmtMarginCheckScaleHighThreshold = DramConfig->RmtMarginCheckScaleHighThreshold;
+
+ DramPolicy->MsgLevelMask = DramConfigData->Message_level_mask;
+ DrpPtr = (DRP_DRAM_POLICY *) (&(DramConfig->Ch0RankEnabled));
+ ChSwizlePtr = (UINT8(*)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzling));
+
+ if (!ReadSetupVars) {
+ DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n"));
+ DramPolicy->ChannelHashMask = DramConfig->ChannelHashMask;
+ DramPolicy->SliceHashMask = DramConfig->SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = DramConfig->ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = DramConfig->ScramblerSupport;
+ DramPolicy->InterleavedMode = DramConfig->InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = DramConfig->MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = DramConfig->DualRankSupportEnabled;
+ }
+
+ //
+ // DRP
+ //
+ if (DrpPtr != NULL) {
+ CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp));
+ }
+
+ //
+ // Swizzling
+ //
+ if (ChSwizlePtr != NULL) {
+ CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));
+ }
+
+ if (ReadSetupVars) {
+ if (SystemConfiguration.Max2G == 0) {
+ DramPolicy->SystemMemorySizeLimit = 0x800;
+ }
+ }
+
+ DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr;
+ DramPolicy->MrcBootDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr;
+
+ *DramPolicyPpi = DramPolicy;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h new file mode 100644 index 0000000000..9c498bfaa2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h @@ -0,0 +1,46 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_MULTIPLATFORM_LIB_H_
+#define _AURORA_MULTIPLATFORM_LIB_H_
+
+#include <BoardFunctionsPei.h>
+#include <Guid/SetupVariable.h>
+#include <Library/MemoryAllocationLib.h>
+
+extern UPDATE_FSPM_UPD_FUNC mAuroraUpdateFspmUpdPtr;
+extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mAuroraDramCreatePolicyDefaultsPtr;
+
+EFI_STATUS
+EFIAPI
+AuroraUpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraDramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf new file mode 100644 index 0000000000..53312b7f01 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf @@ -0,0 +1,58 @@ +## @file
+# Board detected module for Intel(R) Atom(TM) E3900 Processor Series.
+# It will detect the board ID.
+#
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = AuroraGlacierInitPreMem
+ FILE_GUID = 6D2C88A1-78D0-428B-BB8E-47CCA5A3AEEF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = AuroraGlacierInitConstructor
+
+[Sources]
+ BoardInit.c
+ PlatformId.c
+ BoardInitMiscs.c
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+ BroxtonFspPkg/BroxtonFspPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdBoardId
+ gPlatformModuleTokenSpaceGuid.PcdFabId
+ gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc
+ gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc
+ gMinnowModuleTokenSpaceGuid.PcdDefaultFabId ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected ## CONSUMES
+
+[Guids]
+
+[Ppis]
+ gBoardPreMemInitPpiGuid
+ gBoardPreMemInitDoneGuid
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c new file mode 100644 index 0000000000..af1a0da609 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c @@ -0,0 +1,144 @@ +/** @file
+ Implement Platform ID code.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/I2CLib.h>
+#include <Library/GpioLib.h>
+#include <Guid/PlatformInfo.h>
+#include "PlatformId.h"
+
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
+
+EFI_STATUS
+EFIAPI
+AuroraGetBoardId(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "GetBoardId.\n"));
+
+ //
+ // Board_ID0: PMIC_STDBY
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00F0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = 0x1; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID1: PMIC_SDWN_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00D0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Board_ID2: PMIC_RESET_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00C8);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ //
+ // Board_ID3: GP_CAMERASB10
+ //
+
+ CommAndOffset = GetCommOffset (NORTH, 0x01E0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+
+ padConfg0.r.PMode = M0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = GPI; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ padConfg1.r.IOSTerm = EnPu; // Enable pull-up
+ padConfg1.r.Term = P_20K_H; // Set to 20K pull-up
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+ //
+ // Read out Board_ID
+ //
+ *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \
+ (((GpioPadRead (GetCommOffset (NORTH, 0x01E0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));
+
+ DEBUG ((DEBUG_INFO, "BoardId: %02X\n", *BoardId));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+AuroraGetFabId(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FabId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "Aurora GetFabId++\n"));
+
+
+ //
+ // FAB_ID: GPIO_30
+ //
+
+ CommAndOffset = GetCommOffset (NORTH, 0x0F0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+
+ padConfg0.r.PMode = M0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = GPI; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ padConfg1.r.IOSTerm = EnPd; // Enable pull-down
+ padConfg1.r.Term = P_20K_L; // Set to 20K pull-down
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+
+ *FabId = (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1));
+
+ DEBUG ((EFI_D_INFO, "FabId: %02X\n", *FabId));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h new file mode 100644 index 0000000000..f92d5162b0 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h @@ -0,0 +1,71 @@ +/** @file
+ Header file for the Platform ID code.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __AURORA_PLATFORM_ID_H__
+#define __AURORAPLATFORM_ID_H__
+
+//
+// Strap Fw Cfg ID define
+//
+#define IO_EXPANDER_I2C_BUS_NO 0x06
+#define IO_EXPANDER_SLAVE_ADDR 0x22
+#define IO_EXPANDER_INPUT_REG_0 0x00
+#define IO_EXPANDER_INPUT_REG_1 0x01
+#define IO_EXPANDER_INPUT_REG_2 0x02
+
+EFI_STATUS
+EFIAPI
+AuroraGetFwCfgId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FwCfgId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetBoardId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetDockId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *DockId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetOsSelPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *OsSelPss
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetBomIdPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BomIdPss
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/Vbt/VbtBxtMipi.bin b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/Vbt/VbtBxtMipi.bin Binary files differnew file mode 100644 index 0000000000..23b52baea1 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/Vbt/VbtBxtMipi.bin diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/PlatformId.c index 70369248d6..614ed664bb 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/PlatformId.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/PlatformId.c @@ -1,7 +1,7 @@ /** @file
Implement Platform ID code.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -20,6 +20,16 @@ #include <Guid/PlatformInfo.h>
#include "PlatformId.h"
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
EFI_STATUS
EFIAPI
BensonGetBoardId(
diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c index d5fc5185bd..aee2b0c71d 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c @@ -1,7 +1,7 @@ /** @file
Implement Platform ID code.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -20,6 +20,16 @@ #include <Guid/PlatformInfo.h>
#include "PlatformId.h"
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
EFI_STATUS
EFIAPI
LeafHillGetEmbeddedBoardIdFabId(
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c index 5b9da16d55..f4cf51cd67 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c @@ -1,7 +1,7 @@ /** @file
Implement Platform ID code.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -20,6 +20,16 @@ #include <Guid/PlatformInfo.h>
#include "PlatformId.h"
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
EFI_STATUS
EFIAPI
Minnow3GetEmbeddedBoardIdFabId(
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat index 5aa545e50e..d8d664b258 100644 --- a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat @@ -183,6 +183,14 @@ if /i "%~1"=="/BG" ( shift
goto OptLoop
)
+
+if /i "%~1"=="/AG" (
+ set BoardId=AG
+ echo.
+ shift
+ goto OptLoop
+)
+
if /i "%~1"=="/MX" (
set BoardId=MX
echo.
@@ -219,6 +227,8 @@ if /i "%~1" == "%Minnow_RVP%" ( set BOARD_ID=MINNOW3
) else if %BoardId%==BG (
set BOARD_ID=BENSONV
+ ) else if %BoardId%==AG (
+ set BOARD_ID=AURORAV
) else if %BoardId%==MX (
set BOARD_ID=M3MODUL
) else if %BoardId%==LH (
@@ -283,6 +293,10 @@ if %BoardId%==BG ( )
)
+if %BoardId%==AG (
+ echo BOARD_REV = A >> Conf\BiosId.env
+)
+
if %BoardId%==MN (
if %FabId%==B (
echo BOARD_REV = B >> Conf\BiosId.env
@@ -474,6 +488,7 @@ if ErrorLevel 1 goto BldFail if "%BUILD_TYPE%"=="R" set BUILD_TYPE=R
echo Copy BIOS...
+echo BIOS_Name=%BOARD_ID%%BOARD_REV%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%_%VERSION_MINOR%
set BIOS_Name=%BOARD_ID%%BOARD_REV%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%_%VERSION_MINOR%
copy /y/b %BUILD_PATH%\FV\Soc.fd %STITCH_PATH%\%BIOS_Name%.ROM >nul
copy /y %STITCH_PATH%\FlashMap.h %STITCH_PATH%\%BIOS_Name%.map >nul
diff --git a/Platform/BroxtonPlatformPkg/BuildIFWI.bat b/Platform/BroxtonPlatformPkg/BuildIFWI.bat index 274210310a..99b3569c95 100644 --- a/Platform/BroxtonPlatformPkg/BuildIFWI.bat +++ b/Platform/BroxtonPlatformPkg/BuildIFWI.bat @@ -112,6 +112,13 @@ if /i "%~1"=="/BG" ( goto OptLoop ) +if /i "%~1"=="/AG" ( + set BoardId=AG + set Build_Flags=%Build_Flags% /AG + shift + goto OptLoop +) + if /i "%~1"=="/MX" ( set BoardId=MX set Build_Flags=%Build_Flags% /MX diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h index b2fbd0bd27..bebbda4349 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h @@ -1,7 +1,7 @@ /** @file
GUID used for Platform Info Data entries in the HOB list.
- Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -161,11 +161,23 @@ typedef enum { #define BOARD_ID_BXT_KsankaGt_MASK 0x8F
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
+
typedef enum {
+ BOARD_ID_MINNOW_NEXT = 0x03, // Minnow Board Next
BOARD_ID_LFH_CRB = 0x07, // Leaf Hill
BOARD_ID_MINNOW = 0x0F, // Minnow Board
BOARD_ID_BENSON = 0x0C, // Benson Glacier
- BOARD_ID_MINNOW_NEXT = 0x03, // Minnow Board Next
+ BOARD_ID_AURORA = 0x0E, // Aurora Glacier
BOARD_ID_APL_UNKNOWN = 0xFF
} APL_BOARD_ID_LIST;
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h index 0bf9fb6eb7..e721cda959 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h @@ -1,7 +1,7 @@ /** @file
GUID used for Platform Info Data entries in the HOB list.
- Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -147,11 +147,22 @@ typedef struct { UINT8 IgdPAVP; // IGD PAVP data
} EFI_PLATFORM_IGD_DATA;
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
typedef enum {
+ BOARD_ID_MINNOW_NEXT = 0x03, // Minnow Board Next
BOARD_ID_LFH_CRB = 0x07, // Leaf Hill
BOARD_ID_MINNOW = 0x0F, // Minnow Board
- BOARD_ID_MINNOW_NEXT = 0x03, // Minnow Board Next
BOARD_ID_BENSON = 0x0C, // Benson Glacier
+ BOARD_ID_AURORA = 0x0E, // Aurora Glacier
BOARD_ID_APL_UNKNOWN = 0xFF
} APL_BOARD_ID_LIST;
diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat index 207183112d..8ace30f8db 100644 --- a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat +++ b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat @@ -48,6 +48,10 @@ if /i "%~3"=="BG" ( set BoardId=BG
)
+if /i "%~3"=="AG" (
+ set BoardId=AG
+)
+
if /i "%~3"=="MX" (
set BoardId=MX
)
@@ -110,19 +114,6 @@ if not "!BIOS_Name!"=="!BIOS_Name:_R_=!" ( goto Usage
)
-if /i "!Platform_Type!"=="MINN" (
- set Platform_Type=MINN
-) else if /i "!Platform_Type!"=="BENS" (
- set Platform_Type=BENS
-) else if /i "!Platform_Type!"=="M3MO" (
- set Platform_Type=M3MO
-) else if /i "!Platform_Type!"=="LEAF" (
- set Platform_Type=LEAF
-) else (
- echo Error - Unsupported PlatformType: !Platform_Type!
- goto Usage
-)
-
:: rd /s /q %BIOS_Names% >>Stitching.log
pushd %BIOS_Names%
@@ -154,6 +145,14 @@ if %BoardId%==BG ( copy /y /b ..\..\..\Board\BensonGlacier\IFWI\FAB_A\SpiChunk3.bin .
)
copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin
+
+) else if %BoardId%==AG (
+ copy /y /b ..\..\..\Board\AuroraGlacier\IFWI\FAB_A\SpiChunk1.bin .
+ copy /y /b ..\..\..\Board\AuroraGlacier\IFWI\FAB_A\SpiChunk2.bin .
+ copy /y /b ..\..\..\Board\AuroraGlacier\IFWI\FAB_A\SpiChunk3.bin .
+
+ copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin
+
) else if %BoardId%==MN (
if %FabId%==B (
copy /y /b ..\..\..\Board\MinnowBoard3\IFWI\FAB_B\SpiChunk1.bin .
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc index 2bdc3d09d3..8615ebc5c0 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc @@ -1,7 +1,7 @@ ## @file
# Platform Components for IA32 Description.
#
-# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -81,6 +81,7 @@ NULL|$(PLATFORM_NAME)/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
NULL|$(PLATFORM_NAME)/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
NULL|$(PLATFORM_NAME)/Board/BensonGlacier/BoardInitPreMem/BoardInitPreMem.inf
+ NULL|$(PLATFORM_NAME)/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf
NULL|$(PLATFORM_NAME)/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibPreMem.inf
@@ -117,6 +118,7 @@ NULL|$(PLATFORM_NAME)/Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf
NULL|$(PLATFORM_NAME)/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
NULL|$(PLATFORM_NAME)/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+ NULL|$(PLATFORM_NAME)/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
NULL|$(PLATFORM_NAME)/Board/MinnowBoard3Next/BoardInitPostMem/BoardInitPostMem.inf
I2cLibPei|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/I2CLibPei/I2CLibPei.inf
<PcdsPatchableInModule>
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc index d56911a0c0..3135d4dc69 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc @@ -1,7 +1,7 @@ ## @file
# Platform Components Description.
#
-# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -177,6 +177,7 @@ NULL|$(PLATFORM_NAME)/Board/MinnowBoard3/BoardInitDxe/BoardInitDxe.inf
NULL|$(PLATFORM_NAME)/Board/LeafHill/BoardInitDxe/BoardInitDxe.inf
NULL|$(PLATFORM_NAME)/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.inf
+ NULL|$(PLATFORM_NAME)/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf
NULL|$(PLATFORM_NAME)/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf
}
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/BroxtonPlatformPkg/PlatformPkg.dec index f2bb7243ea..aed59fee99 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec @@ -3,7 +3,7 @@ #
# This package provides platform specific modules.
#
-# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -62,6 +62,7 @@ gPeiMinnowBoard3VbtGuid = { 0xE08CA6D5, 0x8D02, 0x43ae, { 0xAB, 0xB1, 0x95, 0x2C, 0xC7, 0x87, 0xC9, 0x33 } }
gPeiBensonGlacierVbtGuid = { 0xbfde308e, 0x2d5a, 0x4ca7, { 0xaa, 0x76, 0x19, 0x93, 0x8a, 0xaa, 0xe4, 0xda } }
gPeiMinnow3NextVbtGuid = { 0x1f9cbb42, 0x107e, 0x46a4, { 0xa2, 0xcb, 0x92, 0xf5, 0x86, 0xf9, 0xfb, 0x31 } }
+ gPeiAuroraGlacierVbtGuid = { 0xaa80b0b1, 0xba1e, 0x4d4f, { 0x83, 0xe0, 0xcc, 0xf4, 0x7a, 0xaa, 0x3c, 0xd8 } }
gPeiLogoGuid = { 0x7BB28B99, 0x61BB, 0x11d5, { 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } }
gPlatformEmmcHs400TuningInfoGuid = { 0xb0ae3e81, 0xc6b0, 0x4d35, { 0xad, 0x51, 0x91, 0x17, 0xe0, 0x65, 0x1e, 0xa3 } }
gEfiTraceHubDebugLibIa32Guid = { 0x23a3e7ba, 0x75d1, 0x4cb9, { 0x9c, 0x8f, 0x56, 0xfa, 0x4e, 0x48, 0xd9, 0x9e } }
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf index c07b65ee54..a037708f70 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -1,7 +1,7 @@ ## @file
# FDF file of Platform.
#
-# Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -271,6 +271,12 @@ SECTION RAW = $(PLATFORM_NAME)/Board/BensonGlacier/Vbt/VbtBxtMipi.bin
SECTION UI = "IntelGopVbt1"
}
+
+ # VBT For Aurora Glacier (File Guid is gPeiAuroraGlacierVbtGuid)
+ FILE FREEFORM = AA80B0B1-BA1E-4D4F-83E0-CCF47AAA3CD8 {
+ SECTION RAW = $(PLATFORM_NAME)/Board/AuroraGlacier/Vbt/VbtBxtMipi.bin
+ SECTION UI = "IntelGopVbt1"
+ }
!endif
INF $(PLATFORM_SI_PACKAGE)/Cpu/SmmAccess/Pei/SmmAccess.inf
|