diff options
| author | Mark Rutland <mark.rutland@arm.com> | 2015-11-19 14:14:25 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-19 14:14:25 +0000 |
| commit | fafb7e9c110eb89d1d1da18a822cae49758b76f6 (patch) | |
| tree | 868a86cd740cc3214399a6117201607b4e8c5feb | |
| parent | 1a6f74d98887377bd5bb61484e54a3ac406f4a5d (diff) | |
| download | edk2-platforms-fafb7e9c110eb89d1d1da18a822cae49758b76f6.tar.xz | |
ArmPkg: correct TTBR1_EL1 settings in TCR_EL1
As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure
it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since
reset.
Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU
may make page table walks via TTBR1_EL1 at any time, potentially using
UNKNOWN values. This can result in a number of potential problems (e.g.
the CPU may load from MMIO registers as part of a page table walk).
Additionally, in the presence of Cortex-A57 erratum #822227, we must
program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value
of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a
hypervisor which makes use of PAR_EL1.
This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above
to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any
CPU capable of running EDK2 must support this granule, and given
TCR_EL1.EPD1, programming the field is not detrimental in the absence of
the erratum.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
| -rw-r--r-- | ArmPkg/Include/Chipset/AArch64Mmu.h | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index 3c3df6d983..f660e65aac 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -108,6 +108,7 @@ #define TCR_PS_256TB (5 << 16)
#define TCR_TG0_4KB (0 << 14)
+#define TCR_TG1_4KB (2 << 30)
#define TCR_IPS_4GB (0ULL << 32)
#define TCR_IPS_64GB (1ULL << 32)
@@ -116,6 +117,7 @@ #define TCR_IPS_16TB (4ULL << 32)
#define TCR_IPS_256TB (5ULL << 32)
+#define TCR_EPD1 (1 << 23)
#define TTBR_ASID_FIELD (48)
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index 377a7858d4..f967a64788 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -628,7 +628,8 @@ ArmConfigureMmu ( return RETURN_UNSUPPORTED;
}
} else if (ArmReadCurrentEL () == AARCH64_EL1) {
- TCR = T0SZ | TCR_TG0_4KB;
+ // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
+ TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
// Set the Physical Address Size using MaxAddress
if (MaxAddress < SIZE_4GB) {
|