diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:51 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:51 +0800 |
| commit | 5c164e151c4047efc32f2bd0d6cad730e635c23c (patch) | |
| tree | f6c3948c9087dec9dd634a3594d62856b9228f33 | |
| parent | ba037b96944c1d1a310867f1c6fb515d96444556 (diff) | |
| download | edk2-platforms-5c164e151c4047efc32f2bd0d6cad730e635c23c.tar.xz | |
PurleySktPkg: Initial version.
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
36 files changed, 6463 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleySktPkg/Iio/Include/Protocol/IioSystem.h b/Silicon/Intel/PurleySktPkg/Iio/Include/Protocol/IioSystem.h new file mode 100644 index 0000000000..b4a2639219 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Iio/Include/Protocol/IioSystem.h @@ -0,0 +1,64 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_SYSTEM_PROTOCOL_H_ +#define _IIO_SYSTEM_PROTOCOL_H_ + +#include <IioPlatformData.h> +#include <IioSetupDefinitions.h> + +// +// IIO System driver Protocol GUID +// +// {DDC3080A-2740-4ec2-9AA5-A0ADEFD6FF9C} +#define EFI_IIO_SYSTEM_GUID \ + { \ + 0xDDC3080A, 0x2740, 0x4ec2, 0x9A, 0xA5, 0xA0, 0xAD, 0xEF, 0xD6, 0xFF, 0x9C \ + } + +extern EFI_GUID gEfiIioSystemProtocolGuid; + +typedef struct _PORT_DESCRIPTOR{ + UINT8 Bus; + UINT8 Device; + UINT8 Function; +}PORT_DESCRIPTOR; + +typedef struct _PORT_ATTRIB{ + UINT8 PortWidth; + UINT8 PortSpeed; +}PORT_ATTRIB; + +EFI_STATUS +IioGetCpuUplinkPort ( + UINT8 IioIndex, + PORT_DESCRIPTOR *PortDescriptor, //Bus, Device, function + BOOLEAN *PortStatus, //TRUE if enabled else disabled + PORT_ATTRIB *PortAttrib //width and speed +); + +typedef +EFI_STATUS +(EFIAPI *IIO_GET_CPU_UPLINK_PORT) ( + IN UINT8 IioIndex, + OUT PORT_DESCRIPTOR *PortDescriptor, + OUT BOOLEAN *PortStatus, + OUT PORT_ATTRIB *PortAttrib +); + +typedef struct _EFI_IIO_SYSTEM_PROTOCOL{ + IIO_GLOBALS *IioGlobalData; + IIO_GET_CPU_UPLINK_PORT IioGetCpuUplinkPort; +} EFI_IIO_SYSTEM_PROTOCOL; + +#endif //_IIO_SYSTEM_PROTOCOL_H_
\ No newline at end of file diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..5102ba7a8f --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MEMORY_CONFIG_DATA_GUID_H_ +#define _MEMORY_CONFIG_DATA_GUID_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }\ + } + +extern EFI_GUID gEfiMemoryConfigDataGuid; +extern CHAR16 EfiMemoryConfigVariable[]; + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..b5cc47bbf5 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h @@ -0,0 +1,75 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include "PartialMirrorGuid.h" + +// {F8870015-6994-4b98-95A2-BD56DA91C07F} +#define EFI_MEMORY_MAP_GUID \ + { \ + 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ + } + +extern EFI_GUID gEfiMemoryMapGuid; +extern CHAR16 EfiMemoryMapVariable[]; + +// +// System Memory Map HOB information +// + +#pragma pack(1) + +struct SystemMemoryMapElement { + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 ImcInterBitmap; // IMC interleave bitmap for this DRAM rule - ONLY IN NUMA + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks +}; + +struct SystemMemoryMapHob { + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - Lockstep + UINT8 DimmType; + UINT16 DramType; + UINT8 DdrVoltage; + UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set + UINT8 SADNum; + UINT8 XMPProfilesSup; + UINT8 cpuType; + UINT8 cpuStepping; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled + UINT8 RasModesSupported; //RAS modes that are supported by current memory population. + UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map Elements + UINT8 maxIMC; + UINT8 maxCh; + struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; +}; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h b/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h new file mode 100644 index 0000000000..d8e770fba6 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PARTIAL_MIRROR_GUID_H_ +#define _PARTIAL_MIRROR_GUID_H_ + +#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } + +#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent" +#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest" +#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VARIABLE_DATA) +#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS) +#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1 +#define MIRROR_STATUS_SUCCESS 0 +#define MIRROR_STATUS_MIRROR_INCAPABLE 1 +#define MIRROR_STATUS_VERSION_MISMATCH 2 +#define MIRROR_STATUS_INVALID_REQUEST 3 +#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4 +#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5 + +extern EFI_GUID gAddressBasedMirrorGuid; + +#pragma pack(1) + +typedef struct { +// +// MirroredAmountAbove4GB is the amount of available memory above 4GB that needs to be mirrored +// measured in basis point (hundredths of percent e.g. 12% = 1275). +// In a multi-socket system, platform is required to distribute the mirrored memory ranges such that the +// amount mirrored is approximately proportional to the amount of memory on each NUMA node. E.g. on +// a two node machine with 64GB on node 0 and 32GB on node 1, a request for 12GB of mirrored memory +// should be allocated with 8GB of mirror on node 0 and 4GB on node 1. +// +// For example, if the total memory in the system is 48GB and 12GB of memory above the 4GB addresses needs to be mirrored then the amount would be: +// Total Memory = 48 GB +// Total Memory above 4GB = 44 GB +// Percentage = 8/44 * 100 = 18.18% = 1818 basis points +// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB on socket 1, +// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to maintain the requested 18%. +// This ensures that OS has an adequate amount of mirrored memory on each NUMA domain. +// + UINT8 MirrorVersion; + BOOLEAN MirrorMemoryBelow4GB; + UINT16 MirroredAmountAbove4GB; + UINT8 MirrorStatus; +} ADDRESS_RANGE_MIRROR_VARIABLE_DATA; + +typedef struct { + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType; + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType; +} RASMEMORYINFO; +#pragma pack() + + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h new file mode 100644 index 0000000000..26b708279f --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h @@ -0,0 +1,49 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
+#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
+
+#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \
+ { \
+ 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \
+ }
+
+/**
+* GUID specific data structure of HOB for reserving SMRAM regions.
+*
+* Inconsistent with specification here:
+* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to EFI_SMRAM_HOB_DESCRIPTOR_BLOCK.
+* This inconsistency is kept in code in order for backward compatibility.
+**/
+typedef struct {
+ ///
+ /// Designates the number of possible regions in the system
+ /// that can be usable for SMRAM.
+ ///
+ /// Inconsistent with specification here:
+ /// In Framework SMM CIS 0.91 specification, it defines the field type as UINTN.
+ /// However, HOBs are supposed to be CPU neutral, so UINT32 should be used instead.
+ ///
+ UINT32 NumberOfSmmReservedRegions;
+ ///
+ /// Used throughout this protocol to describe the candidate
+ /// regions for SMRAM that are supported by this platform.
+ ///
+ EFI_SMRAM_DESCRIPTOR Descriptor[1];
+} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
+
+extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid;
+
+#endif
+
diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h new file mode 100644 index 0000000000..b2472e14bd --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__ +#define __SOCKET_COMMONRC_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketCommonRcVariableGuid; +#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig" + +#pragma pack(1) +typedef struct { + // + // Common Section of RC + // + UINT32 MmiohBase; + UINT16 MmiohSize; + UINT8 MmcfgBase; + UINT8 MmcfgSize; + UINT8 IsocEn; + UINT8 NumaEn; + UINT8 MirrorMode; + UINT8 LockStep; + UINT8 CpuStepping; + UINT8 SystemRasType; + UINT32 FpgaPresentBitMap; +} SOCKET_COMMONRC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h new file mode 100644 index 0000000000..2a47851f17 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h @@ -0,0 +1,269 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_IIO_CONFIG_DATA_H__ +#define __SOCKET_IIO_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketIioVariableGuid; +#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig" + +#pragma pack(1) + + +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTHPCAP[MAX_TOTAL_PORTS]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_TOTAL_PORTS]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; // On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Cb3DcaEn[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_TOTAL_PORTS]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; + // Hide IOAPIC Device 5, Function 4 + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 Pci64BitResourceAllocation; + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + + /** + ================================================================================================== + ================================== PCIe SSD Related Setup Options ========================== + ================================================================================================== + **/ + + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PCIe Global Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + UINT8 MctpEn; //On Setup + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 RtoEnable; + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} SOCKET_IIO_CONFIGURATION; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h new file mode 100644 index 0000000000..ef0b5a300a --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h @@ -0,0 +1,221 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__ +#define __SOCKET_MEMORY_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" +#include <MemDefaults.h> + +extern EFI_GUID gEfiSocketMemoryVariableGuid; +#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig" + +#pragma pack(1) +typedef struct { + UINT8 RtoMaxNodeInterleave; + UINT8 MemoryHotPlugBase; + UINT8 MemoryHotPlugLen; + UINT8 Srat; + UINT8 SratMemoryHotPlug; + UINT8 SratCpuHotPlug; + UINT8 PagePolicy; + UINT8 PatrolScrub; + UINT8 PatrolScrubDuration; + UINT8 PatrolScrubAddrMode; + UINT8 partialmirror; + UINT8 partialmirrorsad0; + UINT8 PartialMirrorUefi; + UINT16 PartialMirrorUefiPercent; + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array of sizes of different partial mirrors + UINT8 DemandScrubMode; + UINT8 SddcPlusOneEn; + UINT16 spareErrTh; + UINT8 DieSparing; + UINT8 DieSparingAggressivenessLevel; + UINT8 ADDDCEn; + UINT8 AdddcErrInjEn; + UINT8 leakyBktLo; + UINT8 leakyBktHi; + UINT8 DutyCycleTraining; + UINT8 refreshMode; + UINT8 dllResetTestLoops; + UINT8 DdrMemoryType; + UINT8 HwMemTest; + UINT16 MemTestLoops; + UINT8 EccSupport; + UINT8 SocketInterleaveBelow4GB; + UINT8 RtoDimmManagement; + UINT8 RtoPartitionDDRTDimm; + UINT8 RtoPartitionRatio[16]; //[MAX_SOCKET * MAX_IMC] = [8] + UINT8 volMemMode; + UINT8 RtoPerMemMode; + UINT8 memInterleaveGran1LM; + UINT8 RtoMemInterleaveGranPMemUMA; + UINT8 RtoCfgMask2LM; + UINT8 ImcInterleaving; + UINT8 ChannelInterleaving; + UINT8 RankInterleaving; + UINT8 CkeProgramming; + UINT8 SrefProgramming; + UINT8 PkgcSrefEn; + UINT8 CkeIdleTimer; + UINT8 ApdEn; + UINT8 PpdEn; + UINT8 DdrtCkeEn; + UINT8 OppSrefEn; + UINT8 DdrtSrefEn; + UINT8 MdllOffEn; + UINT8 CkMode; + UINT8 MemTestOnFastBoot; + UINT8 AttemptFastBoot; + UINT8 AttemptFastBootCold; + UINT8 bdatEn; + UINT8 ScrambleEnDDRT; + UINT8 ScrambleEn; // for ddr4 + UINT8 allowCorrectableError; + UINT16 ScrambleSeedLow; + UINT16 ScrambleSeedHigh; + UINT8 CustomRefreshRateEn; + UINT8 CustomRefreshRate; + UINT8 mcBgfThreshold; + UINT8 readVrefCenter; + UINT8 wrVrefCenter; + UINT8 haltOnMemErr; + UINT8 thermalthrottlingsupport; + UINT8 thermalmemtrip; + UINT8 DimmTempStatValue; + UINT8 XMPProfilesSup; + UINT8 XMPMode; + UINT8 tCAS; + UINT8 tRP; + UINT8 tRCD; + UINT8 tRAS; + UINT8 tWR; + UINT16 tRFC; + UINT8 tRRD; + UINT8 tRTP; + UINT8 tWTR; + UINT8 tFAW; + UINT8 tCWL; + UINT8 tRC; + UINT8 commandTiming; + UINT16 tREFI; + UINT8 DdrFreqLimit; + UINT16 Vdd; + UINT8 lrdimmModuleDelay; + UINT32 rmtPatternLength; + UINT32 rmtPatternLengthExt; + UINT8 check_pm_sts; + UINT8 check_platform_detect; + UINT8 MemPwrSave; + UINT8 ElectricalThrottlingMode; + UINT8 MultiThreaded; + UINT8 promoteMrcWarnings; + UINT8 promoteWarnings; + UINT8 oppReadInWmm; + UINT16 normOppInterval; + UINT8 sck0ch0; + UINT8 sck0ch1; + UINT8 sck0ch2; + UINT8 sck0ch3; + UINT8 sck0ch4; + UINT8 sck0ch5; + UINT8 sck1ch0; + UINT8 sck1ch1; + UINT8 sck1ch2; + UINT8 sck1ch3; + UINT8 sck1ch4; + UINT8 sck1ch5; + UINT8 sck2ch0; + UINT8 sck2ch1; + UINT8 sck2ch2; + UINT8 sck2ch3; + UINT8 sck2ch4; + UINT8 sck2ch5; + UINT8 sck3ch0; + UINT8 sck3ch1; + UINT8 sck3ch2; + UINT8 sck3ch3; + UINT8 sck3ch4; + UINT8 sck3ch5; + UINT8 mdllSden; + UINT8 memhotSupport; + UINT8 MemhotOutputOnlyOpt; + UINT8 ADREn; + UINT8 RankMargin; + UINT8 EnableBacksideRMT; + UINT8 EnableBacksideCMDRMT; + UINT8 Reserved_0; + UINT8 rankMaskEn; + UINT8 RankSparing; + UINT8 multiSparingRanks; + UINT8 caParity; + UINT8 dimmIsolation; + UINT8 smbSpeed; + UINT8 EnforcePOR; + UINT8 pda; + UINT8 turnaroundOpt; + UINT8 oneRankTimingMode; + UINT8 eyeDiagram; + + UINT8 DramRaplInit; + UINT8 BwLimitTfOvrd; + UINT8 perbitmargin; + UINT8 DramRaplExtendedRange; + UINT8 CmsEnableDramPm; + UINT8 logParsing; + UINT8 WritePreamble; + UINT8 ReadPreamble; + UINT8 WrCRC; + + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + UINT8 Reserved_4; + UINT8 Reserved_5; + UINT8 Reserved_6; + UINT8 Reserved_7; + UINT8 Reserved_8; + + UINT8 RmtOnColdFastBoot; + UINT8 mrcRepeatTest; + UINT8 RtoLowMemChannel; + UINT8 RtoHighAddressStartBitPosition; + UINT8 staggerref; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT8 Blockgnt2cmd1cyc; + UINT8 Disddrtopprd; + UINT8 setTDPDIMMPower; + UINT8 setSecureEraseAllDIMMs; + UINT8 setSecureEraseSktCh[48]; + // + // PPR related + // + UINT8 pprType; + UINT8 pprErrInjTest; + // CR QoS Configuration Profiles + UINT8 crQosConfig; + UINT8 Reserved_11; + UINT8 Reserved_12; + UINT8 Reserved_13; + UINT8 imcBclk; + UINT8 spdCrcCheck; +} SOCKET_MEMORY_CONFIGURATION; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h new file mode 100644 index 0000000000..3f51792d8b --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__ +#define __SOCKET_MP_LINK_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketMpLinkVariableGuid; +#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig" + +#pragma pack(1) +typedef struct { + // SKXTODO: rename to Kti when removing HSX code + UINT8 QpiSetupNvVariableStartTag; // This must be the very first one of the whole KTI Setup NV variable! + + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + // + // KTI host structure inputs + // + UINT8 BusRatio[MAX_SOCKET]; + UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 MmioP2pDis; // 1 - Disable; 0 - Enable + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default + + // + // Phy/Link Layer Options + // + UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow Speed; 1- Full Speed + UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable + UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode + UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S Topology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default) + UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (default), 0x00 - min + UINT8 SncEn; // 0 - Disable (default), 1 - Enable + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default) + UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 IrqThreshold; // KTI IRQ Threshold setting + UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - Enable; 2 - AUTO (default) + UINT8 StaleAtoSOptEn; // HA A to S directory optimization + UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - Enable, 0 - Disable + +#define CSICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##KtiLinkVnaOverride; + + UINT8 KtiCpuPerPortStartTag; + CSICPUPRTVARIABLE(UINT8 Cpu0P0) + CSICPUPRTVARIABLE(UINT8 Cpu0P1) + CSICPUPRTVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTVARIABLE(UINT8 Cpu1P0) + CSICPUPRTVARIABLE(UINT8 Cpu1P1) + CSICPUPRTVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTVARIABLE(UINT8 Cpu2P0) + CSICPUPRTVARIABLE(UINT8 Cpu2P1) + CSICPUPRTVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTVARIABLE(UINT8 Cpu3P0) + CSICPUPRTVARIABLE(UINT8 Cpu3P1) + CSICPUPRTVARIABLE(UINT8 Cpu3P2) +#endif +#if (MAX_SOCKET > 4) + CSICPUPRTVARIABLE(UINT8 Cpu4P0) + CSICPUPRTVARIABLE(UINT8 Cpu4P1) + CSICPUPRTVARIABLE(UINT8 Cpu4P2) +#endif +#if (MAX_SOCKET > 5) + CSICPUPRTVARIABLE(UINT8 Cpu5P0) + CSICPUPRTVARIABLE(UINT8 Cpu5P1) + CSICPUPRTVARIABLE(UINT8 Cpu5P2) +#endif +#if (MAX_SOCKET > 6) + CSICPUPRTVARIABLE(UINT8 Cpu6P0) + CSICPUPRTVARIABLE(UINT8 Cpu6P1) + CSICPUPRTVARIABLE(UINT8 Cpu6P2) +#endif +#if (MAX_SOCKET > 7) + CSICPUPRTVARIABLE(UINT8 Cpu7P0) + CSICPUPRTVARIABLE(UINT8 Cpu7P1) + CSICPUPRTVARIABLE(UINT8 Cpu7P2) +#endif + + UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the whole KTI Setup NV variable +} SOCKET_MP_LINK_CONFIGURATION; + +#pragma pack() + +#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__ + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h new file mode 100644 index 0000000000..7aa2ad7fc8 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ +#define __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPciResourceDataGuid; +#define SOCKET_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SocketPciResourceConfigData" + +#pragma pack(1) +typedef struct { + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + UINT16 PciSocketIoBase[MAX_SOCKET]; + UINT16 PciSocketIoLimit[MAX_SOCKET]; + UINT32 PciSocketMmiolBase[MAX_SOCKET]; + UINT32 PciSocketMmiolLimit[MAX_SOCKET]; + UINT64 PciSocketMmiohBase[MAX_SOCKET]; + UINT64 PciSocketMmiohLimit[MAX_SOCKET]; + UINT16 PciResourceIoBase[TOTAL_IIO_STACKS]; + UINT16 PciResourceIoLimit[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Base[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Limit[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Base[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Limit[TOTAL_IIO_STACKS]; +} SOCKET_PCI_RESOURCE_CONFIGURATION_DATA; +#pragma pack() + +#endif // __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h new file mode 100644 index 0000000000..a6724ef0c3 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h @@ -0,0 +1,224 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ +#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPowermanagementVarGuid; +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementConfig" + +#define NUM_CST_LAT_MSR 3 + +#pragma pack(1) + +typedef struct { + UINT8 LOT26UnusedVrPowerDownEnable; + UINT8 WFRWAEnable; + UINT8 UFSDisable; // Allow Mailbox Command to PCU_MISC_CONFIG Bit[28] + UINT8 ProcessorEistEnable; // EIST or GV3 setup option + + // Config TDP + UINT8 ConfigTDP; + UINT8 ConfigTDPLevel; + + // Individual controls for ACPI sleep states + // ** These can be overridden by AcpiSleepState because these knobs are not available to CRB ** + // + UINT8 AcpiS3Enable; + UINT8 AcpiS4Enable; + + // + //HWPM starts + // + UINT8 ProcessorHWPMEnable; + UINT8 ProcessorAutonomousCstateEnable; + UINT8 ProcessorHWPMInterrupt; + UINT8 ProcessorEPPEnable; + UINT8 ProcessorEppProfile; + UINT8 ProcessorAPSrocketing; + UINT8 ProcessorScalability; + UINT8 ProcessorPPOBudget; + UINT8 ProcessorOutofBandAlternateEPB; + // + //HWPM ends + // + UINT8 PStateDomain; // P State Domain + UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select option + UINT8 ProcessorSinglePCTLEn; // PCPS - SINGLE_PCTL select option + UINT8 ProcessorSPD; // PCPS - SPD select option + UINT8 BootPState; // Boot Performance Mode + + // + // Processor Control + // + UINT8 TurboMode; + UINT8 EnableXe; + + //OverClocking + UINT8 OverclockingLock; + + UINT8 TurboRatioLimitRatio[8]; + UINT8 TurboRatioLimitCores[8]; + + UINT8 C2C3TT; + UINT8 DynamicL1; // Enabling Dynamic L1 + UINT8 ProcessorCcxEnable; // Enabling CPU C states of processor + UINT8 PackageCState; // Package C-State Limit + UINT8 C3Enable; // Enable/Disable NHM C3(ACPI C2) report to OS + UINT8 C6Enable; // Enable/Disable NHM C6(ACPI C3) report to OS + UINT8 ProcessorC1eEnable; // Enabling C1E state of processor + UINT8 OSCx; // ACPI C States + + UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Valid + UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Multiplier + UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Value + + UINT8 TStateEnable; // T states enable? + UINT8 OnDieThermalThrottling; // Throtte ratio + UINT8 ProchotLock; + UINT8 EnableProcHot; + UINT8 EnableThermalMonitor; + UINT8 ProchotResponse; + UINT8 EETurboDisable; + UINT8 SapmctlValCtl; + UINT8 PwrPerfTuning; + UINT8 AltEngPerfBIAS; + UINT8 PwrPerfSwitch; + UINT8 WorkLdConfig; + UINT16 EngAvgTimeWdw1; + + UINT8 ProchotResponseRatio; + UINT8 TCCActivationOffset; + + UINT8 P0TtlTimeLow1; + UINT8 P0TtlTimeHigh1; + + UINT8 PkgCLatNeg; + UINT8 LTRSwInput; + UINT8 SAPMControl; + UINT8 CurrentConfig; + UINT8 PriPlnCurCfgValCtl; + UINT8 Psi3Code; + UINT16 CurrentLimit; + + UINT8 Psi3Thshld; + UINT8 Psi2Code; + UINT8 Psi2Thshld; + UINT8 Psi1Code; + UINT8 Psi1Thshld; + + //Power Management Setup options + UINT8 PkgCstEntryValCtl; + + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + UINT8 PpcccLock; + + UINT8 SnpLatVld; + UINT8 SnpLatOvrd; + UINT8 SnpLatMult; + UINT16 SnpLatVal; + UINT16 NonSnpLatVld; + UINT8 NonSnpLatOvrd; + UINT8 NonSnpLatMult; + UINT16 NonSnpLatVal; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + UINT8 EepLOverride; + UINT8 EepLOverrideEn; + UINT8 ITurboOvrdEn; + UINT8 CstDemotOvrdEN; + UINT8 TrboDemotOvrdEn; + UINT8 UncrPerfPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 ImcApmOvrdEn; // unused + UINT8 IomApmOvrdEn; + UINT8 QpiApmOvrdEn; + UINT8 PerfPLmtThshld; + + // SAPMCTL_CFG (CSR 1:30:1:0xB0) + UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0] + UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1] + UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2] + UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3] + UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4] + UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16] + UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17] + UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18] + UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22] + UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23] + UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6] + UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7] + UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19] + UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20] + UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30]; + UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31]; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) + UINT8 PerfPLimitClip; + UINT8 PerfPLimitEn; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >= HSX C stepping + UINT8 PerfPlimitDifferential; + UINT8 PerfPLimitClipC; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90) + UINT8 Kti0In[MAX_SOCKET]; + UINT8 Kti1In[MAX_SOCKET]; + UINT8 Kti2In[MAX_SOCKET]; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c) + UINT8 PcieIio0In[MAX_SOCKET]; + UINT8 PcieIio1In[MAX_SOCKET]; + UINT8 PcieIio2In[MAX_SOCKET]; + UINT8 PcieIio3In[MAX_SOCKET]; + UINT8 PcieIio4In[MAX_SOCKET]; + UINT8 PcieIio5In[MAX_SOCKET]; + + UINT8 FastRaplDutyCycle; + UINT8 TurboPowerLimitLock; + UINT8 TurboPowerLimitCsrLock; + UINT8 PowerLimit1En; + UINT32 PowerLimit1Power; + UINT8 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT8 PowerLimit2En; + UINT32 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2Time; + + UINT8 UsePmaxOffsetTable; + UINT8 PmaxSign; + UINT8 PmaxOffset; + + //XTU 3.0 + + UINT8 MaxEfficiencyRatio[MAX_SOCKET]; + UINT8 MaxNonTurboRatio[MAX_SOCKET]; + + // use SPT workarounds - B2P cmd MISC_WORKAROUND_ENABLE + UINT8 SPTWorkaround; + UINT8 VccSAandVccIOdisable; + +} SOCKET_POWERMANAGEMENT_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h new file mode 100644 index 0000000000..37c614bca2 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h @@ -0,0 +1,115 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ +#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketProcessorCoreVarGuid; +#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfig" + +#pragma pack(1) + +typedef struct { + + UINT8 CpuidMaxValue; + UINT8 ExecuteDisableBit; + + UINT8 PchTraceHubEn; // PCH TRACE HUB + UINT8 C1AutoDemotion; // C1 Auto Demotion + UINT8 C3AutoDemotion; // C3 Auto Demotion + UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL] + UINT8 ProcessorLtsxEnable; // Enabling TXT + UINT8 ProcessorVmxEnable; // Enabling VMX + UINT8 ProcessorSmxEnable; // Enabling SMX + UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control + UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR + UINT8 ThreeStrikeTimer; // Disable 3strike timer + UINT8 FastStringEnable; // Fast String + UINT8 MachineCheckEnable; // Machine Check + UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch + UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch + UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher + UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher + UINT8 DCUModeSelection; // DCU Mode Selection + UINT8 ProcessorX2apic; // Enable Processor XAPIC + UINT8 ForceX2ApicIds; // Force to use > 8bit ApicId + UINT8 BspSelection; // Select BSP + UINT8 IedSize; // IED size + UINT8 IedTraceSize; // IED trace size + UINT8 TsegSize; // TSEG size + UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio + UINT8 CheckCpuBist; // check and disable BIST faile core or ignore + UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Core Ratio Multiplier + UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode Processor Core Ratio Multiplier Enable + UINT8 MTRRDefTypeUncachable; // For changing UC to WB + UINT8 ForcePhysicalModeEnable; // Force physical destionation mode + UINT8 LlcPrefetchEnable; // LLC Prefetch + UINT8 ProcessorVirtualWireMode; + + UINT8 AesEnable; + UINT8 PpinControl; // PPIN Control MSR + UINT8 LockChipset; // Lock Chipset + UINT8 SkipStopPbet; // Skip StopPbet + + UINT8 BiosAcmErrorReset; // Disable LT-SX and reset system when BIOS ACM error occurs + UINT8 AcmType; // 0x80 = debug signed ACM; 0x40 = NPW production signed ACM; 0x00 = PW production signed ACM + + UINT32 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket + // IOT/OCLA configs +#ifndef OCLA_TOR_ENTRY_MAX + #define OCLA_TOR_ENTRY_MIN 0 + #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Isoch on/off + #define OCLA_TOR_ENTRY_DEFAULT 1 + #define OCLA_WAY_MIN 0 + #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 can be reserved for OCLA + #define OCLA_WAY_DEFAULT 1 +#endif + UINT8 IotEn[MAX_SOCKET]; + UINT8 OclaMaxTorEntry[MAX_SOCKET]; + UINT8 OclaMinWay[MAX_SOCKET]; + UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask. - Only Bits[22:0] are used + UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:0] bitmask. - Only Bits[10:0] are used + UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:16] bitmask. - Only Bits[10:0] are used + UINT32 QlruCfgMask_Lo; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Lower 32-bit + UINT32 QlruCfgMask_Hi; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Higher 32-bit + + + UINT8 PCIeDownStreamPECIWrite; + +// +// Targeted Smi Support +// + UINT8 TargetedSmi; +// +// eSMM Save State Mode +// + UINT8 eSmmSaveState; + + UINT8 PeciInTrustControlBit; //On Setup + + UINT8 Poison; + UINT8 Viral; + UINT8 EVMode; + UINT8 SmbusErrorRecovery; +} SOCKET_PROCESSORCORE_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h new file mode 100644 index 0000000000..ac6c4dc0aa --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_CONFIG_DATA_H__ +#define __SOCKET_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" +#include <Guid/SocketIioVariable.h> +#include <Guid/SocketCommonRcVariable.h> +#include <Guid/SocketPowermanagementVariable.h> +#include <Guid/SocketProcessorCoreVariable.h> +#include <Guid/SocketMpLinkVariable.h> +#include <Guid/SocketMemoryVariable.h> + +#pragma pack(1) + +typedef struct { + SOCKET_IIO_CONFIGURATION IioConfig; + SOCKET_COMMONRC_CONFIGURATION CommonRcConfig; + SOCKET_MP_LINK_CONFIGURATION CsiConfig; + SOCKET_MEMORY_CONFIGURATION MemoryConfig; + SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration; +} SOCKET_CONFIGURATION; + + + +#pragma pack() +#endif + diff --git a/Silicon/Intel/PurleySktPkg/Include/Library/CpuPpmLib.h b/Silicon/Intel/PurleySktPkg/Include/Library/CpuPpmLib.h new file mode 100644 index 0000000000..22f312f80b --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Library/CpuPpmLib.h @@ -0,0 +1,706 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + + +#include <PiDxe.h> +#include <Protocol/CpuCsrAccess.h> +#include <Library/TimerLib.h> +#include "SysHost.h" +#include "UncoreCommonIncludes.h" + +#define NUM_CST_LAT_MSR 3 + +// +// Value definition for CpuPCPSCtrl +// +#define PCD_CPU_PCPS_SINGLEPCTL 0x00000004 +#define PCD_CPU_PCPS_SPD 0x00000008 +#define PCD_CPU_PCPS_PSTATEDOMAIN 0x00000010 + +// Bits configuration for PcdAdvPwrMgtFlags +#define PCD_CPU_PKG_CST_ENTRY_VAL_CTL 0x00000001 +#define PCD_CPU_SAPM_CTL_VAL_CTL 0x00000002 +#define PCD_CPU_SKIP_PKG_CST_ENTRY 0x00000004 +#define PCD_CPU_SW_LTR_OVRD_CTL 0x00000008 +#define PCD_CPU_PRI_PLN_CURR_CFG_CTL 0x00000010 +#define PCD_CPU_CURRENT_CONFIG 0x00000020 +#define PCU_CPU_EFFICIENT_BOOT 0x00000040 +#define CPU_MSR_LOCK 0x00000080 +#define MPLL_OFF_ENA_AUTO 0x00000100 +#define DYNAMIC_L1_DISABLE 0x00000200 +#define SPT_PCH_WORKAROUND 0x00000400 +#define TURBO_LIMIT_CSR_LOCK 0x00000800 +#define VCCSA_VCCIO_DISABLE 0x00001000 + + +// PCU_CR_PMAX_CONFIG bit definition +#define PCU_CR_PMAX_CFG_OFFSET_SHIFT 0 +#define PCU_CR_PMAX_CFG_LOCK_SHIFT 31 +#define PCU_CR_PMAX_CFG_OFFSET (0x1f << PCU_CR_PMAX_CFG_OFFSET_SHIFT) // Bits 4:0 +#define USER_PMAX_USE_OFFSET_TABLE BIT5 +#define USER_PMAX_NEGATIVE_BIT BIT4 +#define USER_PMAX_VALUE_BIT_MASK 0x0F // Bits 3:0 +#define PCU_CR_PMAX_CFG_LOCK (0x1 << PCU_CR_PMAX_CFG_LOCK_SHIFT) // Bit 31 + +// DYNAMIC_PERF_POWER_CTL bit definition +#define EEP_L_OVERRIDE_SHIFT 26 // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE_SHIFT 25 // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE_SHIFT 24 // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE_SHIFT 23 // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT 22 // Bit 22 +#define UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT 20 // Bit 20 +#define EET_OVERRIDE_ENABLE_SHIFT 18 // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT 15 // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE_SHIFT 10 // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE_SHIFT 5 // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE_SHIFT 0 // Bit 0 +#define EEP_L_OVERRIDE (0xf << EEP_L_OVERRIDE_SHIFT) // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE (1 << EEP_L_OVERRIDE_ENABLE_SHIFT) // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE (1 << I_TURBO_OVERRIDE_ENABLE_SHIFT) // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE (1 << CST_DEMOTION_OVERRIDE_ENABLE_SHIFT) // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE (1 << TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT) // Bit 22 +#define UNOCRE_PERF_PLIMIT_OVERRIDE_ENABLE (1 << UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT) // Bit 20 +#define EET_OVERRIDE_ENABLE (1 << EET_OVERRIDE_ENABLE_SHIFT) // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE (1 << IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT) // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE (1 << IMC_APM_OVERRIDE_ENABLE_SHIFT) // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE (1 << IOM_APM_OVERRIDE_ENABLE_SHIFT) // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE (1 << QPI_APM_OVERRIDE_ENABLE_SHIFT) // Bit 0 +#define DYNAMIC_PERF_POWER_CTL_MASK (0x3C000000 + UNOCRE_PERF_PLIMIT_OVERRIDE_ENABLE + EET_OVERRIDE_ENABLE + IO_BW_PLIMIT_OVERRIDE_ENABLE + IMC_APM_OVERRIDE_ENABLE + IOM_APM_OVERRIDE_ENABLE + QPI_APM_OVERRIDE_ENABLE) + +// CSR_PCIE_ILTR_OVRD (CSR 1:10:1:78) +// SW_LTR_OVRD (MSR 0xa02) -- not used +//CSR_PCIE_ILTR_OVRD bit definition +#define SNOOP_LATENCY_VLD_SHIFT 31 // Bits 31 +#define FORCE_SNOOP_OVRD_SHIFT 30 // Bits 30 +#define SNOOP_LATENCY_MUL_SHIFT 26 // Bits 28:26 +#define SNOOP_LATENCY_Value_SHIFT 16 // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_SHIFT 15 // Bits 15 +#define FORCE_NON_SNOOP_OVRD_SHIFT 14 // Bits 14 +#define NON_SNOOP_LATENCY_MUL_SHIFT 10 // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_SHIFT 0 // Bits 9:0 +#define SNOOP_LATENCY_VLD_MASK (1 << SNOOP_LATENCY_VLD_SHIFT) // Bits 31 +#define FORCE_SNOOP_OVRD_MASK (1 << FORCE_SNOOP_OVRD_SHIFT) // Bits 30 +#define SNOOP_LATENCY_MUL_MASK (0x7 << SNOOP_LATENCY_MUL_SHIFT) // Bits 28:26 +#define SNOOP_LATENCY_Value_MASK (0x3FF << SNOOP_LATENCY_Value_SHIFT) // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_MASK (1 << NON_SNOOP_LATENCY_VLD_SHIFT) // Bits 15 +#define FORCE_NON_SNOOP_OVRD_MASK (1 << FORCE_NON_SNOOP_OVRD_SHIFT) // Bits 14 +#define NON_SNOOP_LATENCY_MUL_MASK (0x7 << NON_SNOOP_LATENCY_MUL_SHIFT) // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_MASK (0x3FF << NON_SNOOP_LATENCY_Value_SHIFT) // Bits 9:0 +#define SW_LTR_OVRD_CTL_MASK (SNOOP_LATENCY_VLD_MASK + FORCE_SNOOP_OVRD_MASK + SNOOP_LATENCY_MUL_MASK + SNOOP_LATENCY_Value_MASK + \ + NON_SNOOP_LATENCY_VLD_MASK + FORCE_NON_SNOOP_OVRD_MASK + NON_SNOOP_LATENCY_MUL_MASK + NON_SNOOP_LATENCY_Value_MASK) + +//CSR_PKG_CST_ENTRY_CRITERIA_MASK bit definition +#define DRAM_IN_SR_SHIFT 28 +#define QPI_2_IN_L1_SHIFT 27 +#define QPI_1_IN_L1_SHIFT 26 +#define QPI_0_IN_L1_SHIFT 25 +#define QPI_2_IN_L0S_SHIFT 24 +#define QPI_1_IN_L0S_SHIFT 23 +#define QPI_0_IN_L0S_SHIFT 22 +#define PCIE_IN_L1_SHIFT 11 +#define PCIE_IN_L0S_SHIFT 0 +#define DRAM_IN_SR (1 << DRAM_IN_SR_SHIFT) +#define QPI_2_IN_L1 (1 << QPI_2_IN_L1_SHIFT) +#define QPI_1_IN_L1 (1 << QPI_1_IN_L1_SHIFT) +#define QPI_0_IN_L1 (1 << QPI_0_IN_L1_SHIFT) +#define QPI_2_IN_L0S (1 << QPI_2_IN_L0S_SHIFT) +#define QPI_1_IN_L0S (1 << QPI_1_IN_L0S_SHIFT) +#define QPI_0_IN_L0S (1 << QPI_0_IN_L0S_SHIFT) +#define PCIE_IN_L1 (1 << PCIE_IN_L1_SHIFT) +#define PCIE_IN_L0S (1 << PCIE_IN_L0S_SHIFT) +#define PCIE_IN_LX_MASK 0x7FF // Bit[10:0] +#define MASK_PCIE_BITS 0xFFC00000 // clear bits 21:0 +// For SKX +#define KTI_2_IN_L1_SHIFT 2 +#define KTI_1_IN_L1_SHIFT 1 +#define KTI_0_IN_L1_SHIFT 0 +#define KTI_2_IN_L1 (1 << KTI_2_IN_L1_SHIFT) +#define KTI_1_IN_L1 (1 << KTI_1_IN_L1_SHIFT) +#define KTI_0_IN_L1 (1 << KTI_0_IN_L1_SHIFT) +#define MASK_PCIE_IN_L1_BITS 0xFF000000 // clear bits 23:0 +#define SET_KTI_INPKGCENTRY (KTI_0_IN_L1 + KTI_1_IN_L1 + KTI_2_IN_L1) +#define SET_PCIE_INPKGCENTRY 0xFFFFFF // set bits 23:0 +#define SET_PCIEx_MASK 0xF +#define SET_DMI_MASK 0x1 + + +// CSR Perf PLIMIT bit definition for HSX <= B Stepping +#define I_TURBO_WAIT_PERIOD_SHIFT 19 // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD_SHIFT 13 // Bits 18:13 +#define I_TURBO_EN_SHIFT 12 // Bit 12 +#define PERF_P_LIMIT_CLIP_SHIFT 6 // Bits 11:6 +#define DISABLE_PERF_P_INPUT_SHIFT 5 // Bit 5 +#define RESOLUTION_MODE_SHIFT 1 // Bits 2:1 +#define REPERF_P_LIMIT_EN_SHIFT 0 // Bit 0 +#define I_TURBO_WAIT_PERIOD (0x1fff << I_TURBO_WAIT_PERIOD_SHIFT) // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD (0x3f << PERF_P_LIMIT_THRESHOLD_SHIFT) // Bits 18:13 +#define I_TURBO_EN (1 << I_TURBO_EN_SHIFT) // Bit 12 +#define PERF_P_LIMIT_CLIP (0x3f << PERF_P_LIMIT_CLIP_SHIFT) // Bits 11:6 +#define DISABLE_PERF_P_INPUT (1 << DISABLE_PERF_P_INPUT_SHIFT) // Bit 5 +#define RESOLUTION_MODE (3 << RESOLUTION_MODE_SHIFT) // Bits 2:1 +#define REPERF_P_LIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIFT) // Bit 0 + +// CSR Perf PLIMIT bit definition for HSX >= C Stepping & SKX +#define PERF_PLIMIT_DIFFERENTIAL_SHIFT 15 // Bits 17:15 +#define PERF_PLIMIT_DIFFERENTIAL (7 << PERF_PLIMIT_DIFFERENTIAL_SHIFT) // Bits 17:15 +#define PERF_PLIMIT_CLIP_SHIFT 7 // Bits 11:7 +#define PERF_PLIMIT_CLIP (0x1f << PERF_P_LIMIT_CLIP_SHIFT) // Bits 11:7 +#define PERF_PLIMIT_THRESHOLD_SHIFT 1 // Bits 5:1 +#define PERF_PLIMIT_THRESHOLD (0x1f << PERF_P_LIMIT_THRESHOLD_SHIFT) // Bits 5:1 +#define REPERF_PLIMIT_EN_SHIFT 0 // Bit 0 +#define REPERF_PLIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIFT) // Bit 0 +#define PERF_P_LIMIT_CTRL_MASK (PERF_PLIMIT_THRESHOLD + PERF_PLIMIT_CLIP + PERF_PLIMIT_DIFFERENTIAL + REPERF_PLIMIT_EN) + +//CSR SAPMCTLbit definition +#define SAPMCTL_LOCK_SHIFT 31 // Bit 31 for IVT/HSX/SKX +#define SETVID_DECAY_DISABLE_SHIFT 30 // Bit 30 for IVT/KSX/SKX +#define QPI_L0S_PLL_SEN_ENABLE_SHIFT 29 // Bit 29//Only for IVT +#define QPI_L0_PLL_SEN_ENABLE_SHIFT 28 // Bit 28//Only for IVT +#define IIO_L0S_PLL_SEN_ENABLE_SHIFT 27 // Bit 27//Only for IVT +#define IIO_L0_PLL_SEN_ENABLE_SHIFT 26 // Bit 26//Only for IVT +#define QPI2_L0S_PLL_SEN_ENABLE_SHIFT 25 // Bit 25//Only for IVT +#define QPI2_L0_PLL_SEN_ENABLE_SHIFT 24 // Bit 24//Only for IVT +#define QPI2_PKGC_CLOCK_GATE_DISABLE_SHIFT 18 // Bit 18//IVT/HSX +#define QPI01_PKGC_CLOCK_GATE_DISABLE_SHIFT 17 // Bit 17//IVT/HSX +#define IIO_PKGC_CLOCK_GATE_DISABLE_SHIFT 16 // Bit 16//IVT/HSX +#define MDLL_ON_DE_SHIFT 15 // Bit 15//IVT/HSX +#define MPLL_ON_DE_SHIFT 14 // Bit 14//IVT/HSX +#define SACG_MPLL_SHIFT 13 // Bit 13//Only for IVT +#define NSWAKE_SREXIT_SHIFT 12 // Bit 12//IVT/HSX +#define SACG_SREXIT_SHIFT 11 // Bit 11//Only for IVT +#define MDLL_OFF_SEN_SHIFT 10 // Bit 10//Only for IVT +#define MPLL_OFF_SEN_SHIFT 9 // Bit 9//Only for IVT +#define SACG_SEN_SHIFT 8 // Bit 8//Only for IVT +#define FORCE_PPLL_OFF_SHIFT 4 // Bit 4 //IVT/HSX +#define QPLL_OFF_ENA_SHIFT 3 // Bit 3//Only for IVT +#define PPLL_OFF_ENA_SHIFT 2 // Bit 2//IVT/HSX +#define MPLL_OFF_ENA_SHIFT 1 // Bit 1//IVT/HSX +#define SACG_ENA_SHIFT 0 // Bit 0//Only for IVT +#define SAPMCTL_LOCK (1 << SAPMCTL_LOCK_SHIFT) // Bit 31 +#define SETVID_DECAY_DISABLE (1 << SETVID_DECAY_DISABLE_SHIFT) // Bit 30 +#define QPI_L0S_PLL_SEN_ENABLE (1 << QPI_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 29 +#define QPI_L0_PLL_SEN_ENABLE (1 << QPI_L0_PLL_SEN_ENABLE_SHIFT) // Bit 28 +#define IIO_L0S_PLL_SEN_ENABLE (1 << IIO_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 27 +#define IIO_L0_PLL_SEN_ENABLE (1 << IIO_L0_PLL_SEN_ENABLE_SHIFT) // Bit 26 +#define QPI2_L0S_PLL_SEN_ENABLE (1 << QPI2_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 25 +#define QPI2_L0_PLL_SEN_ENABLE (1 << QPI2_L0_PLL_SEN_ENABLE_SHIFT) // Bit 24 +#define QPI2_PKGC_CLOCK_GATE_DISABLE (1 << QPI2_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 18//IVT +#define QPI01_PKGC_CLOCK_GATE_DISABLE (1 << QPI01_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 17//IVT +#define IIO_PKGC_CLOCK_GATE_DISABLE (1 << IIO_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 16//IVT +#define MDLL_ON_DE (1 << MDLL_ON_DE_SHIFT) // Bit 15 +#define MPLL_ON_DE (1 << MPLL_ON_DE_SHIFT) // Bit 14 +#define SACG_MPLL (1 << SACG_MPLL_SHIFT) // Bit 13 +#define NSWAKE_SREXIT (1 << NSWAKE_SREXIT_SHIFT) // Bit 12 +#define SACG_SREXIT (1 << SACG_SREXIT_SHIFT) // Bit 11 +#define MDLL_OFF_SEN (1 << MDLL_OFF_SEN_SHIFT) // Bit 10 +#define MPLL_OFF_SEN (1 << MPLL_OFF_SEN_SHIFT) // Bit 9 +#define SACG_SEN (1 << SACG_SEN_SHIFT) // Bit 8 +#define FORCE_PPLL_OFF (1 << FORCE_PPLL_OFF_SHIFT) // Bit 4 //IVT +#define QPLL_OFF_ENA (1 << QPLL_OFF_ENA_SHIFT) // Bit 3 +#define PPLL_OFF_ENA (1 << PPLL_OFF_ENA_SHIFT) // Bit 2 +#define MPLL_OFF_ENA (1 << MPLL_OFF_ENA_SHIFT) // Bit 1 +#define SACG_ENA (1 << SACG_ENA_SHIFT) // Bit 0 + +//CSR SAPMCTLbit definition for SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 27 // Bit 27, SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 26 // Bit 26, SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 25 // Bit 25, SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 24 // Bit 24, SKX +#define MEM_PLL_OFF_EN_SHIFT 22 // Bit 22,23, SKX +#define KTI_PLL_OFF_EN_SHIFT 19 // Bit 19,20, SKX +#define IIO_PLL_OFF_EN_SHIFT 16 // Bit 16,17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE_SHIFT 7 // Bit 7, SKX +#define MC0_PKGC_CLK_GATE_DISABLE_SHIFT 6 // Bit 6, SKX +#define KTI23_PKGC_CLK_GATE_DISABLE_SHIFT 4 // Bit 4, SKX +#define KTI01_PKGC_CLK_GATE_DISABLE_SHIFT 3 // Bit 3, SKX +#define IIO012_PKGC_CLK_GATE_DISABLE_SHIFT 0 // Bit 0,1,2, SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 27, SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 26, SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 25, SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 24, SKX +#define MEM_PLL_OFF_EN (3 << MEM_PLL_OFF_EN_SHIFT) // Bit 22,23, SKX +#define KTI_PLL_OFF_EN (3 << KTI_PLL_OFF_EN_SHIFT) // Bit 19,20, SKX +#define IIO_PLL_OFF_EN (7 << IIO_PLL_OFF_EN_SHIFT) // Bit 16,17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE (1 << MC1_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 7, SKX +#define MC0_PKGC_CLK_GATE_DISABLE (1 << MC0_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 6, SKX +#define KTI23_PKGC_CLK_GATE_DISABLE (1 << KTI23_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 4, SKX +#define KTI01_PKGC_CLK_GATE_DISABLE (1 << KTI01_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 3, SKX +#define IIO012_PKGC_CLK_GATE_DISABLE (7 << IIO012_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 0,1,2, SKX +#define SAPMCTL_MASK (IIO012_PKGC_CLK_GATE_DISABLE + KTI01_PKGC_CLK_GATE_DISABLE + KTI23_PKGC_CLK_GATE_DISABLE + MC0_PKGC_CLK_GATE_DISABLE \ + + MC1_PKGC_CLK_GATE_DISABLE + IIO_PLL_OFF_EN + KTI_PLL_OFF_EN + MEM_PLL_OFF_EN + SETVID_DECAY_DISABLE + SAPMCTL_LOCK \ + + MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE + MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE) + +//Config TDP +#define CONFIG_TDP_LEVEL (3 << CONFIG_TDP_LEVEL_SHIFT) +#define CONFIG_TDP_LEVEL_SHIFT 1 // Bit [2:1] +#define CONFIG_TDP_SHIFT 0 // Bit 0 + +// MSR 0x1FC +#define MSR_POWER_CTL 0x1FC +#define PCH_NEG_DISABLE (1 << 30) +#define PCH_NEG_DISABLE_SHIFT 30 +#define LTR_SW_DISABLE (1 << 29) //LTR_IIO_DISABLE +#define LTR_SW_DISABLE_SHIFT 29 +#define PROCHOT_LOCK (1 << 27) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_RESPONSE (1 << 26) +#define PROCHOT_RESPONSE_SHIFT 26 +#define PWR_PERF_TUNING_CFG_MODE (1 << 25) +#define PWR_PERF_TUNING_CFG_MODE_SHIFT 25 +#define PWR_PERF_TUNING_ENABLE_DYN_SWITCHING (1 << 24) +#define PWR_PERF_TUNING_ENABLE_DYN_SHIFT 24 +#define PWR_PERF_TUNING_DISABLE_EEP_CTRL (1 << 23) +#define PWR_PERF_TUNING_DISABLE_EEP_SHIFT 23 +#define PWR_PERF_TUNING_DISABLE_SAPM_CTRL (1 << 22) +#define PWR_PERF_TUNING_DISABLE_SAPM_SHIFT 22 +#define DIS_PROCHOT_OUT (1 << 21) +#define DIS_PROCHOT_OUT_SHIFT 21 +#define EE_TURBO_DISABLE (1 << 19) +#define EE_TURBO_DISABLE_SHIFT 19 +#define ENERGY_EFFICIENT_PSTATE_ENABLE (1 << 18) +#define ENERGY_EFFICIENT_PSTATE_ENABLE_SHIFT 18 +#define PHOLD_SR_DISABLE (1 << 17) +#define PHOLD_SR_DISABLE_SHIFT 17 +#define PHOLD_CST_PREVENTION_INIT (1 << 16) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 16 +#define FAST_BRK_INT_EN (1 << 4) +#define FAST_BRK_INT_EN_SHIFT 4 +#define FAST_BRK_SNP_EN (1 << 3) +#define FAST_BRK_SNP_EN_SHIFT 3 +#define SAPM_IMC_C2_POLICY_EN (1 << 2) +#define SAPM_IMC_C2_POLICY_SHIFT 2 +#define C1E_ENABLE (1 << 1) +#define C1E_ENABLE_SHIFT 1 +#define ENABLE_BIDIR_PROCHOT_EN (1 << 0) +#define ENABLE_BIDIR_PROCHOT_EN_SHIFT 0 +#define POWER_CTL_MASK (PCH_NEG_DISABLE + LTR_SW_DISABLE + PWR_PERF_TUNING_CFG_MODE + \ + PWR_PERF_TUNING_ENABLE_DYN_SWITCHING + PWR_PERF_TUNING_DISABLE_EEP_CTRL + \ + PWR_PERF_TUNING_DISABLE_SAPM_CTRL + DIS_PROCHOT_OUT + ENABLE_BIDIR_PROCHOT_EN + C1E_ENABLE) + +// PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 +#define PSI3_CODE_SHIFT 27 // (Bits 61:59 actully) we operate on a 32 bit register +#define PSI3_THSHLD_SHIFT 20 // (Bits 58:52 actully) we operate on a 32 bit register +#define PSI2_CODE_SHIFT 17 // (Bits 51:49 actully) we operate on a 32 bit register +#define PSI2_THSHLD_SHIFT 10 // (Bits 48:42 actully) we operate on a 32 bit register +#define PSI1_CODE_SHIFT 7 // (Bits 41:39 actully) we operate on a 32 bit register +#define PSI1_THSHLD_SHIFT 0 // (Bits 38:32 actully) we operate on a 32 bit register +#define PPCCC_LOCK_SHIFT 31 +#define CURRENT_LIMIT_SHIFT 0 +#define PSI3_CODE (0x7 << PSI3_CODE_SHIFT) // (Bits 61:59 actully) we operate on a 32 bit register +#define PSI3_THSHLD (0x7f << PSI3_THSHLD_SHIFT) // (Bits 58:52 actully) we operate on a 32 bit register +#define PSI2_CODE (0x7 << PSI2_CODE_SHIFT) // (Bits 51:49 actully) we operate on a 32 bit register +#define PSI2_THSHLD (0x7f << PSI2_THSHLD_SHIFT) // (Bits 48:42 actully) we operate on a 32 bit register +#define PSI1_CODE (0x7 << PSI1_CODE_SHIFT) // (Bits 41:39 actully) we operate on a 32 bit register +#define PSI1_THSHLD (0x7f << PSI1_THSHLD_SHIFT) // (Bits 38:32 actully) we operate on a 32 bit register +#define PPCCC_LOCK (1 << PPCCC_LOCK_SHIFT) +#define CURRENT_LIMIT (0x1fff << CURRENT_LIMIT_SHIFT) + +#define B_PCPS_DISABLE (1 << 25) // Bit 25 + +// MSR_C_STATE_LATENCY_CONTROL_0 0x60a, 60b, 60c +#define VALID_SHIFT 15 +#define MULTIPLIER_SHIFT 10 +#define VALUE_SHIFT 0 + +// MSR_TURBO_POWER_LIMIT 0x610 +// CSR_TURBO_POWER_LIMIT +#define POWER_LIMIT_ENABLE_SHIFT 15 +#define POWER_LIMIT_ENABLE (1 << POWER_LIMIT_ENABLE_SHIFT) // Used as Bit 15 and Bit 47 +#define PKG_CLMP_LIM_SHIFT 16 +#define PKG_CLMP_LIM (1 << PKG_CLMP_LIM_SHIFT) // used as Bit 16 and Bit48 +#define POWER_LIMIT_MASK (0x7FFF) // Bits 14:0 and 46:32 +#define POWER_LIMIT_1_TIME_SHIFT 17 +#define POWER_LIMIT_1_TIME_MASK (0xFE0000) // Bits 23:17 +#define POWER_LIMIT_LOCK_SHIFT 31 +#define POWER_LIMIT_LOCK (1 << POWER_LIMIT_LOCK_SHIFT) // Bit 63 + +// MSR_ENERGY_PERF_BIAS_CONFIG 0xA01 +#define AVG_TIME_Window (0xff << AVG_TIME_Window_SHIFT) // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW (0x3f << PO_TOTAL_TIME_THSHLD_LOW_SHIFT) // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH (0x3f << PO_TOTAL_TIME_THSHLD_HIGH_SHIFT) // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS (0xf << ALT_ENERGY_PERF_BIAS_SHIFT) // Bits 6:3 +#define WORKLD_CONFIG (0x7 << WORKLD_CONFIG_SHIFT) // Bits 2:0 +#define AVG_TIME_Window_SHIFT 24 // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW_SHIFT 18 // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH_SHIFT 12 // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS_SHIFT 3 // Bits 6:3 +#define WORKLD_CONFIG_SHIFT 0 // Bits 2:0 +#define ENERGY_PERF_BIAS_CTRL_MASK (AVG_TIME_Window + PO_TOTAL_TIME_THSHLD_LOW + PO_TOTAL_TIME_THSHLD_HIGH + WORKLD_CONFIG + ALT_ENERGY_PERF_BIAS) + +// +// Cross over Mode +// +#define XOVER_MODE_2TO2 1 +#define XOVER_MODE_1TO1 2 + +// HWPM features +#define HWP_ENABLE 0x01 +#define ACC_ENABLE 0x02 + +// SPT workarounds +#define SPT_WA_ENABLE 0x03 + +// ratio in Performance Control MSR (MSR_IA32_PERF_CTL) +#define B_IA32_PERF_CTRLP_STATE_TARGET (0x7F << 8) + +#pragma pack(1) + +/************************** + Processor Power Management Data structs +***************************/ + +typedef struct _PPM_FROM_PPMINFO_HOB { + UINT8 NumberOfSockets; // # of populated sockets in the system + UINT8 SocketNumber; // which socket + UINT32 SocketPresentBitMap; // bitmap for present CPU packages/nodes + UINT8 IioBusNumber[MAX_SOCKET]; // Bus# for IIO, indexed by CPU Socket/Node ID + UINT8 UncoreBusNumber[MAX_SOCKET]; // Bus# for Uncore, indexed by CPU Socket/Node ID + UINT32 mmCfgBase; + UINT8 DdrXoverMode; // DDR 2.2 Mode + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + UINT32 OutPciePerLinkL1En[MAX_SOCKET]; // output PCIe (IIO) link enabled status for PM + UINT8 KtiPortCnt; // num KTI ports residing on each Socket + UINT8 ProcessorPowerUnit[MAX_SOCKET]; // + UINT8 ProcessorTimeUnit[MAX_SOCKET]; // + UINT16 PackageTdp[MAX_SOCKET]; // Package TDP + UINT32 CapId4; //CapId CSR value + UINT32 CpuType; // CpuType + UINT8 CpuStepping; // CpuStepping + UINT32 mNumOfBitShift; // # Bits to shift right APIC ID to get next level APIC ID + UINTN NumberOfProcessors; // number of active threads + BOOLEAN EistCap; // EIST Capability + UINT8 Bios_Reset_Cpl_Phase; + UINT8 HwpmSupport; //HWPM support flag +}PPM_FROM_PPMINFO_HOB; + +typedef struct { + UINT8 Major; // Major Vesion + UINT8 Minor; // Minor Vesion + UINT8 Rev; // Release Version + UINT8 Build; // +} PPM_VERSION; + +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; + +typedef struct { + BOOLEAN C1e; + + UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET]; + UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET]; + MSR_REGISTER LatencyCtrl[NUM_CST_LAT_MSR]; + +} CSTATE_STRUCT; + +typedef struct { + + BOOLEAN EistEnabled; // option to enable GV3 + +} PSTATE_STRUCT; + +typedef struct { + BOOLEAN Enable; + UINT32 Voltage; + UINT16 RatioLimit[MAX_CORE]; +} XE_STRUCT; + +typedef struct { + UINT8 RatioLimitRatio[8]; + UINT8 RatioLimitRatioMask[8]; + UINT8 RatioLimitCores[8]; + UINT8 RatioLimitCoresMask[8]; +} TURBO_RATIO_LIMIT_RATIO_CORES; + +typedef struct { + UINT8 HWPMEnable; + UINT8 HWPMNative; + UINT8 HWPMOOB; + UINT8 HWPMInterrupt; + UINT8 AutoCState; + UINT8 EPPEnable; + UINT8 EPPProfile; + UINT8 APSrocketing; + UINT8 Scalability; + UINT8 PPOTarget; + UINT8 PPOBudget; + UINT8 OutofBandAlternateEPB; +} HWPM_STRUCT; + +typedef struct { + + UINT8 ConfigTDP; + UINT8 PcpsCtrl; + UINT8 FastRaplDutyCycle; + UINT8 FuseTjMaxOffset; + + UINT8 OverclockingLock; + UINT32 AdvPwrMgtCtlFlags; + + MSR_REGISTER PowerCtl; + MSR_REGISTER TurboPowerLimit; + MSR_REGISTER PP0CurrentCfg; + MSR_REGISTER PerfBiasConfig; + + UINT32 ProchotRatio; + UINT32 PmaxConfig; + UINT32 SapmCtl[MAX_SOCKET]; + UINT32 PerPLimitCtl; + UINT32 C2C3TT; + UINT32 DynamicPerPowerCtl; + UINT32 PcieIltrOvrd; + + CSTATE_STRUCT Cst; + PSTATE_STRUCT Pst; + XE_STRUCT Xe; + HWPM_STRUCT Hwpm; + TURBO_RATIO_LIMIT_RATIO_CORES TurboRatioLimitRatioCores; + + UINT8 TCCActivationOffset; + +} EFI_PPM_STRUCT; + + +typedef struct { + + PPM_VERSION Version; + + EFI_CPU_CSR_ACCESS_PROTOCOL *CpuCsrAccess; + + PPM_FROM_PPMINFO_HOB *Info; + + EFI_PPM_STRUCT *Setup; + + UINTN ProcessorNumber; + +} EFI_CPU_PM_STRUCT; + + +#pragma pack() + +VOID +PStateTransition ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +InitializeCpuPPMLib ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetBiosInitDone ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetCsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCSRTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrDynamicPerfPowerCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSapmCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSwLtrOvrd ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPkgCstEntryCriteriaMask( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrResponseRatioCfg( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +SetupPCIEPkgCstEntryCriteria ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPerfPlimitControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPmaxConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrPowerCtl ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramEnergyPerfBiasConfigMsr ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgMsrPriPlaneCurtCfgCtrL ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboRatioLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +GetMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrMiscPwrMgmt ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +Program_Bios_Reset_Cpl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PFastRaplDutyCycle ( + EFI_CPU_PM_STRUCT *ppm + ); + +UINT8 +EFIAPI +GetHwpmSupport ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +HWPMInterfaceReg ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EnableAutonomousCStateControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +EnableHwpLvtThermalInterrupt( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EFIAPI +EnableHwpFeatures( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PPcuMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PHWPMMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrCLatency ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PDynamicL1 ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrCstConfigCtrlLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PForceUncoreAndMeshRatio ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PMiscWorkaroundEnable ( + EFI_CPU_PM_STRUCT *ppm + ); + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Protocol/IioUds.h b/Silicon/Intel/PurleySktPkg/Include/Protocol/IioUds.h new file mode 100644 index 0000000000..10834e0cdf --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Protocol/IioUds.h @@ -0,0 +1,50 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_IIO_UDS_PROTOCOL_H_ +#define _EFI_IIO_UDS_PROTOCOL_H_ + +#include <Setup/IioUniversalData.h> + +#define EFI_IIO_UDS_PROTOCOL_GUID \ + { 0xa7ced760, 0xc71c, 0x4e1a, 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb } + +typedef struct _EFI_IIO_UDS_PROTOCOL EFI_IIO_UDS_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *IIH_ENABLE_VC) ( + IN EFI_IIO_UDS_PROTOCOL *This, + IN UINT32 VcCtrlData + ); +/** + + Enables the requested VC in IIO + + @param This Pointer to the EFI_IOH_UDS_PROTOCOL instance. + @param VcCtrlData Data read from VC resourse control reg. + +**/ + + +typedef struct _EFI_IIO_UDS_PROTOCOL { + IIO_UDS *IioUdsPtr; + IIH_ENABLE_VC EnableVc; +} EFI_IIO_UDS_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiIioUdsProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Protocol/PciCallback.h b/Silicon/Intel/PurleySktPkg/Include/Protocol/PciCallback.h new file mode 100644 index 0000000000..9b8bfecc45 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Protocol/PciCallback.h @@ -0,0 +1,90 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_PCI_CALLBACK_H
+#define _EFI_PCI_CALLBACK_H
+
+#include <Include/IndustryStandard/Pci22.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+
+//
+// Global Id for PCI callback
+//
+#define EFI_PCI_CALLBACK_PROTOCOL_GUID \
+ { \
+ 0x1ca0e202, 0xfe9e, 0x4776, 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0x06 \
+ }
+
+typedef struct _EFI_PCI_CALLBACK_PROTOCOL EFI_PCI_CALLBACK_PROTOCOL;
+
+typedef enum {
+ EfiPciEnumerationDeviceScanning = 1,
+ EfiPciEnumerationBusNumberAssigned = 2,
+ EfiPciEnumerationResourceAssigned = 4,
+} EFI_PCI_ENUMERATION_PHASE;
+
+typedef struct {
+ PCI_TYPE00 PciHeader;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_CPU_IO2_PROTOCOL *CpuIo;
+} EFI_PCI_CALLBACK_CONTEXT;
+
+typedef
+VOID
+(EFIAPI *EFI_PCI_CALLBACK_FUNC) (
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_ENUMERATION_PHASE Phase,
+ IN EFI_PCI_CALLBACK_CONTEXT *Context
+);
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REGISTER_PCI_CALLBACK) (
+ IN EFI_PCI_CALLBACK_PROTOCOL *This,
+ IN EFI_PCI_CALLBACK_FUNC Function,
+ IN EFI_PCI_ENUMERATION_PHASE Phase
+)
+/*++
+
+Routine Description:
+
+ Register a callback during PCI bus enumeration
+
+Arguments:
+
+ This - Protocol instance pointer.
+ Function - Callback function pointer.
+ Phase - PCI enumeration phase.
+
+Returns:
+
+ EFI_SUCCESS - Function has registed successfully
+ EFI_UNSUPPORTED - The function has been regisered
+ EFI_InVALID_PARAMETER - The parameter is incorrect
+
+--*/
+;
+
+//
+// Protocol definition
+//
+typedef struct _EFI_PCI_CALLBACK_PROTOCOL {
+ EFI_REGISTER_PCI_CALLBACK RegisterPciCallback;
+} EFI_PCI_CALLBACK_PROTOCOL;
+
+extern EFI_GUID gEfiPciCallbackProtocolGuid;
+
+#endif
diff --git a/Silicon/Intel/PurleySktPkg/Include/SocketConfiguration.h b/Silicon/Intel/PurleySktPkg/Include/SocketConfiguration.h new file mode 100644 index 0000000000..aaf78d7084 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/SocketConfiguration.h @@ -0,0 +1,520 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_CONFIGURATION_H__ +#define __SOCKET_CONFIGURATION_H__ + +#define SOCKET_CONFIG_CLASS_ID 44 +#define SOCKET_CONFIG_SUBCLASS_ID 0x00 + +#define VFR_BLANK_LINE subtitle text = STRING_TOKEN(STR_NULL_STRING); +#define VFR_END_FORM endform; +#define VFR_END_FORMSET endformset; +#define VFR_HORIZ_LINE subtitle text = STRING_TOKEN(STR_HORIZONTAL_LINE); + + + +#define SOCKET_IIO_CONFIG_KEY 0xFAFB +#define SOCKET_COMMONRC_CONFIG_KEY 0xFAFA +#define SOCKET_MP_LINK_CONFIG_KEY 0xFAF9 +#define SOCKET_MEMORY_CONFIG_KEY 0xFAF8 +#define SOCKET_MISC_CONFIG_KEY 0xFAF7 +#define SOCKET_CONFIG_KEY 0xF00A +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_KEY 0xF00B +#define SOCKET_PROCESSORCORE_CONFIGURATION_KEY 0xF00C + + + +#define KEY_XMP_PROFILE 0x1DC0 +#define KEY_XMP_PROFILE1 0x1DC1 +#define KEY_CPU_ONLINE 0x10B8 + +// {26A69232-ABF8-4597-8876-A7DC0A7CA602} +#define SOCKET_CONFIG_SETUP_GUID {0x26a69232, 0xabf8, 0x4597, 0x88, 0x76, 0xa7, 0xdc, 0xa, 0x7c, 0xa6, 0x2} + + + +#define VFR_FORMID_SOCKET 0x510 +#define VFR_FORMID_COMMONRC 0x511 +#define VFR_FORMID_KTI 0x512 +#define VFR_FORMID_PROCESSOR 0x513 +#define VFR_FORMID_KTI_STATUS 0x514 + +#define VFR_FORMID_SOCKET_IIO_CONFIGURATION 0x517 + +#define VFR_FORMID_IIO 0x518 +#define VFR_FORMID_IIO2 0x519 +#define VFR_FORMID_IIO3 0x51A +#define VFR_FORMID_IIO4 0x51B +#define VFR_FORMID_PWRMGT 0x51C + +// +// KTI Form for SV +// + +#define VFR_FORMID_KTI_GENERAL 0x521 +#define VFR_FORMID_KTISYSTEMWIDE 0x522 +#define VFR_FORMID_KTISYSTEM_PHY_LINK 0x523 +#define VFR_FORMID_KTISYSTEM_OSB 0x524 +#define VFR_FORMID_KTIPERSOCKET 0x525 +#define VFR_FID_KTI_CPU0 0x526 +#define VFR_FID_KTI_CPU1 0x527 +#define VFR_FID_KTI_CPU2 0x528 +#define VFR_FID_KTI_CPU3 0x529 +#define VFR_FID_KTI_CPU4 0x52A +#define VFR_FID_KTI_CPU5 0x52B +#define VFR_FID_KTI_CPU6 0x52C +#define VFR_FID_KTI_CPU7 0x52D +// +// KTI Form IDs +// +#define VFR_FORMID_CPU_KTII 0x530 +#define VFR_FID_KTI_STATUS 0x531 +#define VFR_FID_KTI_TOPOLOGY 0x532 +#define VFR_FID_KTI_TOPOLOGY_MATRIX 0x533 +#define VFR_FID_IIO_DEV_HIDE 0x534 +#define VFR_FID_KTI_SOCKET_RES 0x535 +#define VFR_FID_KTI_SOCKET_RES_REQUEST 0x536 +#define VFR_FID_KTI_SOCKET_RES_STATUS 0x537 +#define VFR_FORMID_MEMORY 0x540 +#define VFR_FORMID_MEMORY_RAS 0x541 +#define VFR_FID_KTI_CPU0_LINK0 0x542 +#define VFR_FID_KTI_CPU0_LINK1 0x543 +#define VFR_FID_KTI_CPU0_LINK2 0x544 +#define VFR_FID_KTI_CPU1_LINK0 0x545 +#define VFR_FID_KTI_CPU1_LINK1 0x546 +#define VFR_FID_KTI_CPU1_LINK2 0x547 +#define VFR_FID_KTI_CPU2_LINK0 0x548 +#define VFR_FID_KTI_CPU2_LINK1 0x549 +#define VFR_FID_KTI_CPU2_LINK2 0x54A +#define VFR_FID_KTI_CPU3_LINK0 0x54B +#define VFR_FID_KTI_CPU3_LINK1 0x54C +#define VFR_FID_KTI_CPU3_LINK2 0x54D +#define VFR_FID_KTI_CPU4_LINK0 0x54E +#define VFR_FID_KTI_CPU4_LINK1 0x54F +#define VFR_FORMID_BRANCH_RANK_CONFIG 0x571 +#define VFR_FORMID_VALHOOKS_CONFIG 0x572 +#define VFR_FORMID_THERMTHRT_CONFIG 0x573 +#define VFR_FORMID_MEMTOPOLOGY_DISPLAY 0x574 +#define VFR_FORMID_PAGE_POLICY_DISPLAY 0x57D +#define VFR_FORMID_MEMORY_TRAINING_DISPLAY 0x57E +#define VFR_FORMID_MEM_PWR_SAVE_ADV_ID 0x57F +#define VFR_FORMID_CKE_DISPLAY 0x59F +#define VFR_FORMID_SREF_DISPLAY 0x5A0 +#define VFR_FORMID_MEM_THERMAL_ID 0x580 +#define VFR_FORMID_XMP_DISPLAY 0x581 +#define VFR_FORMID_MEM_PM_CFG_ID 0x582 +#define VFR_FORMID_MEM_MAP 0x58A +#define VFR_FORMID_RAPL 0x58B +#define VFR_FORMID_SECURE_ERASE 0x58E + +#define VFR_FID_KTI_CPU4_LINK2 0x590 +#define VFR_FID_KTI_CPU5_LINK0 0x591 +#define VFR_FID_KTI_CPU5_LINK1 0x592 +#define VFR_FID_KTI_CPU5_LINK2 0x593 +#define VFR_FID_KTI_CPU6_LINK0 0x594 +#define VFR_FID_KTI_CPU6_LINK1 0x595 +#define VFR_FID_KTI_CPU6_LINK2 0x596 +#define VFR_FID_KTI_CPU7_LINK0 0x597 +#define VFR_FID_KTI_CPU7_LINK1 0x598 +#define VFR_FID_KTI_CPU7_LINK2 0x599 + +#define VFR_FID_KTI_WARNING_LOG 0x59E + + +// +// MEMORY Form IDs +// + + + + +// +// IIO Form IDs +// +#define VFR_FORMID_IIO_CONFIG 0x450 +#define VFR_FORMID_VTD 0x451 +#define VFR_FORMID_PCIE 0x452 +#define VFR_FORMID_PCIE_IIO0P0 0x453 +#define VFR_FORMID_PCIE_IIO0P1 0x454 +#define VFR_FORMID_PCIE_IIO0P2 0x455 +#define VFR_FORMID_PCIE_IIO0P3 0x456 +#define VFR_FORMID_PCIE_IIO0P4 0x457 +#define VFR_FORMID_PCIE_IIO0P5 0x458 +#define VFR_FORMID_PCIE_IIO0P6 0x459 +#define VFR_FORMID_PCIE_IIO0P7 0x45A +#define VFR_FORMID_PCIE_IIO0P8 0x45B +#define VFR_FORMID_PCIE_IIO0P9 0x45C +#define VFR_FORMID_PCIE_IIO0P10 0x45D +#define VFR_FORMID_PCIE_IIO0P11 0x45E +#define VFR_FORMID_PCIE_IIO0P12 0x45F +#define VFR_FORMID_PCIE_IIO0P13 0x460 +#define VFR_FORMID_PCIE_IIO0P14 0x461 +#define VFR_FORMID_PCIE_IIO0P15 0x488 +#define VFR_FORMID_PCIE_IIO0P16 0x489 +#define VFR_FORMID_PCIE_IIO0P17 0x48A +#define VFR_FORMID_PCIE_IIO0P18 0x48B +#define VFR_FORMID_PCIE_IIO0P19 0x48C +#define VFR_FORMID_PCIE_IIO0P20 0x48D + +#define VFR_FORMID_PCIE_IIO1P0 0x462 +#define VFR_FORMID_PCIE_IIO1P1 0x463 +#define VFR_FORMID_PCIE_IIO1P2 0x469 +#define VFR_FORMID_PCIE_IIO1P3 0x46A +#define VFR_FORMID_PCIE_IIO1P4 0x46B +#define VFR_FORMID_PCIE_IIO1P5 0x46C +#define VFR_FORMID_PCIE_IIO1P6 0x46D +#define VFR_FORMID_PCIE_IIO1P7 0x46E +#define VFR_FORMID_PCIE_IIO1P8 0x46F +#define VFR_FORMID_PCIE_IIO1P9 0x470 +#define VFR_FORMID_PCIE_IIO1P10 0x475 +#define VFR_FORMID_PCIE_IIO1P11 0x476 +#define VFR_FORMID_PCIE_IIO1P12 0x477 +#define VFR_FORMID_PCIE_IIO1P13 0x478 +#define VFR_FORMID_PCIE_IIO1P14 0x479 +#define VFR_FORMID_PCIE_IIO1P15 0x48E +#define VFR_FORMID_PCIE_IIO1P16 0x48F +#define VFR_FORMID_PCIE_IIO1P17 0x490 +#define VFR_FORMID_PCIE_IIO1P18 0x491 +#define VFR_FORMID_PCIE_IIO1P19 0x492 +#define VFR_FORMID_PCIE_IIO1P20 0x493 + +#define VFR_FORMID_IIO0 0x47A +#define VFR_FORMID_IIO1 0x47B +#define VFR_FORMID_IOAT_CONFIG 0x47C +#define VFR_FORMID_IIO0IOAT 0x47D +#define VFR_FORMID_IIO1IOAT 0x47E +#define VFR_FORMID_IIO2IOAT 0x47F +#define VFR_FORMID_IIO3IOAT 0x480 +#define VFR_FORMID_IIO_PCIE_SLOT 0x487 +// +// extended IIO form IDs for 4S +// +#define VFR_FORMID_PCIE_IIO2P0 0x0690 +#define VFR_FORMID_PCIE_IIO2P1 0x0691 +#define VFR_FORMID_PCIE_IIO2P2 0x0692 +#define VFR_FORMID_PCIE_IIO2P3 0x0693 +#define VFR_FORMID_PCIE_IIO2P4 0x0694 +#define VFR_FORMID_PCIE_IIO2P5 0x0695 +#define VFR_FORMID_PCIE_IIO2P6 0x0696 +#define VFR_FORMID_PCIE_IIO2P7 0x0697 +#define VFR_FORMID_PCIE_IIO2P8 0x0698 +#define VFR_FORMID_PCIE_IIO2P9 0x0699 +#define VFR_FORMID_PCIE_IIO2P10 0x069A +#define VFR_FORMID_PCIE_IIO2P11 0x069B +#define VFR_FORMID_PCIE_IIO2P12 0x069C +#define VFR_FORMID_PCIE_IIO2P13 0x069D +#define VFR_FORMID_PCIE_IIO2P14 0x069E +#define VFR_FORMID_PCIE_IIO2P15 0x06AA +#define VFR_FORMID_PCIE_IIO2P16 0x06AB +#define VFR_FORMID_PCIE_IIO2P17 0x06AC +#define VFR_FORMID_PCIE_IIO2P18 0x06AD +#define VFR_FORMID_PCIE_IIO2P19 0x06AE +#define VFR_FORMID_PCIE_IIO2P20 0x06AF + +#define VFR_FORMID_PCIE_IIO3P0 0x069F +#define VFR_FORMID_PCIE_IIO3P1 0x0670 +#define VFR_FORMID_PCIE_IIO3P2 0x0671 +#define VFR_FORMID_PCIE_IIO3P3 0x0672 +#define VFR_FORMID_PCIE_IIO3P4 0x0673 +#define VFR_FORMID_PCIE_IIO3P5 0x06A0 +#define VFR_FORMID_PCIE_IIO3P6 0x06A1 +#define VFR_FORMID_PCIE_IIO3P7 0x06A2 +#define VFR_FORMID_PCIE_IIO3P8 0x06A3 +#define VFR_FORMID_PCIE_IIO3P9 0x06A4 +#define VFR_FORMID_PCIE_IIO3P10 0x06A5 +#define VFR_FORMID_PCIE_IIO3P11 0x06A6 +#define VFR_FORMID_PCIE_IIO3P12 0x06A7 +#define VFR_FORMID_PCIE_IIO3P13 0x06A8 +#define VFR_FORMID_PCIE_IIO3P14 0x06A9 +#define VFR_FORMID_PCIE_IIO3P15 0x06B0 +#define VFR_FORMID_PCIE_IIO3P16 0x06B1 +#define VFR_FORMID_PCIE_IIO3P17 0x06B2 +#define VFR_FORMID_PCIE_IIO3P18 0x06B3 +#define VFR_FORMID_PCIE_IIO3P19 0x06B4 +#define VFR_FORMID_PCIE_IIO3P20 0x06B5 + +#define VFR_FORMID_VMD 0x06C0 +#define VFR_FORMID_VMD_IIO0 0x06C1 +#define VFR_FORMID_VMD_IIO1 0x06C2 +#define VFR_FORMID_VMD_IIO2 0x06C3 +#define VFR_FORMID_VMD_IIO3 0x06C4 +#define VFR_FORMID_IIO_RTO_CONFIG 0x06C5 +#define VFR_FORMID_IIO_RTO_SKT0SVDEVHIDE 0x06C6 +#define VFR_FORMID_IIO_RTO_SKT1SVDEVHIDE 0x06C7 +#define VFR_FORMID_IIO_RTO_SKT2SVDEVHIDE 0x06C8 +#define VFR_FORMID_IIO_RTO_SKT3SVDEVHIDE 0x06C9 + +#define VFR_FORMID_RTO_PCIE_IIO0P0 0x06CA +#define VFR_FORMID_RTO_PCIE_IIO0P1 0x06CB +#define VFR_FORMID_RTO_PCIE_IIO0P2 0x06CD +#define VFR_FORMID_RTO_PCIE_IIO0P3 0x06CE +#define VFR_FORMID_RTO_PCIE_IIO0P4 0x06CF +#define VFR_FORMID_RTO_PCIE_IIO0P5 0x06D0 +#define VFR_FORMID_RTO_PCIE_IIO0P6 0x06D1 +#define VFR_FORMID_RTO_PCIE_IIO0P7 0x06D2 +#define VFR_FORMID_RTO_PCIE_IIO0P8 0x06D3 +#define VFR_FORMID_RTO_PCIE_IIO0P9 0x06D4 +#define VFR_FORMID_RTO_PCIE_IIO0P10 0x06D5 +#define VFR_FORMID_RTO_PCIE_IIO0P11 0x06D6 +#define VFR_FORMID_RTO_PCIE_IIO0P12 0x06D7 +#define VFR_FORMID_RTO_PCIE_IIO0P13 0x06D8 +#define VFR_FORMID_RTO_PCIE_IIO0P14 0x06D9 +#define VFR_FORMID_RTO_PCIE_IIO0P15 0x06DA +#define VFR_FORMID_RTO_PCIE_IIO0P16 0x06DB +#define VFR_FORMID_RTO_PCIE_IIO0P17 0x06DC +#define VFR_FORMID_RTO_PCIE_IIO0P18 0x06DD +#define VFR_FORMID_RTO_PCIE_IIO0P19 0x06DE +#define VFR_FORMID_RTO_PCIE_IIO0P20 0x06DF + +#define VFR_FORMID_RTO_PCIE_IIO1P0 0x06E0 +#define VFR_FORMID_RTO_PCIE_IIO1P1 0x06E1 +#define VFR_FORMID_RTO_PCIE_IIO1P2 0x06E2 +#define VFR_FORMID_RTO_PCIE_IIO1P3 0x06E3 +#define VFR_FORMID_RTO_PCIE_IIO1P4 0x06E4 +#define VFR_FORMID_RTO_PCIE_IIO1P5 0x06E5 +#define VFR_FORMID_RTO_PCIE_IIO1P6 0x06E6 +#define VFR_FORMID_RTO_PCIE_IIO1P7 0x06E7 +#define VFR_FORMID_RTO_PCIE_IIO1P8 0x06E8 +#define VFR_FORMID_RTO_PCIE_IIO1P9 0x06E9 +#define VFR_FORMID_RTO_PCIE_IIO1P10 0x06EA +#define VFR_FORMID_RTO_PCIE_IIO1P11 0x06EB +#define VFR_FORMID_RTO_PCIE_IIO1P12 0x06EC +#define VFR_FORMID_RTO_PCIE_IIO1P13 0x06ED +#define VFR_FORMID_RTO_PCIE_IIO1P14 0x06EE +#define VFR_FORMID_RTO_PCIE_IIO1P15 0x06EF +#define VFR_FORMID_RTO_PCIE_IIO1P16 0x06F0 +#define VFR_FORMID_RTO_PCIE_IIO1P17 0x06F1 +#define VFR_FORMID_RTO_PCIE_IIO1P18 0x06F2 +#define VFR_FORMID_RTO_PCIE_IIO1P19 0x06F3 +#define VFR_FORMID_RTO_PCIE_IIO1P20 0x06F4 +#define VFR_FORMID_RTO_PCIE_IIO2P0 0x06F5 +#define VFR_FORMID_RTO_PCIE_IIO2P1 0x06F6 +#define VFR_FORMID_RTO_PCIE_IIO2P2 0x06F7 +#define VFR_FORMID_RTO_PCIE_IIO2P3 0x06F8 +#define VFR_FORMID_RTO_PCIE_IIO2P4 0x06F9 +#define VFR_FORMID_RTO_PCIE_IIO2P5 0x06FA +#define VFR_FORMID_RTO_PCIE_IIO2P6 0x06FB +#define VFR_FORMID_RTO_PCIE_IIO2P7 0x06FC +#define VFR_FORMID_RTO_PCIE_IIO2P8 0x06FD +#define VFR_FORMID_RTO_PCIE_IIO2P9 0x06FE +#define VFR_FORMID_RTO_PCIE_IIO2P10 0x06FF +#define VFR_FORMID_RTO_PCIE_IIO2P11 0x0700 +#define VFR_FORMID_RTO_PCIE_IIO2P12 0x0701 +#define VFR_FORMID_RTO_PCIE_IIO2P13 0x0702 +#define VFR_FORMID_RTO_PCIE_IIO2P14 0x0703 +#define VFR_FORMID_RTO_PCIE_IIO2P15 0x0704 +#define VFR_FORMID_RTO_PCIE_IIO2P16 0x0705 +#define VFR_FORMID_RTO_PCIE_IIO2P17 0x0706 +#define VFR_FORMID_RTO_PCIE_IIO2P18 0x0707 +#define VFR_FORMID_RTO_PCIE_IIO2P19 0x0708 +#define VFR_FORMID_RTO_PCIE_IIO2P20 0x0709 + +#define VFR_FORMID_RTO_PCIE_IIO3P0 0x070A +#define VFR_FORMID_RTO_PCIE_IIO3P1 0x070B +#define VFR_FORMID_RTO_PCIE_IIO3P2 0x070C +#define VFR_FORMID_RTO_PCIE_IIO3P3 0x070D +#define VFR_FORMID_RTO_PCIE_IIO3P4 0x070E +#define VFR_FORMID_RTO_PCIE_IIO3P5 0x070F +#define VFR_FORMID_RTO_PCIE_IIO3P6 0x0710 +#define VFR_FORMID_RTO_PCIE_IIO3P7 0x0711 +#define VFR_FORMID_RTO_PCIE_IIO3P8 0x0712 +#define VFR_FORMID_RTO_PCIE_IIO3P9 0x0713 +#define VFR_FORMID_RTO_PCIE_IIO3P10 0x0714 +#define VFR_FORMID_RTO_PCIE_IIO3P11 0x0715 +#define VFR_FORMID_RTO_PCIE_IIO3P12 0x0716 +#define VFR_FORMID_RTO_PCIE_IIO3P13 0x0717 +#define VFR_FORMID_RTO_PCIE_IIO3P14 0x0718 +#define VFR_FORMID_RTO_PCIE_IIO3P15 0x0719 +#define VFR_FORMID_RTO_PCIE_IIO3P16 0x071A +#define VFR_FORMID_RTO_PCIE_IIO3P17 0x071B +#define VFR_FORMID_RTO_PCIE_IIO3P18 0x071C +#define VFR_FORMID_RTO_PCIE_IIO3P19 0x071D +#define VFR_FORMID_RTO_PCIE_IIO3P20 0x071E + +#define VFR_FORMID_RTO_IIO0 0x071F +#define VFR_FORMID_RTO_IIO1 0x0720 +#define VFR_FORMID_RTO_IIO2 0x0721 +#define VFR_FORMID_RTO_IIO3 0x0722 + +#define VFR_FORMID_PCIEAIC 0x0723 +#define VFR_FORMID_PCIEAIC_IIO0 0x0724 +#define VFR_FORMID_PCIEAIC_IIO1 0x0725 +#define VFR_FORMID_PCIEAIC_IIO2 0x0726 +#define VFR_FORMID_PCIEAIC_IIO3 0x0727 + +#define VFR_FORMLABLE_SOCKET_TOP 0x4062 +#define VFR_FORMLABLE_SOCKET_BOTTOM 0x4063 + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + + +//Per Socket forms for active core count and IOT options +#define VFR_FORMID_PER_SOCKET 0x300 +#define VFR_FORMID_CPU_SOCKET0 0x301 +#define VFR_FORMID_CPU_SOCKET1 0x302 +#define VFR_FORMID_CPU_SOCKET2 0x303 +#define VFR_FORMID_CPU_SOCKET3 0x304 +#define VFR_FORMID_CPU_SOCKET4 0x305 +#define VFR_FORMID_CPU_SOCKET5 0x306 +#define VFR_FORMID_CPU_SOCKET6 0x307 +#define VFR_FORMID_CPU_SOCKET7 0x308 +#define VFR_FORMID_IIO_ERR 0x309 + +#define SOCKET0_CPUPWRADVPMCFG_FORMID 0x310 +#define SOCKET1_CPUPWRADVPMCFG_FORMID 0x311 +#define SOCKET2_CPUPWRADVPMCFG_FORMID 0x312 +#define SOCKET3_CPUPWRADVPMCFG_FORMID 0x313 +#define SOCKET4_CPUPWRADVPMCFG_FORMID 0x314 +#define SOCKET5_CPUPWRADVPMCFG_FORMID 0x315 +#define SOCKET6_CPUPWRADVPMCFG_FORMID 0x316 +#define SOCKET7_CPUPWRADVPMCFG_FORMID 0x317 + +//P State Control Form +#define P_STATE_CONTROL_FORMID 0x380 +#define XE_RATIO_LIMIT_FORMID 0x381 +#define VID_OPTIONS_FORM_ID 0x382 + +//HWPM control Form +#define HWPM_STATE_CONTROL_FORMID 0x385 + +//C State Control Form +#define CPU0_CSTATE_CONTROL_FORM_ID 0x390 +#define HLV_SASV_FORM_ID 0x391 + +//T State Control Form +#define CPU_TSTATE_CONTROL_FORM_ID 0x392 + +//CPU Theraml Management +#define CPU_THERMMAL_MANAGE_FORM_ID 0x393 + +//Package C State Control +#define PACKAGE_CSTATE_CONTROL_FORM_ID 0x394 + +//DST 2.0 +#define CPU_THERMAL_DTS_2_0_FORM_ID 0x395 + +//Advacned PM Tuning Form +#define CPU_POWER_ADVANCED_CONFIG_FORM_ID 0x3A0 +#define ENERGY_PERF_BIAS_FORM_ID 0x3A1 +//#define PROG_POWERCTL_MSR_FORM_ID 0x3A2 +#define PROG_MSR_PP_CURT_CFG_CTRL_FORM_ID 0x3A3 +#define PROG_MSR_PP_CURT_PSI_CONFIG_FORM_ID 0x3A4 +#define PROG_ENTRY_CRITERIA_FORM_ID 0x3A5 +#define PROG_CSR_SWLTROVRD_FORM_ID 0x3A6 +#define PROG_CSR_DYNAMIC_PERF_POWER_CTL_FORM_ID 0x3A7 +#define PROG_CSR_SAPMCTL_FORM_ID 0x3A8 +#define PROG_CSR_PERF_P_LIMIT_FORM_ID 0x3A9 + +#define DRAM_RAPL_FORMID 0x3B0 +#define SOCKET_RAPL_FORMID 0x3C0 + +#define ACPI_S_STATE_FORMID 0x3D0 + +#define PROG_CSR_PMAX_CONFIG_FORM_ID 0x3E0 + +#define SOCKET0_PKGCENTRY_FORMID 0x3F0 +#define SOCKET1_PKGCENTRY_FORMID 0x3F1 +#define SOCKET2_PKGCENTRY_FORMID 0x3F2 +#define SOCKET3_PKGCENTRY_FORMID 0x3F3 +#define SOCKET4_PKGCENTRY_FORMID 0x3F4 +#define SOCKET5_PKGCENTRY_FORMID 0x3F5 +#define SOCKET6_PKGCENTRY_FORMID 0x3F6 +#define SOCKET7_PKGCENTRY_FORMID 0x3F7 + +#define SOCKET0_PKGCSAPM_FORMID 0x3F8 +#define SOCKET1_PKGCSAPM_FORMID 0x3F9 +#define SOCKET2_PKGCSAPM_FORMID 0x3FA +#define SOCKET3_PKGCSAPM_FORMID 0x3FB +#define SOCKET4_PKGCSAPM_FORMID 0x3FC +#define SOCKET5_PKGCSAPM_FORMID 0x3FD +#define SOCKET6_PKGCSAPM_FORMID 0x3FE +#define SOCKET7_PKGCSAPM_FORMID 0x3FF + +#define SOCKET0_PMAX_CONFIG_FORMID 0x400 +#define SOCKET1_PMAX_CONFIG_FORMID 0x401 +#define SOCKET2_PMAX_CONFIG_FORMID 0x402 +#define SOCKET3_PMAX_CONFIG_FORMID 0x403 +#define SOCKET4_PMAX_CONFIG_FORMID 0x404 +#define SOCKET5_PMAX_CONFIG_FORMID 0x405 +#define SOCKET6_PMAX_CONFIG_FORMID 0x406 +#define SOCKET7_PMAX_CONFIG_FORMID 0x407 + +// {516D5A04-C0D5-4657-B908-E4FB1D935EF0} +#define SOCKET_FORMSET_GUID \ + { \ + 0x516d5a04, 0xc0d5, 0x4657, 0xb9, 0x8, 0xe4, 0xfb, 0x1d, 0x93, 0x5e, 0xf0 \ + } + +// {DD84017E-7F52-48F9-B16E-50ED9E0DBE27} +#define SOCKET_IIO_CONFIG_GUID \ + { \ + 0xdd84017e, 0x7f52, 0x48f9, 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0xd, 0xbe, 0x27 \ + } + +// {4402CA38-808F-4279-BCEC-5BAF8D59092F} +#define SOCKET_COMMONRC_CONFIG_GUID \ + { \ + 0x4402ca38, 0x808f, 0x4279, 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f \ + } + +// {2B9B22DE-2AD4-4ABC-957D-5F18C504A05C} +#define SOCKET_MP_LINK_CONFIG_GUID \ + { \ + 0x2b9b22de, 0x2ad4, 0x4abc, 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c \ + } + +// {CA3FF937-D646-4936-90E8-1B950649B389} +#define SOCKET_PCI_RESOURCE_CONFIG_DATA_GUID \ + { \ + 0xca3ff937, 0xd646, 0x4936, 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 \ + } + +// {98CF19ED-4109-4681-B79D-9196757C7824} +#define SOCKET_MEMORY_CONFIG_GUID \ + { \ + 0x98cf19ed, 0x4109, 0x4681, 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 \ + } + +// {6BE64B20-C679-4ECD-ACE8-87AB4B70EC06} +#define SOCKET_MISC_CONFIG_GUID \ + { \ + 0x6be64b20, 0xc679, 0x4ecd, 0xac, 0xe8, 0x87, 0xab, 0x4b, 0x70, 0xec, 0x6 \ + } +// {A1047342-BDBA-4DAE-A67A-40979B65C7F8} +#define SOCKET_POWERMANAGEMENT_CONFIG_GUID \ + { \ + 0xA1047342, 0xBDBA, 0x4DAE, 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 \ + } +// {07013588-C789-4E12-A7C3-88FAFAE79F7C} +#define SOCKET_PROCESSORCORE_CONFIG_GUID \ + { \ + 0x07013588, 0xC789, 0x4E12, 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C \ + } +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/UncoreCommonIncludes.h b/Silicon/Intel/PurleySktPkg/Include/UncoreCommonIncludes.h new file mode 100644 index 0000000000..f6a0aa5743 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/UncoreCommonIncludes.h @@ -0,0 +1,360 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _UNCORE_COMMON_INCLUDES_H_ +#define _UNCORE_COMMON_INCLUDES_H_ + +#ifndef V_INTEL_VID +#define V_INTEL_VID 0x8086 +#endif + +#ifndef MAX_CORE +#define MAX_CORE 28 // Maximum cores per CPU (SKX) +#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU +#endif + +#define MAX_PROCESSOR_CORE_RATIO 100 +#define DEFAULT_PROCESSOR_CORE_RATIO 23 +#define MAX_SCRAMBLE_SEED_LOW 65535 +#define MAX_SCRAMBLE_SEED_HIGH 65535 +#define ITURBO_MODE_TRADITIONAL 0 +#define ITURBO_MODE_POWER_OPTIMIZED 4 +#define MAX_PROCESSOR_TSEG 5 + + +// Define the different SKX package Sku's +#define SKX_PHY_CHOP_HCC 0x2 +#define SKX_PHY_CHOP_MCC 0x1 +#define SKX_PHY_CHOP_LCC 0x0 + +// +// Defines used for variables to be range checked before consumption. +// For MiniBIOS support, these are also defined in +// so any changes here need to be updated in these files as well. +// If you change this, please also update CPU_FAMILY_XXX in \Library\ProcMemInit\Include\CpuPciAccess.h, Library\ProcessorStartup\Ia32\ProcessorStartupPlatform.inc +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif + +// SKX REV_ID SiliconID SteppingID CPUID ChopType +// A0 0 0 0 0x50650 3 +// A1 0 1 0 0x50650 3 +// A2 2 2 1 0x50651 3 +// B0 3 3 2 0x50652 3 +// L0 4 4 2 0x50652 2 +// B1 5 5 3 0x50653 3 +// H0 6 6 4 0x50654 3 (xcc) +// M0 7 6 4 0x50654 2 (hcc) +// U0 8 6 4 0x50654 0 (lcc) +// +// xy_REV_SKX is the logical ID for BIOS to distinguish the Si +// A0 and A1 still keep to 0 +// +#ifndef A0_REV +#define A0_REV 0x00 +#endif +#ifndef A0_REV_SKX +#define A0_REV_SKX A0_REV +#endif +#ifndef A1_REV_SKX +#define A1_REV_SKX A0_REV +#endif +#ifndef A2_REV_SKX +#define A2_REV_SKX 0x02 +#endif +#ifndef B0_REV_SKX +#define B0_REV_SKX 0x03 +#endif +#ifndef L0_REV_SKX +#define L0_REV_SKX 0x04 +#endif +#ifndef B1_REV_SKX +#define B1_REV_SKX 0x05 +#endif +#ifndef H0_REV_SKX +#define H0_REV_SKX 0x06 +#endif +#ifndef M0_REV_SKX +#define M0_REV_SKX 0x07 +#endif +#ifndef U0_REV_SKX +#define U0_REV_SKX 0x08 +#endif + +#ifndef C0_REV_SKX +#define C0_REV_SKX 0x09 +#endif + +// +// Xy_CPU_STEP is from CPUID +// +#ifndef A0_CPU_STEP +#define A0_CPU_STEP 0x00 +#endif +#ifndef A1_CPU_STEP +#define A1_CPU_STEP A0_CPU_STEP +#endif +#ifndef A2_CPU_STEP +#define A2_CPU_STEP 0x01 +#endif +#ifndef B0_CPU_STEP +#define B0_CPU_STEP 0x02 +#endif +#ifndef L0_CPU_STEP +#define L0_CPU_STEP 0x02 +#endif +#ifndef B1_CPU_STEP +#define B1_CPU_STEP 0x03 +#endif +#ifndef H0_CPU_STEP +#define H0_CPU_STEP 0x04 +#endif +#ifndef M0_CPU_STEP +#define M0_CPU_STEP 0x04 +#endif +#ifndef U0_CPU_STEP +#define U0_CPU_STEP 0x04 +#endif + +#ifndef C0_CPU_STEP +#define C0_CPU_STEP 0x05 +#endif + +#include "MaxSocket.h" + +#define MAX_THREAD 2 +#define MAX_DIE 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_SOCKET) + +#ifndef MAX_HA +#define MAX_HA 2 +#endif + + +// If you change this, please also update MAX_KTI_PORTS in \Library\ProcMemInit\Platform\Include\PlatformHost.h +#ifndef MAX_KTI_PORTS +#define MAX_KTI_PORTS 3 // Max KTI ports supported +#endif + +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_IMC +#define MAX_IMC 2 // Maximum memory controllers per socket +#endif + +// If you change this, please also update MAX_MC_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_MC_CH +#define MAX_MC_CH 3 // Max number of channels per MC (3 for EP) +#endif + + +// If you change this, please also update MAX_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_CH +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) +#endif + +// If you change this, please also update MAX_DIMM in Library\ProcMemInit\Include\MemHostChip.h +#ifndef MAX_DIMM +#define MAX_DIMM 2 // Max DIMM per channel +#endif + +// If you change this, please also update MC_MAX_NODE in Library\ProcMemInit\Include\MemHostChip.h +#ifndef MC_MAX_NODE +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes +#endif + +// If you change this, please also update MAX_SYS_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_SYS_CH +#define MAX_SYS_CH (MAX_CH * MAX_SOCKET) // Max channels in the system +#endif +#define MAX_SYS_DIMM MAX_SYS_CH * MAX_DIMM + +#define MAX_CRS_ENTRIES_PER_NODE 4 // Max number of ranges allowed on a memory node +#ifndef NUMBER_PORTS_PER_SOCKET +#define NUMBER_PORTS_PER_SOCKET 21 +#endif + +#ifndef CB3_DEVICES_PER_SOCKET +#define CB3_DEVICES_PER_SOCKET 8 +#endif + +#ifndef TOTAL_CB3_DEVICES +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#endif +#endif + +#ifndef MaxIIO +#define MaxIIO MAX_SOCKET +#endif + +#ifndef MAX_TOTAL_PORTS +#if MAX_SOCKET > 4 +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal +#else +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO +#endif +#endif + +#ifndef TOTAL_IIO_STACKS +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure! +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#endif +#endif + +#ifndef NUMBER_NTB_PORTS_PER_SOCKET +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#endif + +#ifndef MAX_NTB_PORTS + +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#endif +#endif + +#ifndef VMD_STACK_PER_SOCKET +#define VMD_STACK_PER_SOCKET 3 +#endif + +#ifndef VMD_PORT_PER_STACK +#define VMD_PORT_PER_STACK 4 +#endif + +#ifndef VMD_PORTS_PER_SOCKET +#define VMD_PORTS_PER_SOCKET 12 +#endif + +#if MAX_SOCKET > 4 +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/ +#endif +#else +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/ +#endif +#endif + +#ifndef NUM_DEVHIDE_REGS +#define NUM_DEVHIDE_REGS 8 +#endif + +#ifndef MAX_DEVHIDE_REGS +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#endif + +#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM + +#if MAX_SOCKET > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#endif + +#endif + + +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + +// +// Resource Ratio units used by Uncore Init PEIM. +// +// Assumption: these values must be 2^N; Otherwise the algorithm in OemProcMemInit.c +// needs to be adjusted: the "if (Alignment > KTI_SOCKET_BUS_RATIO_UNIT) {" should be +// removed when computing adjusted "Length". +// +#define KTI_SOCKET_BUS_RATIO_UNIT 0x20 +#define KTI_SOCKET_IO_RATIO_UNIT 0x2000 +#define KTI_SOCKET_MMIOL_RATIO_UNIT 0x4000000 +// +// Maximum alignment bit allowed for Socket PCI Resources. +// +#define KTI_SOCKET_MAX_BUS_ALIGNMENT 0x8 +#define KTI_SOCKET_MAX_IO_ALIGNMENT 0x10 +#define KTI_SOCKET_MAX_MMIOL_ALIGNMENT 0x20 + +#ifndef MAX_IIO_STACK +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 +#endif + +#ifndef UNDEFINED_RAS +#define HEDT_RAS 0x0 +#define BASIC_RAS_AX 0x1 // Valid in A stepping only. +#define S1WS_RAS 0x2 // Not valid in A stepping. +#define CORE_RAS 0x3 // Not valid in A stepping . +#define STANDARD_RAS 0x4 +#define FPGA_RAS 0x5 // Not valid in A stepping. +#define ADVANCED_RAS 0x6 +#define UNDEFINED_RAS 0x7 +#endif + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID "INTEL " +#define EFI_ACPI_OEM_TABLE_ID 0x59454C525550 // "PURLEY" +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL" +#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009 + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..e40505d880 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h @@ -0,0 +1,62 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include <SysHost.h> +#include <MemHost.h>
+#include <Library/PcieAddress.h> + +#include <CsrToPcieAddress.h> +#include <CpuPciAccessCommon.h> + + +typedef enum { + BUS_CLASS = 0, + DEVICE_CLASS = 1, + FUNCTION_CLASS = 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf new file mode 100644 index 0000000000..ccdf763bef --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf @@ -0,0 +1,92 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CsrToPcieDxeLib
+ FILE_GUID = FF3C93E7-30DE-49DE-9C02-56C2BC077561
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CsrToPcieLib
+
+## {FF3C93E7-30DE-49DE-9C02-56C2BC077561}
+##{ 0xff3c93e7, 0x30de, 0x49de, { 0x9c, 0x2, 0x56, 0xc2, 0xbc, 0x7, 0x75, 0x61 } };
+
+
+[Sources]
+ CsrToPcieLib.c
+ ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ UefiRuntimeServicesTableLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiIioUdsProtocolGuid
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Depex]
+ gEfiIioUdsProtocolGuid
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+
+
+[BuildOptions.Ia32]
+ MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+
+[BuildOptions.X64]
+ MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS)
diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c new file mode 100644 index 0000000000..d6b98f2aec --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c @@ -0,0 +1,185 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CpuCsrAccessDefine.h" +#include "CpuPciAccess.h" + +CPU_CSR_ACCESS_VAR *gCpuCsrAccessVarPtr = NULL; +CPU_CSR_ACCESS_VAR gCpuCsrAccessVar; + + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ) +{ + return 0; +}; + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType +// UINT8 SocId, +// UINT8 BoxType + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT32 Data32 =0 ; + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + if(BDFType == BUS_CLASS){ + Data32 = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else if(BDFType == DEVICE_CLASS){ + Data32 = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else { + Data32 = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } + return Data32; + +} + +VOID +GetBDF ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + USRA_PCIE_ADDR_TYPE *PcieAddress + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + PcieAddress->Bus = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Dev = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Func = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Seg = SocId; // Refcode and EFI data structure difference. Refcode treats this array as 1 entry per socket, and not per segment, thus we index by SocId for now.. +} +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CPU_CSR_ACCESS_VAR *pCpuCsrAccessVar; + USRA_ADDRESS UsraAddress; + INTN MmCfgBase; + + /********************************************************************************************************* + ToDo: + For now, this implementation only covers the Bus/Dev/Fun number generation for IVT and HSX CPUs. + Register offset and size information comes from the HSX style register offset passed to this function. + When the auto generation of header files using the new format is available, then we need to implement + the logic to translate the register pseudo offset into real offset. + *********************************************************************************************************/ + Address->Attribute.AccessWidth = (UINT8) (((((CSR_OFFSET *) &Address->Csr.Offset)->Bits.size) & 0x06) >> 1); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); + pCpuCsrAccessVar = NULL; + +#else + gCpuCsrAccessVarPtr = &gCpuCsrAccessVar; + GetCpuCsrAccessVar_RC ((PSYSHOST)host, &gCpuCsrAccessVar); + + pCpuCsrAccessVar = &gCpuCsrAccessVar; +#endif // defined + + // + // Identify the PCI Bus/Device/Function number for the access + // + USRA_ZERO_ADDRESS_TYPE(UsraAddress, AddrTypePCIE); + GetBDF(Address, pCpuCsrAccessVar, &UsraAddress.Pcie); + + UsraAddress.Pcie.Offset = (UINT16)((CSR_OFFSET *) &Address->Csr.Offset)->Bits.offset; + UsraAddress.Attribute.HostPtr = Address->Attribute.HostPtr; + + MmCfgBase = GetPcieSegMmcfgBaseAddress(&UsraAddress); + *AlignedAddress = MmCfgBase + (UINTN)(UsraAddress.Attribute.RawData32[0] & 0x0fffffff); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); +#endif + + return 0; +}; + diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf new file mode 100644 index 0000000000..27616a22f4 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf @@ -0,0 +1,88 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CsrToPciePeiLib
+ FILE_GUID = C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CsrToPcieLib
+
+## {C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0}
+##{ 0xc18fb69b, 0xd1a7, 0x4ef0, { 0x98, 0x8d, 0x2a, 0x40, 0xfe, 0x2e, 0x96, 0xb0 } };
+
+
+[Sources]
+ CsrToPcieLib.c
+ ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Protocols]
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Depex]
+
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+
+
+[BuildOptions.Ia32]
+ MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+
+[BuildOptions.X64]
+ MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS)
diff --git a/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.c b/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.c new file mode 100644 index 0000000000..456e5cf3ab --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.c @@ -0,0 +1,311 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <SysHost.h>
+
+#include "PcieAddress.h"
+
+#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
+#include <Library/DebugLib.h>
+#endif
+
+#ifdef _MSC_VER
+#pragma optimize ("",off)
+#endif //_MSC_VER
+//////////////////////////////////////////////////////////////////////////
+//
+// Common Silicon Address Library
+// This Lib provide the way use platform Library instance
+//
+//////////////////////////////////////////////////////////////////////////
+
+PCIE_MMCFG_TABLE_TYPE mMmcfgTable =\
+ {
+ {
+ {'M', 'C', 'F', 'G'}, // Signature
+ 0x00000090, // Length
+ 0x01, // Revision
+ 0x08, // The Maximum number of Segments
+ 0x00FF, // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ...
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+ {{
+ 0, //MMCFG_BASE_ADDRESS, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0000, // Segment 0
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ }}
+};
+//
+// Segment 1 ~ 7
+//
+PCIE_MMCFG_BASE_ADDRESS_TYPE mMmcfgAddr[] = \
+{
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0001, // Segment 1
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0002, // Segment 2
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0003, // Segment 3
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0004, // Segment 4
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0005, // Segment 5
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0006, // Segment 6
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ },
+ {
+ 0x00000000, // Base Address Low
+ 0x00000000, // Base Address High
+ 0x0007, // Segment 7
+ 0x00, // Start Bus
+ 0xFF, // End Bus
+ {0x00,0x00,0x00,0x00} // Reserved
+ }
+};
+
+
+/**
+ This Lib is used for platfor to set platform specific Pcie MMCFG Table
+
+ @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type.
+ @param NumOfSeg: Sumber of Segments in the table.
+
+ @retval <>NULL The function completed successfully.
+ @retval NULL Returen Error
+**/
+UINTN
+SetSocketMmcfgTable (
+ IN UINT8 SocketLastBus[],
+ IN UINT8 SocketFirstBus[],
+ IN UINT8 segmentSocket[],
+ IN UINT32 mmCfgBaseH[],
+ IN UINT32 mmCfgBaseL[],
+ IN UINT8 NumOfSocket
+ )
+{
+#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
+ UINT32 MmcfgTableSize;
+ PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable;
+ UINT8 i, *Dest, *Source;
+
+ union {
+ UINT64 D64;
+ UINT32 D32[2];
+ } Data;
+
+ MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSocket * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE));
+
+ HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
+ ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr));
+
+ Data.D64 = PcdGet64 (PcdPciExpressBaseAddress);
+ mMmcfgTable.MmcfgBase[0].BaseAddressL = Data.D32[0];
+ mMmcfgTable.MmcfgBase[0].BaseAddressH = Data.D32[1];
+
+ //1. copy global variable mMcfgTable to HobMmcfgTable
+ // note that mMmcfgTable only has PCIE_MMCFG_BASE_ADDRESS_TYPE for segment 0 (for socket 0)
+ // need to copy base addresses for other segments corresponding to sockets 1 through NumOfSocket-1
+ Dest = (UINT8*)HobMmcfgTable;
+ Source = (UINT8*)&mMmcfgTable;
+ for(i=0; i<sizeof(PCIE_MMCFG_TABLE_TYPE); i++)
+ {
+ Dest[i] = Source[i];
+ }
+
+ //2. copy remaining segments 1 to NumOfSocket-1 from global array to HobMmcfgTable
+ if(NumOfSocket > 1){
+ Dest = (UINT8*)&HobMmcfgTable->MmcfgBase[1];
+ Source = (UINT8*)&mMmcfgAddr[0];//array of base addresses starting with segment 1 (max segment = 7)
+ for(i = 0; i< (MmcfgTableSize - sizeof(PCIE_MMCFG_TABLE_TYPE)); i++){
+ Dest[i] = Source[i];
+ }
+ }
+
+ HobMmcfgTable->Header.Length = MmcfgTableSize;
+ for(i=0; i<NumOfSocket; i++)
+ {
+ HobMmcfgTable->MmcfgBase[i].StartBus = SocketFirstBus[i];
+ HobMmcfgTable->MmcfgBase[i].EndBus = SocketLastBus[i];
+ HobMmcfgTable->MmcfgBase[i].Segment = segmentSocket[i];
+ HobMmcfgTable->MmcfgBase[i].BaseAddressH = mmCfgBaseH[i];
+ HobMmcfgTable->MmcfgBase[i].BaseAddressL = mmCfgBaseL[i];
+ }
+#endif
+ return 0;
+};
+
+
+/**
+ This Lib is used for platform to set platform specific Pcie MMCFG Table
+
+ @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type.
+ @param NumOfSeg: Sumber of Segments in the table.
+
+ @retval <>NULL The function completed successfully.
+ @retval NULL Returen Error
+**/
+UINTN
+EFIAPI
+SetPcieSegMmcfgTable (
+ IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable,
+ IN UINT32 NumOfSeg
+ )
+{
+#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
+ UINT32 MmcfgTableSize;
+ PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable;
+
+ union {
+ UINT64 D64;
+ UINT32 D32[2];
+ } Data;
+
+ Data.D32[0] = Data.D32[1] = 0;
+ MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSeg * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE));
+
+ HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
+ //ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr));
+
+ //InternalMemCopyMem(HobMmcfgTable, MmcfgTable, PcdGetSize (PcdPcieMmcfgTablePtr));
+ MmcfgTable->Header.Length = MmcfgTableSize;
+ if((MmcfgTable->MmcfgBase[0].BaseAddressL == 0) && (MmcfgTable->MmcfgBase[0].BaseAddressH == 0))
+ {
+ //
+ // The first time default should be the PcdPciExpressBaseAddress
+ //
+ Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ HobMmcfgTable->MmcfgBase[0].BaseAddressL = Data.D32[0];
+ HobMmcfgTable->MmcfgBase[0].BaseAddressH = Data.D32[1];
+ };
+#endif
+ return 0;
+};
+
+
+/**
+ This Lib return PCIE MMCFG Base Address
+
+ @param Address: A pointer of the address of the Common Address Structure for PCIE type.
+ @param Buffer: A pointer of buffer for the value read from platform.
+
+ @retval <>NULL The function completed successfully.
+ @retval NULL Returen Error
+ **/
+
+UINTN
+EFIAPI
+GetPcieSegMmcfgBaseAddress (
+ IN USRA_ADDRESS *Address
+ )
+{
+ UINT32 BaseAddressL=0; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism
+ UINT32 BaseAddressH=0;
+ UINTN SegMmcfgBase;
+
+#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION)
+ PCIE_MMCFG_TABLE_TYPE *MmcfgTable=NULL;
+ union {
+ UINTN D64;
+ UINT32 D32[2];
+ } Data;
+#endif
+#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION)
+ if(Address->Attribute.HostPtr == 0) {
+ MmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
+ if(MmcfgTable->Header.Length != 0)
+ {
+ BaseAddressH = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressH;
+ BaseAddressL = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressL;
+ } else {
+ //
+ // if it is not valid MMCFG pointer, initialize it to use the predefined default MMCFG Table
+ //
+ SetPcieSegMmcfgTable(&mMmcfgTable, PcdGet32 (PcdNumOfPcieSeg));
+ BaseAddressH = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressH;
+ BaseAddressL = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressL;
+
+ if((BaseAddressL == 0) && (BaseAddressH == 0)){
+ Data.D32[0] = Data.D32[1] = 0;
+ Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ BaseAddressL = Data.D32[0];
+ BaseAddressH = Data.D32[1];
+ }
+ }
+ }
+ else
+#endif
+ {
+ BaseAddressH = 0;
+ BaseAddressL = 0;
+ }
+
+ if((BaseAddressL == 0) && (BaseAddressH == 0))
+ {
+
+#if defined(MINIBIOS_BUILD) || defined(KTI_SW_SIMULATION)
+ BaseAddressL = 0x80000000;
+ BaseAddressH = 0;
+#else
+ //
+ // The first time default should be the PcdPciExpressBaseAddress
+ //
+ Data.D32[0] = Data.D32[1] = 0;
+ Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ BaseAddressL = Data.D32[0];
+ BaseAddressH = Data.D32[1];
+#endif
+ }
+ return SegMmcfgBase = BaseAddressL;
+
+};
+
diff --git a/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.inf b/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.inf new file mode 100644 index 0000000000..157e61c860 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/PcieAddressLib/PcieAddressLib.inf @@ -0,0 +1,77 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieAddrLib
+ FILE_GUID = 629E0F0C-073A-475F-BF23-1F39A5D6D1C7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PcieAddrLib
+
+## {629E0F0C-073A-475F-BF23-1F39A5D6D1C7}
+##{ 0x629e0f0c, 0x73a, 0x475f, { 0xbf, 0x23, 0x1f, 0x39, 0xa5, 0xd6, 0xd1, 0xc7 } };
+
+
+[Sources]
+ PcieAddressLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ BaseMemoryLib
+
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+ gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
diff --git a/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c new file mode 100644 index 0000000000..78e648da7b --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c @@ -0,0 +1,818 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <SysHost.h> +#include "CpuPciAccess.h" + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) +#include <Library/DebugLib.h> +#endif + + + + +#ifndef IA32 + +#include "Library/IoLib.h" +#include <Protocol/IioUds.h> +#include <Library/UefiBootServicesTableLib.h> + + +static EFI_IIO_UDS_PROTOCOL *mIioUds; +IIO_UDS *mIioUdsDataPtr; +CPU_CSR_ACCESS_VAR *PCpuCsrAccessVarGlobal = NULL; +#endif +#ifndef IA32 +CPU_CSR_ACCESS_VAR CpuCsrAccessVarGlobal; +#endif + +// +// Disable warning for unsued input parameters +// +#ifdef _MSC_VER +#pragma warning(disable : 4100) +#pragma warning(disable : 4013) +#pragma warning(disable : 4306) +#endif + +// +// PCI function translation table; note that this table doesn't capture the function +// information for all instances of a box. It only captures for the first instance. +// It has to be translated for other instances after the look up is done. +// +STATIC UINT8 FunTbl[MAX_CPU_TYPES][MAX_BOX_TYPES][8] = { + { + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA MISC 0 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA PMA 1 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA CMS 2 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // CHABC 3 + {0, 1, 2, 3, 4, 5, 6, 7 }, // PCU 4 + {0, 1, 2, 3, 4, 5, 6, 7 }, // VCU 5 + {0, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2MEM 6 + {0, 4, 0, 0, 4, 0, 0xFF, 0xFF}, // MC 7 //SKX:Should be {0, 1, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 2, 4, 0, 2, 4, 0xFF, 0xFF}, // MCIO DDRIO 8 //SKX:should be {0, 1, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // KTI 9 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // M3KTI 10 + {2, 6, 2, 2, 6, 2, 0xFF, 0xFF}, // MCDDC 11 //SKX:SHould be {2, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // MCDDC These entries all seem wrong but work + {0, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2UPCIE 12 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO DMI 13 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIE 14 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIENTB 15 + {0, 1, 2, 3, 4, 5, 6, 7 }, // IIOCB 16 + {0, 1, 2, 4, 5, 6, 0xFF, 0xFF}, // IIO VTD 17 + {0, 0, 7, 7, 4, 4, 0xFF, 0xFF}, // IIO_RTO 18 + {0, 1, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // UBOX 19 + }, // SKX +}; + +STATIC UINT8 m2pcieDevTable[MAX_SKX_M2PCIE] = { 22, 21, 22, 23, 21}; + +/** + + Populate CpuCsrAccessVar structure. + + @param host - pointer to the system host root structure + @param CpuCsrAccessVar - pointer to CpuCsrAccessVar structure to be populated + + @retval None + +**/ +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ +#ifndef IA32 + EFI_STATUS Status; +#endif + + if (host != NULL) { + CpuDeadLoop (); + } + +#ifndef IA32 + if (host == NULL) { + if(PCpuCsrAccessVarGlobal == NULL){ //check if 1st time, if yes, then need to update + // Locate the IIO Protocol Interface + Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid, NULL, &mIioUds); + mIioUdsDataPtr = (IIO_UDS *)mIioUds->IioUdsPtr; + //ASSERT_EFI_ERROR (Status); + + PCpuCsrAccessVarGlobal = &CpuCsrAccessVarGlobal; + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType; + CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC; + CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC; + } + + if ((PCpuCsrAccessVarGlobal != NULL) && (CpuCsrAccessVarGlobal.socketPresentBitMap != mIioUdsDataPtr->SystemStatus.socketPresentBitMap)) { + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType; + CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC; + CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC; + } + + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVar->stackPresentBitmap[socket] = CpuCsrAccessVarGlobal.stackPresentBitmap[socket]; + + + CopyMem (&CpuCsrAccessVar->StackBus[socket], &CpuCsrAccessVarGlobal.StackBus[socket], MAX_IIO_STACK); + } + CpuCsrAccessVar->cpuType = CpuCsrAccessVarGlobal.cpuType; + //CpuCsrAccessVar->stepping = CpuCsrAccessVarGlobal.stepping; + CpuCsrAccessVar->socketPresentBitMap = CpuCsrAccessVarGlobal.socketPresentBitMap; + CpuCsrAccessVar->FpgaPresentBitMap = CpuCsrAccessVarGlobal.FpgaPresentBitMap; + //CpuCsrAccessVar->mmCfgBase = CpuCsrAccessVarGlobal.mmCfgBase; + CpuCsrAccessVar->numChPerMC = CpuCsrAccessVarGlobal.numChPerMC; + CpuCsrAccessVar->maxCh = CpuCsrAccessVarGlobal.maxCh; + //CpuCsrAccessVar->maxIMC = CpuCsrAccessVarGlobal.maxIMC; + } +#endif +} + +/** + + Stall execution after internal assertion fails + + @param haltOnError - 1 stalls in infinite loop; 0 returns to caller + + @retval None + +**/ +VOID RcDeadLoop ( + UINT8 haltOnError + ) +{ + // + // Prevent from optimizing out + // + while (*(volatile UINT8 *) &haltOnError); +} + +/** + + CsrAccess specific print to serial output + + @param host - Pointer to the system host (root) structure + @param Format - string format + + @retval N/A + +**/ +VOID +CpuCsrAccessError ( + PSYSHOST host, + char* Format, + ... + ) +{ + UINT8 haltOnError; +#ifdef SERIAL_DBG_MSG +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + UINT32 *pData32; +#endif + va_list Marker; + va_start (Marker, Format); +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + if (host != NULL) { + pData32 = (UINT32 *)Marker; + if( (*pData32 & 0xFFFFFF00) == 0xFFFFFF00){ // check if input is one byte only + *pData32 = *pData32 & 0x000000FF; + } if( (*pData32 & 0xFFFF0000) == 0xFFFF0000){ // check if input is word only + *pData32 = *pData32 & 0x0000FFFF; + } + DEBUG (( + DEBUG_ERROR, Format, *pData32 + )); + } +#else + if (host != NULL) { + rcVprintf (host, Format, Marker); + } +#endif + va_end (Marker); +#endif + haltOnError = 1; + RcDeadLoop (haltOnError); + + return; +} + +/** + + Returns the CPU Index for MC func tbl lookup based on CPU type and CPU sub type. + This index will be used for MC box instance -> function mapping look-up + + @param host - Pointer to the system host (root) structure + + @retval Index for CPU type + +**/ +STATIC +UINT8 +GetCpuIndex ( + PSYSHOST host + ) +{ + UINT8 cpuIndex = 0xFF; + + cpuIndex = 0; + return cpuIndex; +} + +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to the system host (root) structure + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + + @retval PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Bus = 0; + UINT8 TempStack = 0; + + + + // Make sure SocId or Fpga is valid + if ((!((CpuCsrAccessVar->socketPresentBitMap & (1 << SocId)) && (BoxType != BOX_FPGA)))) { + if ((!((CpuCsrAccessVar->FpgaPresentBitMap & (1 << SocId)) && (BoxType == BOX_FPGA)))) { + CpuCsrAccessError (host, "\nInvalid Socket Id %d. \n", SocId); + } + } + + // + // Each socket is assigned multiple buses + // Check the box type and return the appropriate bus number. + // + if ((BoxType == BOX_MC) || + (BoxType == BOX_MCDDC) || + (BoxType == BOX_MCIO) || + (BoxType == BOX_M2MEM)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK1]; + + } else if (BoxType == BOX_UBOX) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if ((BoxType == BOX_IIO_PCIE_DMI) || + (BoxType == BOX_IIO_CB)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if (BoxType == BOX_IIO_PCIE) { + // + // IIO_PCIE is used to access all pcie ports in all stacks + // + if (BoxInst == 0) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst); + } + } + } else if (BoxType == BOX_IIO_VTD) { + TempStack = IIO_CSTACK + BoxInst; + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_VTD BoxInstance %d. \n", BoxInst); + } + } else if (BoxType == BOX_IIO_PCIE_NTB) { + if (BoxInst > 0) { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst); + } + } else if (BoxType == BOX_IIO_RTO) { + if (FuncBlk == IIO_RTO) { + // + // IIO_RTO is used to access all pcie ports in all stacks same as iio_pcie + // + if (BoxInst == 0) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst); + } + } + } else if ((FuncBlk == IIO_RTO_GLOBAL) || (FuncBlk == IIO_RTO_VTD)) { + // + // IIO_RTO_GLOBAL and IIO_RTO_VTD maps 1 instance per c/p/m stack + // + if ((IIO_CSTACK + BoxInst) < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK + BoxInst]; + } + } else if ((FuncBlk == IIO_RTO_VTD_DMI) || + (FuncBlk == IIO_RTO_DMI) || + (FuncBlk == IIO_RTO_GLOBAL_DMI)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + CpuCsrAccessError (host, "\nInvalid BoxType %d, Functional block %d. \n", BoxType, FuncBlk); + } + } else if ((BoxType == BOX_CHA_MISC) || + (BoxType == BOX_CHA_PMA) || + (BoxType == BOX_CHA_CMS) || + (BoxType == BOX_CHABC) || + (BoxType == BOX_PCU) || + (BoxType == BOX_VCU)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK0]; + } else if ((BoxType == BOX_M2UPCIE) || + (BoxType == BOX_KTI) || + (BoxType == BOX_M3KTI)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK2]; + } else if (BoxType == BOX_FPGA) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + + } else { + // Error + CpuCsrAccessError (host, "\nInvalid BoxType %d. \n", BoxType); + } + + return Bus; +} + +/** + + Indetifies the device number for given Box Type & Box Instance + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Dev = 0; + UINT8 CpuType, NumChPerMC; + + CpuType = CpuCsrAccessVar->cpuType; + NumChPerMC = CpuCsrAccessVar->numChPerMC; + + + // + // Translate the Box Type & Instance into PCI Device number. + // + switch (BoxType) { + case BOX_MC: + case BOX_MCDDC: + if (CpuType == CPU_SKX) { + switch (BoxInst) { + case 0: + case 1: + Dev = 10; + break; + case 2: + Dev = 11; + break; + case 3: + case 4: + Dev = 12; + break; + case 5: + Dev = 13; + break; + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_MCIO: + if (CpuType == CPU_SKX) { + Dev = 22 + (BoxInst / NumChPerMC); + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2MEM: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_M2MEM)) { + Dev = 8 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid M2MEM Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_MISC: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 8; + } else if (BoxInst < 16) { + Dev = 9; + } else if (BoxInst < 24) { + Dev = 10; + } else if (BoxInst < 28) { + Dev = 11; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_PMA: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 14; + } else if (BoxInst < 16) { + Dev = 15; + } else if (BoxInst < 24) { + Dev = 16; + } else if (BoxInst < 28) { + Dev = 17; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_CMS: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 20; + } else if (BoxInst < 16) { + Dev = 21; + } else if (BoxInst < 24) { + Dev = 22; + } else if (BoxInst < 28) { + Dev = 23; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHABC: + if ((CpuType == CPU_SKX) && (BoxInst == 0)) { + Dev = 29; + } else { + CpuCsrAccessError (host, "\nInvalid CHABC Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_PCU: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_PCU)) { + Dev = 30; + } else { + CpuCsrAccessError (host, "\nInvalid PCU Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_VCU: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_VCU)) { + Dev = 31; + } else { + CpuCsrAccessError (host, "\nInvalid VCU Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_KTI: + /* + Dev # KTI(phy,logic)# + 14 0 0 + 15 1 1 + 16 2 2 + */ + if (CpuType == CPU_SKX) { + if (BoxInst < MAX_SKX_KTIAGENT ) { + Dev = 14 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + if (CpuType == CPU_SKX) { + if (BoxInst < 2 ) { + Dev = 18; + } else { + CpuCsrAccessError (host, "\nInvalid Box instance.\n"); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2UPCIE: + if (CpuType == CPU_SKX) { + if (BoxInst < MAX_SKX_M2PCIE) { + Dev = m2pcieDevTable[BoxInst]; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_IIO_PCIE_DMI: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO)) { + Dev = 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE DMI Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_PCIE: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_PCIE)) { + if (BoxInst == 0) { + // Cstack + Dev = 0; + } else { + // M/Pstacks + Dev = 0 + ((BoxInst-1) % 4); + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_PCIE_NTB: + if ((CpuType == CPU_SKX)) { + Dev = 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_CB: + if ((CpuType == CPU_SKX)) { + Dev = 4; + } else { + CpuCsrAccessError (host, "\nInvalid IIO CB Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_VTD: + if ((CpuType == CPU_SKX)) { + Dev = 5; + } else { + CpuCsrAccessError (host, "\nInvalid IIO VTD Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_RTO: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_RTO)) { + Dev = 7; + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_UBOX: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_UBOX)) { + Dev = 8; + } else { + CpuCsrAccessError (host, "\nInvalid Ubox Instance Number %d. \n", BoxInst); + //Note: the fatal error function writes to UBOX CSR and recurses forever (until stack is gone). + } + break; + case BOX_FPGA: + if ((CpuType == CPU_SKX) && (BoxInst == 0)) { + Dev = 16; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Instance number %d. \n", BoxInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Dev > 31) { + CpuCsrAccessError (host, "\nInvalid Device %d accessed for Box Type %d and Box Instance %d. \n", Dev, BoxType, BoxInst); + } + return Dev; +} + +/** + + Indetifies the function number for given BoxType, BoxInst & Functional Block + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Fun = 0; + UINT8 CpuIndex, CpuType, NumChPerMC; + + CpuType = CpuCsrAccessVar->cpuType; + NumChPerMC = CpuCsrAccessVar->numChPerMC; + + // Get the CPU type, sub type + CpuIndex = GetCpuIndex(host); + + // + // Translate the Box Type & Functional Block into PCI function number. Note that the box type & instance number + // passed to this routine are assumed to be valid; here we only need to validate if the function number is correct + // after the look up is done. + // + + switch (BoxType) { + + case BOX_MC: + + if (FuncBlk == 0 || FuncBlk == 1) { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } else { + Fun = 4; + } + break; + + case BOX_MCDDC: + + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + break; + + case BOX_MCIO: + + if (FuncBlk == 2) { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + 3; + + } else { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } + break; + + case BOX_CHA_MISC: + case BOX_CHA_PMA: + case BOX_CHA_CMS: + // + // For Cha, no table look up is needed; the function number can be obtained from instance number. + // + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + Fun = (BoxInst % 8); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst == 1) { + Fun = Fun + 4; + } + break; + + case BOX_M2MEM: + case BOX_CHABC: + case BOX_PCU: + case BOX_VCU: + case BOX_IIO_PCIE_DMI: + case BOX_IIO_PCIE: + case BOX_IIO_PCIE_NTB: + case BOX_IIO_CB: + case BOX_IIO_VTD: + case BOX_UBOX: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + break; + + case BOX_M2UPCIE: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst == 2 || BoxInst == 4) { // M2PCIE2 & M2MCP1 + Fun = Fun + 4; + } + break; + + case BOX_KTI: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst >=9 ) { + Fun = Fun + 4; + } + break; + + case BOX_IIO_RTO: + if ((BoxInst < MAX_ALL_IIO_RTO) && (FunTbl[CpuType][BoxType][FuncBlk] != 0xFF)) { + if (FuncBlk == IIO_RTO) { + if (BoxInst == 0) { + // Cstack + Fun = 0; + } else { + // M/Pstacks + Fun = 0 + ((BoxInst-1) % 4); + } + } else { + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_FPGA: + if (BoxInst == 0) { + Fun = 0; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Box Instance Number %d. \n", BoxInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Fun > 7) { + CpuCsrAccessError (host, "\nInvalid Functional Block %d accessed for CPUType %d CPUIndex %d Box Type %d and Box Instance %d. \n", + FuncBlk, CpuType, CpuIndex, BoxType, BoxInst); + } + + return Fun; +} + + diff --git a/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..484949006f --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h @@ -0,0 +1,58 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include <CsrToPcieAddress.h> +#include <CpuPciAccessCommon.h> + + +typedef enum { + BUS_CLASS = 0, + DEVICE_CLASS = 1, + FUNCTION_CLASS = 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h new file mode 100644 index 0000000000..df7bb8954d --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h @@ -0,0 +1,123 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_PCI_ACCESS_H_ +#define _CPU_PCI_ACCESS_H_ + +#include "DataTypes.h" + + + +// +// CPU Types; this needs to be contiguous to assist in table look up +// +#define MAX_CPU_TYPES 1 + +// +// CPU Index for MC function look-up +// +#define MAX_CPU_INDEX 1 + + +// +// Box Types; this needs to be contiguous to assist in table look up +// +#define BOX_CHA_MISC 0 +#define BOX_CHA_PMA 1 +#define BOX_CHA_CMS 2 +#define BOX_CHABC 3 +#define BOX_PCU 4 +#define BOX_VCU 5 +#define BOX_M2MEM 6 +#define BOX_MC 7 +#define BOX_MCIO 8 +#define BOX_KTI 9 +#define BOX_M3KTI 10 +#define BOX_MCDDC 11 +#define BOX_M2UPCIE 12 +#define BOX_IIO_PCIE_DMI 13 +#define BOX_IIO_PCIE 14 +#define BOX_IIO_PCIE_NTB 15 +#define BOX_IIO_CB 16 +#define BOX_IIO_VTD 17 +#define BOX_IIO_RTO 18 +#define BOX_UBOX 19 +#define BOX_FPGA 20 +#define MAX_BOX_TYPES 21 + + +// +// Maximum Number of Instances supported by each box type. Note that if the number of instances +// are same for all supported CPUs, then we will have only one #define here (i.e MAX_ALL_XXXXX) +// +#define MAX_SKX_CHA 28 + +#define MAX_SKX_M2PCIE 5 + +#define MAX_ALL_CBOBC 1 + +#define MAX_SKX_M3KTI 2 + +#define MAX_SKX_KTIAGENT 3 + +#define MAX_SKX_M2MEM 2 + +#define MAX_ALL_M2PCIE 1 +#define MAX_ALL_UBOX 1 +#define MAX_ALL_IIO 4 +#define MAX_ALL_PCU 1 +#define MAX_ALL_VCU 1 + +#define MAX_ALL_IIO_CB 1 // 1 instance per CB function block +#define MAX_ALL_IIO_PCIE_DMI 1 // 0:0:0 +#define MAX_ALL_IIO_PCIE_NTB 3 // 4 instances in PCIE_NTB (0:3:0/1/2/3) +#define MAX_ALL_IIO_RTO 21 // 4 instances per M/PSTACK + 1 Cstack +#define MAX_ALL_IIO_RTO_DMI 4 // 4 instances in C stack +#define MAX_ALL_IIO_RTO_VTD 6 // 6 instances in IIO_RTO block across C/P/MCP stacks +#define MAX_ALL_IIO_RTO_VTD_DMI 1 // 1 instances in IIO_RTO block across C stack +#define MAX_ALL_IIO_PCIE 21 // 4 instances per M/PSTACK + 1 Cstack + + +#define IIO_RTO 0 +#define IIO_RTO_DMI 1 +#define IIO_RTO_GLOBAL 2 +#define IIO_RTO_GLOBAL_DMI 3 +#define IIO_RTO_VTD 4 +#define IIO_RTO_VTD_DMI 5 + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files. +// +typedef union { + struct { + UINT32 offset : 12; // bits <11:0> + UINT32 size : 3; // bits <14:12> + UINT32 pseudo : 1; // bit <15> + UINT32 funcblk : 8; // bits <23:16> + UINT32 boxtype : 8; // bits <31:24> + } Bits; + UINT32 Data; +} CSR_OFFSET; + + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files. +// +#define PCI_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xff) | (((Function) & 0x07) << 8) | (((Device) & 0x1f) << 11) | (((Bus) & 0xff) << 16)) +#define PCIE_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +#endif // _CPU_PCI_ACCESS_H_ diff --git a/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h new file mode 100644 index 0000000000..2b8c367f5e --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_PCI_ACCESS_COMMON_H_ +#define _CPU_PCI_ACCESS_COMMON_H_ + +#include <SysHost.h>
+ +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the device number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the function number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_PCI_ACCESS_COMMON_H_ + + diff --git a/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h new file mode 100644 index 0000000000..df4d9a2ecf --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h @@ -0,0 +1,8 @@ +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:20] = Major revision number +// [19:12] = Minor revision number +// [11:0] = Release Candidate number / Reserved +#define RC_REVISION 0x15352001 + diff --git a/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec new file mode 100644 index 0000000000..e773767a31 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec @@ -0,0 +1,607 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = IA32FamilyCpuPkg
+ PACKAGE_GUID = 7dbe088f-2e1a-475c-b006-55632c2a5489
+ PACKAGE_VERSION = 0.5
+
+[Includes]
+ Include
+
+[LibraryClasses]
+ CpuConfigLib|Include/Library/CpuConfigLib.h
+ CpuOnlyResetLib|Include/Library/CpuOnlyResetLib.h
+ Socket775LgaLib|Include/Library/SocketLga775Lib.h
+ SocketLga1156Lib|Include/Library/SocketLga1156Lib.h
+
+[Guids]
+ ## Include/Guid/HtBistHob.h
+ gEfiHtBistHobGuid = { 0xBE644001, 0xE7D4, 0x48B1, { 0xB0, 0x96, 0x8B, 0xA0, 0x47, 0xBC, 0x7A, 0xE7 }}
+ ## Include/Guid/IA32FamilyCpuPkgTokenSpace.h
+ gEfiCpuTokenSpaceGuid = { 0x2ADA836D, 0x0A3D, 0x43D6, { 0xA2, 0x5A, 0x38, 0x45, 0xCA, 0xD2, 0xD4, 0x00 }}
+
+[Ppis]
+ ## Include/Ppi/Cache.h
+ gPeiCachePpiGuid = { 0xC153205A, 0xE898, 0x4C24, { 0x86, 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2 }}
+
+[Protocols]
+ gSmmCpuSyncProtocolGuid = { 0xd5950985, 0x8be3, 0x4b1c, { 0xb6, 0x3f, 0x95, 0xd1, 0x5a, 0xb3, 0xb6, 0x5f }}
+ gSmmCpuSync2ProtocolGuid = { 0x9db72e22, 0x9262, 0x4a18, { 0x8f, 0xe0, 0x85, 0xe0, 0x3d, 0xfa, 0x96, 0x73 }}
+ gIntelCpuPcdsSetDoneProtocolGuid = { 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd, 0x78 }}
+
+#
+# [Error.gEfiCpuTokenSpaceGuid]
+# 0x80000001 | Invalid value provided.
+#
+
+[PcdsFeatureFlag]
+ ## Indicates if the support for Intel(R) Pentium(R) 4 (90nm) processor with HT
+ # Technology, Intel(R) Celeron D Processor, Intel(R) Pentium(R) 4 Processor
+ # Extreme Edition Supporting HT Technology Processor, and Mobile Intel(R)
+ # Pentium(R) 4 Processor supporting HT Technology is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Processor Family.
+ gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|TRUE|BOOLEAN|0x00000001
+ ## Indicates if the support for Intel(R) Pentium(R) 4 (65nm) processor supporting HT Technology and Intel(R)
+ # Celeron D Processor is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Pentium(R) 4 (65nm) processor supporting HT Technology and Intel(R) Celeron D Processor Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|TRUE|BOOLEAN|0x00000002
+ ## Indicates if the support for Intel(R) Core(TM)2 Processor, Intel(R) Celeron(R) Processor,
+ # Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor is included in
+ # the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Core(TM)2 Processor, Intel(R) Celeron(R) Processor, Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|TRUE|BOOLEAN|0x00000003
+ ## Indicates if the support for Intel(R) Atom(TM) E6xx processor family is
+ # included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Intel(R) Atom(TM) E6xx processor family is included in the CPU MP driver.<BR>
+ # FALSE - The support for Intel(R) Atom(TM) E6xx processor family is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Atom(TM) E6xx processor family Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuTunnelCreekFamilyFlag|FALSE|BOOLEAN|0x10000033
+ ## Indicates if the support for Intel(R) Xeon(R) (45nm QPI) processor family is included
+ # in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)is included in the CPU MP driver.<BR>
+ # FALSE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor family (45nm QPI) Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|TRUE|BOOLEAN|0x10000019
+ ## Indicates if the support for Intel(R) Core(TM) 2xxx processor family is
+ # included in the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R) Processor, Intel(R) Core(TM) Processor, Intel(R) Celeron(R) Processor Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000030
+ ## Indicates if the support for Intel(R) Atom(TM) C2xxx processor family is
+ # included in the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Atom(TM) C2xxx processor family Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuSilvermontFamilyFlag|FALSE|BOOLEAN|0x10000034
+ ## Indicates if the support for Intel(R) Core(TM) 3xxx processor family is
+ # included in the CPU MP driver.<BR><BR>
+ # TRUE - The support is included in the CPU MP driver.<BR>
+ # FALSE - The support is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R) Processor, Intel(R) Core(TM) Processor Support.
+ gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031
+ ## Indicates if the support for 4th Generation Intel(R) Core(TM) processor family is included in the CPU
+ # MP driver.<BR><BR>
+ # TRUE - The support for 4th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.<BR>
+ # FALSE - The support for 4th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver 4th Generation Intel(R) Core(TM) processor support.
+ gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE|BOOLEAN|0x10000032
+ ## Indicates if the support for 5th Generation Intel(R) Core(TM) processor family is included in the CPU
+ # MP driver.<BR><BR>
+ # TRUE - The support for 5th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.<BR>
+ # FALSE - The support for 5th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver 5th Generation Intel(R) Core(TM) processor support.
+ gEfiCpuTokenSpaceGuid.PcdCpuBroadwellFamilyFlag|FALSE|BOOLEAN|0x10000035
+ ## Indicates if the support for 6th Generation Intel(R) Core(TM) processor family is included in the CPU
+ # MP driver.<BR><BR>
+ # TRUE - The support for 6th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.<BR>
+ # FALSE - The support for 6th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver 6th Generation Intel(R) Core(TM) processor support.
+ gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|FALSE|BOOLEAN|0x10000036
+ ## Indicates if the support for 16nm Intel(R) Atom(TM) processor family is included in the CPU
+ # MP driver.<BR><BR>
+ # TRUE - The support for 16nm Intel(R) Atom(TM) processor family is included in the CPU MP driver.<BR>
+ # FALSE - The support for 16nm Intel(R) Atom(TM) processor family is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver 16nm Intel(R) Atom(TM) processor family support.
+ gEfiCpuTokenSpaceGuid.PcdCpuGoldmontFamilyFlag|FALSE|BOOLEAN|0x10000037
+ ## Indicates if the support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is included in the CPU MP driver.<BR>
+ # FALSE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver 14nm Intel(R) Xeon Phi(TM) Coprocessor family support.
+ gEfiCpuTokenSpaceGuid.PcdCpuKnightsLandingFamilyFlag|FALSE|BOOLEAN|0x10000038
+ ## Indicates if the support for thermal management features is included in the CPU MP driver.
+ # Thermal management features include TM1, TM2 and bi-directional PROCHOT.<BR><BR>
+ # TRUE - The support for thermal management features is included in the CPU MP driver.<BR>
+ # FALSE - The support for thermal management features is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver thermal management features support.
+ gEfiCpuTokenSpaceGuid.PcdCpuThermalManagementFlag|TRUE|BOOLEAN|0x10000001
+ ## Indicates if the support for enhanced C-State feature (including C1e) is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for enhanced C-State feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for enhanced C-State feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver enhanced C-State feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuEnhancedCStateFlag|TRUE|BOOLEAN|0x10000006
+ ## Indicates if the support for Limit CPUID Maxval feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Limit CPUID Maxval feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Limit CPUID Maxval feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Limit CPUID Maxval feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMaxCpuIDValueLimitFlag|TRUE|BOOLEAN|0x10000008
+ ## Indicates if the support for CPU microcode update is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for CPU microcode update is included in the CPU MP driver.<BR>
+ # FALSE - The support for CPU microcode update is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver CPU microcode update support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMicrocodeUpdateFlag|TRUE|BOOLEAN|0x1000000D
+ ## Indicates if the support for Machine Check feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Machine Check feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Machine Check feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Machine Check feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMachineCheckFlag|TRUE|BOOLEAN|0x1000000E
+ ## Indicates if the support for Select Least Featured Processor as BSP feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Select Least Featured Processor as BSP feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Select Least Featured Processor as BSP feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Select Least Featured Processor as BSP feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F
+ ## Indicates if BSP election in SMM will be enabled.
+ # If enabled, a BSP will be dynamically elected among all processors in each SMI.
+ # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
+ # TRUE - BSP election in SMM will be enabled.<BR>
+ # FALSE - BSP election in SMM will be disabled.<BR>
+ # @Prompt Enable BSP election in SMM.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
+ ## Indicates if the support for Enhanced Intel Speed Step (EIST) feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for EIST feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for EIST feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver EIST feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuEistFlag|TRUE|BOOLEAN|0x10000004
+ ## Indicates if the support for VT-x and TXT initialization is included in the CPU MP driver.
+ # VT-x - Intel Virtualization Technology for IA-32 Intel Architecture.
+ # TXT - Intel(R) Trusted Execution Technology.<BR><BR>
+ # TRUE - The support for VT and LT initialization is included in the CPU MP driver.<BR>
+ # FALSE - The support for VT and LT initialization is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver VT-x and TXT initialization support.
+ gEfiCpuTokenSpaceGuid.PcdCpuVtLtFlag|TRUE|BOOLEAN|0x10000007
+ ## Indicates if the support for Execute Disable Bit feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Execute Disable Bit feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Execute Disable Bit feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Execute Disable Bit feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuExecuteDisableBitFlag|TRUE|BOOLEAN|0x10000009
+ ## Indicates if the support for Fast Strings for REP MOVS and REP STOS feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Fast Strings feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Fast Strings feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Fast Strings feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuFastStringFlag|TRUE|BOOLEAN|0x10000012
+ ## Indicates if the support for Hardware Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Hardware Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Hardware Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Hardware Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuHardwarePrefetcherFlag|TRUE|BOOLEAN|0x10000013
+ ## Indicates if the support for Adjacent Cache Line Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Adjacent Cache Line Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Adjacent Cache Line Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Adjacent Cache Line Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuAdjacentCacheLinePrefetchFlag|TRUE|BOOLEAN|0x10000014
+ ## Indicates if the support for DCU Streamer Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for DCU Streamer Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for DCU Streamer Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver DCU Streamer Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuDcuPrefetcherFlag|TRUE|BOOLEAN|0x10000015
+ ## Indicates if the support for DCU IP Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for DCU IP Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for DCU IP Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver DCU IP Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuIpPrefetcherFlag|TRUE|BOOLEAN|0x10000016
+ ## Indicates if the support for MLC Streamer Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for MLC Streamer Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for MLC Streamer Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver MLC Streamer Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMlcStreamerPrefetcherFlag|TRUE|BOOLEAN|0x1000001D
+ ## Indicates if the support for MLC Spatial Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for MLC Spatial Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for MLC Spatial Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver MLC Spatial Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMlcSpatialPrefetcherFlag|TRUE|BOOLEAN|0x1000001E
+ ## Indicates if the support for L2 Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for L2 Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for L2 Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver L2 Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuL2PrefetcherFlag|TRUE|BOOLEAN|0x1000002B
+ ## Indicates if the support for L1 Data Prefetcher feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for L1 Data Prefetcher feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for L1 Data Prefetcher feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver L1 Data Prefetcher feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuL1DataPrefetcherFlag|TRUE|BOOLEAN|0x1000002C
+ ## Indicates if the support for Pending Break Enable feature is included in the CPU MP driver.
+ # This feature uses the FERR#/PBE# pin when the processor is in the stop-clock state to signal the processor
+ # that an interrupt is pending and that the processor should return to normal operation to handle the interrupt.<BR><BR>
+ # TRUE - The support for Pending Break Enable feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Pending Break Enable feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Pending Break Enable feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuFerrSignalBreakFlag|TRUE|BOOLEAN|0x10000017
+ ## Indicates if the support for Platform Enviroment Control Interface (PECI) feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for PECI feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for PECI feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Platform Environment Control Interface (PECI) feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuPeciFlag|TRUE|BOOLEAN|0x10000018
+ ## Indicates if the support for MONITOR (MONITOR and MWAIT instructions) feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for MONITOR feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for MONITOR feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver MONITOR feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuMonitorMwaitFlag|TRUE|BOOLEAN|0x1000001F
+ ## Indicates if the support for Three Strike Counter feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Three Strike Counter feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Three Strike Counter feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Three Strike Counter feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuThreeStrikeCounterFlag|TRUE|BOOLEAN|0x10000020
+ ## Indicates if the support for CPU Energy Efficiency Policy feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for CPU Energy Efficiency Policy feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for CPU Energy Efficiency Policy feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver CPU Energy Efficiency Policy feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuEnergyPerformanceBiasFlag|TRUE|BOOLEAN|0x10000021
+ ## Indicates if the support for T-State feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for T-State feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for T-State feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver T-State feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuTStateFlag|TRUE|BOOLEAN|0x10000022
+ ## Indicates if the support for Advanced Encryption Standard (AES) feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for AES feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for AES feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Advanced Encryption Standard (AES) feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuAesFlag|TRUE|BOOLEAN|0x10000023
+ ## Indicates if the support for Direct Cache Access (DCA) feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for DCA feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for DCA feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Direct Cache Access (DCA) feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuDcaFlag|TRUE|BOOLEAN|0x10000024
+ ## Indicates if the support for C-State feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for C-State feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for C-State feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver C-State feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuCStateFlag|TRUE|BOOLEAN|0x10000025
+ ## Indicates if the support for x2APIC mode is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for x2APIC mode is included in the CPU MP driver.<BR>
+ # FALSE - The support for x2APIC mode is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver x2APIC mode support.
+ gEfiCpuTokenSpaceGuid.PcdCpuX2ApicFlag|TRUE|BOOLEAN|0x10000026
+ ## Indicates if the support for APIC TPR Update message feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for APIC TPR Update message feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for APIC TPR Update message feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver APIC TPR Update message feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuApicTprUpdateMessageFlag|TRUE|BOOLEAN|0x10000027
+ ## Indicates if the support for Data Cache Unit (DCU) mode selection feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Data Cache Unit (DCU) mode selection feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Data Cache Unit (DCU) mode selection feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver DCU mode selection feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuDcuModeSelectionFlag|TRUE|BOOLEAN|0x10000028
+ ## Indicates if the support for A20M Disable feature is included in the CPU MP driver.
+ # When the A20M #pin (Address 20 Mask) is asserted, the processor will mask physical address bit 20 (A20#).
+ # The A20M Disable can disable this legacy A20M feature.<BR><BR>
+ # TRUE - The support for A20M Disable feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for A20M Disable feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver A20M Disable feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|TRUE|BOOLEAN|0x1000001A
+ ## Indicates if the support for CPU socket ID re-assignment feature is included in the CPU MP driver.
+ # This feature allows re-assignment of CPU socket ID over hardware power-on default value, which in turn
+ # changes the APIC ID of logical processors in the CPU socket.<BR><BR>
+ # TRUE - The support for CPU socket ID re-assignment feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for CPU socket ID re-assignment feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver CPU socket ID re-assignment feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|FALSE|BOOLEAN|0x10000029
+ ## Indicates if SMM Debug will be enabled.
+ # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
+ # TRUE - SMM Debug will be enabled.<BR>
+ # FALSE - SMM Debug will be disabled.<BR>
+ # @Prompt Enable SMM Debug.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
+ ## Indicates if SMM Stack Guard will be enabled.
+ # If enabled, stack overflow in SMM can be caught which eases debugging.<BR><BR>
+ # TRUE - SMM Stack Guard will be enabled.<BR>
+ # FALSE - SMM Stack Guard will be disabled.<BR>
+ # @Prompt Enable SMM Stack Guard.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C
+ ## Indicates if SMM Startup AP in a blocking fashion.
+ # TRUE - SMM Startup AP in a blocking fashion.<BR>
+ # FALSE - SMM Startup AP in a non-blocking fashion.<BR>
+ # @Prompt SMM Startup AP in a blocking fashion.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
+ ## Indicates if SMM Profile will be enabled.
+ # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
+ # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
+ # TRUE - SMM Profile will be enabled.<BR>
+ # FALSE - SMM Profile will be disabled.<BR>
+ # @Prompt Enable SMM Profile.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
+ ## Indicates if the SMM profile log buffer is a ring buffer.
+ # If disabled, no additional log can be done when the buffer is full.<BR><BR>
+ # TRUE - the SMM profile log buffer is a ring buffer.<BR>
+ # FALSE - the SMM profile log buffer is a normal buffer.<BR>
+ # @Prompt The SMM profile log buffer is a ring buffer.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
+ ## Indicates if SMM MP sync data resides in un-cached RAM.<BR><BR>
+ # TRUE - SMM MP sync data will be resided in un-cached RAM.<BR>
+ # FALSE - SMM MP sync data will be resided in cached RAM.<BR>
+ # @Prompt SMM MP sync data resides in un-cached RAM.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUncacheCpuSyncData|FALSE|BOOLEAN|0x3213210D
+ ## Indidates if CPU SMM hot-plug will be enabled.<BR><BR>
+ # TRUE - SMM CPU hot-plug will be enabled.<BR>
+ # FALSE - SMM CPU hot-plug will be disabled.<BR>
+ # @Prompt SMM CPU hot-plug.
+ gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
+ ## Indidates if lock SMM Feature Control MSR.<BR><BR>
+ # TRUE - SMM Feature Control MSR will be locked.<BR>
+ # FALSE - SMM Feature Control MSR will not be locked.<BR>
+ # @Prompt Lock SMM Feature Control MSR.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
+ ## Whether to set the IA untrusted lock feature of SAI-capable processors.
+ # TRUE - IA untrusted lock feature is supported.<BR>
+ # FALSE - IA untrusted lock feature is not supported.<BR>
+ # @Prompt Enabled the IA untrusted lock feature.
+ gEfiCpuTokenSpaceGuid.PcdCpuEnableIaUntrustedModeFlag|TRUE|BOOLEAN|0x3213210E
+ ## Indicates if the support for Peci Downstream Write feature is included in the CPU MP driver.<BR><BR>
+ # TRUE - The support for Peci Downstream Write feature is included in the CPU MP driver.<BR>
+ # FALSE - The support for Peci Downstream Write feature is not included in the CPU MP driver.<BR>
+ # @Prompt CPU MP driver Peci Downstream Write feature support.
+ gEfiCpuTokenSpaceGuid.PcdCpuPeciDownstreamWriteFlag|TRUE|BOOLEAN|0x1000002E
+
+ gEfiCpuTokenSpaceGuid.PcdCpuPCIeDownStreamPECIFlag|TRUE|BOOLEAN|0x1000002F
+
+[PcdsFixedAtBuild]
+ ## Specifies maximum number of PPIs provided by SecCore.
+ # @Prompt Maximum number of PPIs provided by SecCore.
+ gEfiCpuTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x10001010
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+ ## Specifies maximum number of processors supported by the platform.
+ # @Prompt Maximum number of processors supported by the platform.
+ gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x30000002
+ ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
+ # @Prompt AP synchronization timeout value in SMM.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
+ ## Specifies stack size in bytes for each processor in SMM.
+ # @Prompt Processor stack size in SMM.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
+ ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
+ # @Prompt SMM profile data buffer size.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
+ ## Specifies the temporary RAM base address.
+ # @Prompt Temporary RAM base address.
+ gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x10001001
+ ## Specifies the temporary RAM size in bytes.
+ # @Prompt Temporary RAM size.
+ gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x10001002
+ ## Maximum number of processors in SEC (Not used).
+ # @Prompt Maximum number of processors in SEC.
+ gEfiCpuTokenSpaceGuid.PcdSecMaximumNumberOfProcessors|1|UINT32|0x10001000
+ ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
+ # @Prompt Stack size in the temporary RAM.
+ gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
+ ## Indidates if SMM Code Access Check is enabled.
+ # If enabled, the SMM handler cannot execut the code outside ranges defined by SMRR/SMRR2.
+ # This PCD is suggested to TRUE in production image.<BR><BR>
+ # TRUE - SMM Code Access Check will be enabled.<BR>
+ # FALSE - SMM Code Access Check will be disabled.<BR>
+ # @Prompt SMM Code Access Check.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+ ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
+ # @Prompt Timeout for the BSP to detect all APs for the first time.
+ gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x30000001
+ ## Specifies stack size in bytes for each AP.
+ # @Prompt AP stack size.
+ gEfiCpuTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x30000003
+ ## Specifies user's desired settings for enabling/disabling processor features, each bit corresponding to a specific feature.
+ # @Prompt User settings for enabling/disabling processor features.
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0|UINT32|0x40000001
+ ## Specifies desired settings for enabling/disabling processor features, each bit corresponding to a specific feature.
+ # @Prompt User extension1 settings for enabling/disabling processor features.
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0|UINT32|0x40000006
+ ## Indicates if the platform supports high power load line.
+ # @Prompt The platform supports high power load line.
+ gEfiCpuTokenSpaceGuid.PcdPlatformHighPowerLoadLineSupport|TRUE|BOOLEAN|0x60000001
+ ## Platform dynamic Vid support (not used).
+ # @Prompt Platform dynamic Vid support.
+ gEfiCpuTokenSpaceGuid.PcdPlatformDynamicVidSupport|TRUE|BOOLEAN|0x60000002
+ ## Indicates the platform type: desktop, mobile or server.<BR><BR>
+ # 0 - desktop<BR>
+ # 1 - mobile<BR>
+ # 2 - server<BR>
+ # @Prompt Platform type.
+ # @ValidRange 0x80000001 | 0 - 2
+ gEfiCpuTokenSpaceGuid.PcdPlatformType|0|UINT8|0x60000003
+ ## Indicates the maximum CPU core frequency in the platform.
+ # @Prompt Maximum CPU core frequency in the platform.
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|0x0|UINT32|0x60000004
+ ## Platform CPU maximum FSB frequency (not used).
+ # @Prompt Platform CPU maximum FSB frequency.
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|0x0|UINT32|0x60000005
+ ## Specifies the base address of the first microcode Patch in the microcode Region.
+ # @Prompt Microcode Region base address.
+ gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x60000009
+ ## Specifies the size of the microcode Region.
+ # @Prompt Microcode Region size.
+ gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x6000000A
+ ## Indicates if Intel Enhanced Debug (IED) will be enabled.
+ # Note that for some processors, IED is optional, but for others, IED is required.<BR><BR>
+ # TRUE - IED will be enabled.<BR>
+ # FALSE - IED will be disabled.<BR>
+ # @Prompt Enable IED.
+ gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|FALSE|BOOLEAN|0x6000000B
+ ## Specifies the IEDRAM size.
+ # Note that there is a minimum size requirement for a processor.
+ # @Prompt IEDRAM size.
+ gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x20000|UINT32|0x6000000C
+ ## Specifies the Energy efficiency policy when Energy Performance Bias feature is enabled.
+ # 0 - indicates preference to highest performance.
+ # 15 - indicates preference to maximize energy saving.
+ # @Prompt The Energy efficiency policy.
+ # @ValidRange 0x80000001 | 0 - 15
+ gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0x0|UINT8|0x60008000
+ ## Specifies the 16-bit IO port base address of the LVL_2 register visible to software.
+ # @Prompt LVL_2 register IO port base address.
+ gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0x0|UINT16|0x60008001
+ ## Specifies the package C-State limit.
+ # @Prompt The package C-State limit.
+ # @ValidRange 0x80000001 | 0 - 7
+ gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0x0|UINT8|0x60008002
+
+ ## Specifies the On-demand clock modulation duty cycle when T-State feature is enabled.
+ # @Prompt The encoded values for target duty cycle modulation.
+ # @ValidRange 0x80000001 | 0 - 15
+ gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x60008003
+ ## Indicates if HW Coordination is enabled when EIST feature is enabled.<BR><BR>
+ # TRUE - HW Coordination will be enabled.<BR>
+ # FALSE - HW Coordination will be disabled.<BR>
+ # @Prompt Enable HW Coordination.
+ gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|FALSE|BOOLEAN|0x60008004
+ ## Selects the DCU (Data Cache Unit) mode.<BR><BR>
+ # 0 - 32-KB 8-way without ECC.<BR>
+ # 1 - 16-KB 4-way with ECC.<BR>
+ # @Prompt The DCU (Data Cache Unit) mode.
+ # @ValidRange 0x80000001 | 0 - 1
+ gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0x0|UINT8|0x60008005
+ ## Specifies the AP wait loop mode during POST.
+ # The value is defined as below.<BR><BR>
+ # 1: ApInHltLoop, AP is in the Hlt-Loop state.<BR>
+ # 2: ApInMwaitLoop, AP is in the Mwait-Loop state.<BR>
+ # 3: ApInRunLoop, AP is in the Run-Loop state.<BR>
+ # @Prompt The AP wait loop mode.
+ # @ValidRange 0x80000001 | 1 - 3
+ gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
+ ## Indidates if SMM Save State saved in MSRs.
+ # if enabled, SMM Save State will use the MSRs instead of the memory.<BR><BR>
+ # TRUE - SMM Save State will use the MSRs.<BR>
+ # FALSE - SMM Save State will use the memory.<BR>
+ # @Prompt SMM Save State uses MSRs.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x60000014
+ ## Specifies the SMRR2 base address.<BR><BR>
+ # @Prompt SMRR2 base address.
+ # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xfff) == 0
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x60000015
+ ## Specifies the SMRR2 range size.<BR><BR>
+ # @Prompt SMRR2 range size.
+ # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xfff) == 0
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x60000016
+ ## Specifies the SMRR2 range cache type.
+ # If SMRR2 is used to map a flash/ROM based handler, it would be configured as WP.<BR><BR>
+ # 5: WP(Write Protect).<BR>
+ # 6: WB(Write Back).<BR>
+ # @Prompt SMRR2 range cache type.
+ # @ValidList 0x80000001 | 5, 6
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x60000017
+ ## Indidates if SMM Delay feature is supported.<BR><BR>
+ # TRUE - SMM Delay feature is supported.<BR>
+ # FALSE - SMM Delay feature is not supported.<BR>
+ # @Prompt SMM Delay feature.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018
+ ## Indidates if SMM Block feature is supported.<BR><BR>
+ # TRUE - SMM Block feature is supported.<BR>
+ # FALSE - SMM Block feature is not supported.<BR>
+ # @Prompt SMM Block feature.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019
+ ## Indidates if SMM Enable/Disable feature is supported.<BR><BR>
+ # TRUE - SMM Enable/Disable feature is supported.<BR>
+ # FALSE - SMM Enable/Disable feature is not supported.<BR>
+ # @Prompt SMM Enable/Disable feature.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|TRUE|BOOLEAN|0x6000001A
+ ## Specifies the TCC Activation Offset value.<BR><BR>
+ # @Prompt TCC Activation Offset value.
+ gEfiCpuTokenSpaceGuid.PcdCpuTccActivationOffset|0|UINT8|0x6000001B
+ ## Indidates if SMM PROT MODE feature is supported.<BR><BR>
+ # TRUE - SMM PROT MODE feature is supported.<BR>
+ # FALSE - SMM PROT MODE feature is not supported.<BR>
+ # @Prompt SMM PROT MODE feature.
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x6000001C
+
+
+[PcdsDynamicEx]
+ gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009
+
+ ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
+ # @Prompt Processor feature capabilities.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapability|0|UINT32|0x40000002
+ ## Specifies actual settings for processor features, each bit corresponding to a specific feature.
+ # @Prompt Actual processor feature settings.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSetting|0|UINT32|0x40000003
+ ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
+ # @Prompt Processor feature extension1 capabilities.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapabilityEx1|0|UINT32|0x40000004
+ ## Specifies actual settings for processor features, each bit corresponding to a specific feature.
+ # @Prompt Actual processor feature extension1 settings.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSettingEx1|0|UINT32|0x40000005
+ ## Contains the pointer to CPU Configuration Context Buffer defined in the CpuConfigLib.
+ # @Prompt The pointer to CPU Configuration Context Buffer.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001
+ ## Used for a callback mechanism for the CPU MP driver.
+ # The CPU MP driver will set this PCD at pre-defined points. If there is callback function registered on it,
+ # the callback function will be triggered, and it may change the value of PcdCpuCallbackSignal.
+ # @Prompt PCD for CPU callback signal.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0|UINT8|0x50000002
+ ## Platform CPU frequency lists (not used).
+ # @Prompt Platform CPU frequency lists.
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuFrequencyLists|0x0|UINT64|0x60000006
+ ## Specifies the number of CPU sockets in the platform.
+ # @Prompt The number of CPU sockets in the platform.
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012
+ ## Contains the pointer to a pointer array of which each item points to a unicode string of CPU socket name.
+ # @Prompt The name of each CPU socket.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames|0x0|UINT64|0x60000007
+ ## Contains the pointer to a pointer array of which each item points to a unicode string of CPU asset tag.
+ # @Prompt The asset tag of each CPU socket.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags|0x0|UINT64|0x60000008
+ ## Indicates if the current boot is a power-on reset.<BR><BR>
+ # TRUE - Current boot is a power-on reset.<BR>
+ # FALSE - Current boot is not a power-on reset.<BR>
+ # @Prompt Current boot is a power-on reset.
+ gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x6000000F
+ ## CPU page table address (not used).
+ # @Prompt CPU page table address.
+ gEfiCpuTokenSpaceGuid.PcdCpuPageTableAddress|0x0|UINT64|0x6000000E
+ ## Contains the pointer to a MTRR table buffer of structure MTRR_SETTINGS.
+ # @Prompt The pointer to a MTRR table buffer.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuMtrrTableAddress|0x0|UINT64|0x6000000D
+ ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
+ # @Prompt The pointer to a CPU S3 data buffer.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
+
+ ## Contains the pointer to a buffer where new socket IDs to be assigned are stored.
+ # @Prompt The pointer to a new socket ID buffer.
+# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0}|VOID*|0x60008007
+
+ ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
+ # @Prompt The pointer to CPU Hot Plug Data.
+ # @ValidList 0x80000001 | 0
+ gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
+
+ ## Contains the pointer to a buffer where new socket IDs to be assigned are stored.
+ # @Prompt The pointer to a new socket ID buffer.
+ gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x3,0x0,0x0,0x0}|VOID*|0x60008007
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x6000001D
+
diff --git a/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h new file mode 100644 index 0000000000..ef9ffb7fe2 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h @@ -0,0 +1,671 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include <Protocol/MpService.h> +#include <AcpiCpuData.h> + +// +// Bits definition of PcdProcessorFeatureUserConfiguration, +// PcdProcessorFeatureCapability, and PcdProcessorFeatureSetting +// +#define PCD_CPU_HT_BIT 0x00000001 +#define PCD_CPU_CMP_BIT 0x00000002 +#define PCD_CPU_L2_CACHE_BIT 0x00000004 +#define PCD_CPU_L2_ECC_BIT 0x00000008 +#define PCD_CPU_VT_BIT 0x00000010 +#define PCD_CPU_LT_BIT 0x00000020 +#define PCD_CPU_EXECUTE_DISABLE_BIT 0x00000040 +#define PCD_CPU_L3_CACHE_BIT 0x00000080 +#define PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT 0x00000100 +#define PCD_CPU_FAST_STRING_BIT 0x00000200 +#define PCD_CPU_FERR_SIGNAL_BREAK_BIT 0x00000400 +#define PCD_CPU_PECI_BIT 0x00000800 +#define PCD_CPU_HARDWARE_PREFETCHER_BIT 0x00001000 +#define PCD_CPU_ADJACENT_CACHE_LINE_PREFETCH_BIT 0x00002000 +#define PCD_CPU_DCU_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_IP_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_MACHINE_CHECK_BIT 0x00010000 +#define PCD_CPU_THERMAL_MANAGEMENT_BIT 0x00040000 +#define PCD_CPU_EIST_BIT 0x00080000 +#define PCD_CPU_C1E_BIT 0x00200000 +#define PCD_CPU_C2E_BIT 0x00400000 +#define PCD_CPU_C3E_BIT 0x00800000 +#define PCD_CPU_C4E_BIT 0x01000000 +#define PCD_CPU_HARD_C4E_BIT 0x02000000 +#define PCD_CPU_DEEP_C4_BIT 0x04000000 +#define PCD_CPU_A20M_DISABLE_BIT 0x08000000 +#define PCD_CPU_MONITOR_MWAIT_BIT 0x10000000 +#define PCD_CPU_TSTATE_BIT 0x20000000 +#define PCD_CPU_TURBO_MODE_BIT 0x80000000 + +// +// Bits definition of PcdProcessorFeatureUserConfigurationEx1, +// PcdProcessorFeatureCapabilityEx1, and PcdProcessorFeatureSettingEx1 +// +#define PCD_CPU_C_STATE_BIT 0x00000001 +#define PCD_CPU_C1_AUTO_DEMOTION_BIT 0x00000002 +#define PCD_CPU_C3_AUTO_DEMOTION_BIT 0x00000004 +#define PCD_CPU_MLC_STREAMER_PREFETCHER_BIT 0x00000008 +#define PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT 0x00000010 +#define PCD_CPU_THREE_STRIKE_COUNTER_BIT 0x00000020 +#define PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT 0x00000040 +#define PCD_CPU_DCA_BIT 0x00000080 +#define PCD_CPU_X2APIC_BIT 0x00000100 +#define PCD_CPU_AES_BIT 0x00000200 +#define PCD_CPU_APIC_TPR_UPDATE_MESSAGE_BIT 0x00000400 +#define PCD_CPU_SOCKET_ID_REASSIGNMENT_BIT 0x00000800 +#define PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT 0x00001000 +#define PCD_CPU_ENABLE_IA_UNTRUSTED_MODE_BIT 0x00002000 +#define PCD_CPU_L2_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_L1_DATA_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_C1_AUTO_UNDEMOTION_BIT 0x00010000 +#define PCD_CPU_C3_AUTO_UNDEMOTION_BIT 0x00020000 + +// +// Value definition for PcdCpuCallbackSignal +// +#define CPU_BYPASS_SIGNAL 0x00000000 +#define CPU_DATA_COLLECTION_SIGNAL 0x00000001 +#define CPU_PROCESSOR_FEATURE_LIST_CONFIG_SIGNAL 0x00000002 +#define CPU_REGISTER_TABLE_TRANSLATION_SIGNAL 0x00000003 +#define CPU_PROCESSOR_SETTING_SIGNAL 0x00000004 +#define CPU_PROCESSOR_SETTING_END_SIGNAL 0x00000005 + +// CPU C State Settings +#define C3_ENABLE 0x02 +#define C6_ENABLE 0x03 +#define C7_ENABLE 0x04 +#define C8_ENABLE 0x05 +#define C9_ENABLE 0x06 +#define C10_ENABLE 0x07 + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +// +// Enumeration of processor features +// +typedef enum { + Ht, + Cmp, + Vt, + ExecuteDisableBit, + L3Cache, + MaxCpuidValueLimit, + FastString, + FerrSignalBreak, + Peci, + HardwarePrefetcher, + AdjacentCacheLinePrefetch, + DcuPrefetcher, + IpPrefetcher, + ThermalManagement, + Eist, + BiDirectionalProchot, + Forcepr, + C1e, + C2e, + C3e, + C4e, + HardC4e, + DeepC4, + Microcode, + Microcode2, + MachineCheck, + GateA20MDisable, + MonitorMwait, + TState, + TurboMode, + CState, + C1AutoDemotion, + C3AutoDemotion, + MlcStreamerPrefetcher, + MlcSpatialPrefetcher, + ThreeStrikeCounter, + EnergyPerformanceBias, + Dca, + X2Apic, + Aes, + ApicTprUpdateMessage, + TccActivation, + PeciDownstreamWrite, + IaUntrustedMode, + L2Prefetcher, + L1DataPrefetcher, + C1AutoUndemotion, + C3AutoUndemotion, + CpuFeatureMaximum +} CPU_FEATURE_ID; + +// +// Structure for collected processor feature capability, +// and feature-specific attribute. +// +typedef struct { + BOOLEAN Capability; + VOID *Attribute; +} CPU_FEATURE_DATA; + +// +// Structure for collected CPUID data. +// +typedef struct { + EFI_CPUID_REGISTER *CpuIdLeaf; + UINTN NumberOfBasicCpuidLeafs; + UINTN NumberOfExtendedCpuidLeafs; + UINTN NumberOfCacheAndTlbCpuidLeafs; + UINTN NumberOfDeterministicCacheParametersCpuidLeafs; + UINTN NumberOfExtendedTopologyEnumerationLeafs; +} CPU_CPUID_DATA; + +typedef struct { + UINTN Ratio; + UINTN Vid; + UINTN Power; + UINTN TransitionLatency; + UINTN BusMasterLatency; +} FVID_ENTRY; + +// +// Miscellaneous processor data +// +typedef struct { + // + // Local Apic Data + // + UINT32 InitialApicID; ///< Initial APIC ID + UINT32 ApicID; ///< Current APIC ID + EFI_PHYSICAL_ADDRESS ApicBase; + UINT32 ApicVersion; + // + // Frequency data + // + UINTN IntendedFsbFrequency; + UINTN ActualFsbFrequency; + BOOLEAN FrequencyLocked; + UINTN MaxCoreToBusRatio; + UINTN MinCoreToBusRatio; + UINTN MaxTurboRatio; + UINTN MaxVid; + UINTN MinVid; + UINTN PackageTdp; + UINTN CoreTdp; + UINTN NumberOfPStates; + FVID_ENTRY *FvidTable; + // + // Config TDP data + // + UINTN PkgMinPwrLvl1; + UINTN PkgMaxPwrLvl1; + UINTN ConfigTDPLvl1Ratio; + UINTN PkgTDPLvl1; + UINTN PkgMinPwrLvl2; + UINTN PkgMaxPwrLvl2; + UINTN ConfigTDPLvl2Ratio; + UINTN PkgTDPLvl2; + + // + // Other data + // + UINT32 PlatformRequirement; + UINT64 HealthData; + UINT32 MicrocodeRevision; + UINT64 EnabledThreadCountMsr; +} CPU_MISC_DATA; + +// +// Structure for all collected processor data +// +typedef struct { + CPU_CPUID_DATA CpuidData; + EFI_CPU_PHYSICAL_LOCATION ProcessorLocation; + CPU_MISC_DATA CpuMiscData; + CPU_FEATURE_DATA FeatureData[CpuFeatureMaximum]; + UINT8 PackageIdBitOffset; + BOOLEAN PackageBsp; +} CPU_COLLECTED_DATA; + +#define GET_CPU_MISC_DATA(ProcessorNumber, Item) \ + ((mCpuConfigLibConfigContextBuffer->CollectedDataBuffer[ProcessorNumber]).CpuMiscData.Item) + +// +// Signature for feature list entry +// +#define EFI_CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'f', 't', 'r') + +// +// Node of processor feature list +// +typedef struct { + UINT32 Signature; + CPU_FEATURE_ID FeatureID; + VOID *Attribute; + LIST_ENTRY Link; +} CPU_FEATURE_ENTRY; + +#define CPU_FEATURE_ENTRY_FROM_LINK(link) CR (link, CPU_FEATURE_ENTRY, Link, EFI_CPU_FEATURE_ENTRY_SIGNATURE) + +// +// Definition of Processor Configuration Context Buffer +// +typedef struct { + UINTN NumberOfProcessors; + UINTN BspNumber; + CPU_COLLECTED_DATA *CollectedDataBuffer; + LIST_ENTRY *FeatureLinkListEntry; + CPU_REGISTER_TABLE *PreSmmInitRegisterTable; + CPU_REGISTER_TABLE *RegisterTable; + UINTN *SettingSequence; +} CPU_CONFIG_CONTEXT_BUFFER; + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT32 DefaultSocketId; + UINT32 NewSocketId; +} CPU_SOCKET_ID_INFO; + +extern CPU_CONFIG_CONTEXT_BUFFER *mCpuConfigLibConfigContextBuffer; + +/** + Set feature capability and related attribute. + + This function sets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Feature-specific data. + +**/ +VOID +EFIAPI +SetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Clears feature capability and related attribute. + + This function clears the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + +**/ +VOID +EFIAPI +ClearProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID + ); + +/** + Get feature capability and related attribute. + + This function gets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Pointer to the output feature-specific data. + + @retval TRUE The feature is supported by the processor + @retval FALSE The feature is not supported by the processor + +**/ +BOOLEAN +EFIAPI +GetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + OUT VOID **Attribute OPTIONAL + ); + +typedef enum { + BasicCpuidLeaf, + ExtendedCpuidLeaf, + CacheAndTlbCpuidLeafs, + DeterministicCacheParametersCpuidLeafs, + ExtendedTopologyEnumerationCpuidLeafs +} CPUID_TYPE; + +/** + Get the number of CPUID leafs of various types. + + This function get the number of CPUID leafs of various types. + + @param ProcessorNumber Handle number of specified logical processor + @param CpuidType The type of the CPU id. + + @return Maximal index of CPUID instruction for basic leafs. + +**/ +UINTN +EFIAPI +GetNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber, + IN CPUID_TYPE CpuidType + ); + +/** + Get the pointer to specified CPUID leaf. + + This function gets the pointer to specified CPUID leaf. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetProcessorCpuid ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of cache and TLB parameters. + + This function gets the pointer to specified CPUID leaf of cache and TLB parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetCacheAndTlbCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of deterministic cache parameters. + + This function gets the pointer to specified CPUID leaf of deterministic cache parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetDeterministicCacheParametersCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of Extended Topology Enumeration. + + This function gets the pointer to specified CPUID leaf of Extended Topology Enumeration. + + @param ProcessorNumber Handle number of specified logical processor. + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetExtendedTopologyEnumerationCpuidLeafs ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the version information of specified logical processor. + + This function gets the version information of specified logical processor, + including family ID, model ID, stepping ID and processor type. + + @param ProcessorNumber Handle number of specified logical processor + @param DisplayedFamily Pointer to family ID for output + @param DisplayedModel Pointer to model ID for output + @param SteppingId Pointer to stepping ID for output + @param ProcessorType Pointer to processor type for output + +**/ +VOID +EFIAPI +GetProcessorVersionInfo ( + IN UINTN ProcessorNumber, + OUT UINT32 *DisplayedFamily OPTIONAL, + OUT UINT32 *DisplayedModel OPTIONAL, + OUT UINT32 *SteppingId OPTIONAL, + OUT UINT32 *ProcessorType OPTIONAL + ); + +/** + Get initial local APIC ID of specified logical processor + + This function gets initial local APIC ID of specified logical processor. + + @param ProcessorNumber Handle number of specified logical processor + + @return Initial local APIC ID of specified logical processor + +**/ +UINT32 +EFIAPI +GetInitialLocalApicId ( + UINTN ProcessorNumber + ); + +/** + Get the location of specified processor. + + This function gets the location of specified processor, including + package number, core number within package, thread number within core. + + @param ProcessorNumber Handle number of specified logical processor. + @param PackageNumber Pointer to the output package number. + @param CoreNumber Pointer to the output core number. + @param ThreadNumber Pointer to the output thread number. + +**/ +VOID +EFIAPI +GetProcessorLocation ( + IN UINTN ProcessorNumber, + OUT UINT32 *PackageNumber OPTIONAL, + OUT UINT32 *CoreNumber OPTIONAL, + OUT UINT32 *ThreadNumber OPTIONAL + ); + +/** + Get the Feature entry at specified position in a feature list. + + This function gets the Feature entry at specified position in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + @param Attribute Pointer to output feature-specific attribute + + @return Feature ID of specified feature. CpuFeatureMaximum means not found + +**/ +CPU_FEATURE_ID +EFIAPI +GetProcessorFeatureEntry ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + OUT VOID **Attribute OPTIONAL + ); + +/** + Append a feature entry at the end of a feature list. + + This function appends a feature entry at the end of a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS This function always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +AppendProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Delete a feature entry in a feature list. + + This function deletes a feature entry in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + + @retval EFI_SUCCESS The feature node successfully removed. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +DeleteProcessorFeatureFromList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex + ); + +/** + Insert a feature entry into a feature list. + + This function insert a feature entry into a feature list before a node specified by FeatureIndex. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the new node in feature list. + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS The feature node successfully inserted. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +InsertProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Add an entry in the post-SMM-init register table. + + This function adds an entry in the post-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WriteRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Add an entry in the pre-SMM-init register table. + + This function adds an entry in the pre-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WritePreSmmInitRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Set the sequence of processor setting. + + This function sets the a processor setting at the position in + setting sequence specified by Index. + + @param Index The zero-based index in the sequence. + @param ProcessorNumber Handle number of the processor to set. + + @retval EFI_SUCCESS The sequence successfully modified. + @retval EFI_INVALID_PARAMETER Index surpasses the boundary of sequence. + @retval EFI_NOT_FOUND Processor specified by ProcessorNumber does not exist. + +**/ +EFI_STATUS +SetSettingSequence ( + IN UINTN Index, + IN UINTN ProcessorNumber + ); + +/** + Set PcdCpuCallbackSignal, and then read the value back. + + This function sets PCD entry PcdCpuCallbackSignal. If there is callback + function registered on it, the callback function will be triggered, and + it may change the value of PcdCpuCallbackSignal. This function then reads + the value of PcdCpuCallbackSignal back, the check whether it has been changed. + + @param Value The value to set to PcdCpuCallbackSignal. + + @return The value of PcdCpuCallbackSignal read back. + +**/ +UINT8 +SetAndReadCpuCallbackSignal ( + IN UINT8 Value + ); + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h new file mode 100644 index 0000000000..0bf7d0c2e0 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h @@ -0,0 +1,24 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ +#define _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ + +#define INTEL_CPU_PCDS_SET_DONE_PROTOCOL_GUID \ + { \ + 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd, 0x78 } \ + } + +extern EFI_GUID gIntelCpuPcdsSetDoneProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleySktPkg/SktCommonLib.dsc b/Silicon/Intel/PurleySktPkg/SktCommonLib.dsc new file mode 100644 index 0000000000..e721adb7f9 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/SktCommonLib.dsc @@ -0,0 +1,15 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.common]
diff --git a/Silicon/Intel/PurleySktPkg/SktDxeLib.dsc b/Silicon/Intel/PurleySktPkg/SktDxeLib.dsc new file mode 100644 index 0000000000..30a8f76f93 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/SktDxeLib.dsc @@ -0,0 +1,16 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+ CsrToPcieLib|$(SKT_PKG)/Library/CsrToPcieLib/CsrToPcieDxeLib.inf
diff --git a/Silicon/Intel/PurleySktPkg/SktPeiLib.dsc b/Silicon/Intel/PurleySktPkg/SktPeiLib.dsc new file mode 100644 index 0000000000..08abd42ebd --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/SktPeiLib.dsc @@ -0,0 +1,18 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.IA32]
+ CsrToPcieLib|$(SKT_PKG)/Library/CsrToPcieLib/CsrToPciePeiLib.inf
+ PcieAddrLib|$(SKT_PKG)/Library/PcieAddressLib/PcieAddressLib.inf
+
diff --git a/Silicon/Intel/PurleySktPkg/SocketPkg.dec b/Silicon/Intel/PurleySktPkg/SocketPkg.dec new file mode 100644 index 0000000000..e109e8763b --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/SocketPkg.dec @@ -0,0 +1,117 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PurleySktPkg
+ PACKAGE_GUID = DD44D851-9A3E-46E8-A2Ef-D794D014ECC1
+ PACKAGE_VERSION = 0.91
+
+[Includes]
+ Include
+ Include/Library
+ Include/Guid
+
+ Library/ProcMemInit/Chip/Include
+ Override/IA32FamilyCpuPkg
+ Override/IA32FamilyCpuPkg/Include
+
+ Iio/Include
+ Iio/Include/Protocol
+
+[Guids]
+ gCpuUncoreTokenSpaceGuid = { 0x9044434c, 0x40e8, 0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 } }
+ gProcessorProducerGuid = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } }
+ gEfiCpuHtCapableGuid = { 0x0d1b9c8e, 0xf77b, 0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 } }
+ gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } }
+ gEfiMemoryConfigDataHobGuid = { 0x1de25879, 0x6e2a, 0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 } }
+ gEfiMemorySetupGuid = { 0x3eeff35f, 0x147c, 0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 } }
+ gEfiMemoryMapGuid = { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
+ gEfiMemoryMapDataHobBdatGuid = { 0x3417b225, 0x916a, 0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 } }
+ gEfiMpstNodeDataGuid = { 0x418bc604, 0xf15e, 0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 0x88 } }
+ gReadyForLockProtocolGuid = { 0x8d6f1add, 0x45a5, 0x45a8, { 0x8b, 0xb8, 0x0c, 0x3a, 0x95, 0x31, 0x48, 0xfa } }
+ gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } }
+ gEfiSocketIioVariableGuid = { 0xdd84017e, 0x7f52, 0x48f9, { 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0x0d, 0xbe, 0x27 } }
+ gEfiSocketCommonRcVariableGuid = { 0x4402ca38, 0x808f, 0x4279, { 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f } }
+ gEfiSocketMpLinkVariableGuid = { 0x2b9b22de, 0x2ad4, 0x4abc, { 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c } }
+ gEfiSocketPciResourceDataGuid = { 0xca3ff937, 0xd646, 0x4936, { 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 } }
+ gEfiSocketMemoryVariableGuid = { 0x98cf19ed, 0x4109, 0x4681, { 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 } }
+ gEfiSocketPowermanagementVarGuid = { 0xA1047342, 0xBDBA, 0x4DAE, { 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 } }
+ gEfiSocketProcessorCoreVarGuid = { 0x07013588, 0xC789, 0x4E12, { 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C } }
+ gSocketPkgListGuid = { 0x5c0083db, 0x3f7d, 0x4b20, { 0xac, 0x9b, 0x73, 0xfc, 0x65, 0x1b, 0x25, 0x03 } }
+ gEfiVolatileMemModeVariableGuid = { 0x0633a0f1, 0x78fe, 0x4139, { 0xb8, 0x78, 0x00, 0x45, 0xe8, 0x1c, 0xb8, 0xab } }
+ gEfiQpiRcParmGuid = { 0x8149fbb8, 0xa2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d } }
+ gAddressBasedMirrorGuid = { 0x7b9be2e0, 0xe28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } }
+ gClvBootTimeTestExecution = { 0x3ff7d152, 0xef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } }
+ gEfiRasClvTesterGuid = { 0x9bd36f4f, 0x08dc, 0x4eab, { 0x86, 0x37, 0x2b, 0xc1, 0xbd, 0x5e, 0x0d, 0x95 } }
+ gSocketPkgFpgaGuid = { 0x624b948f, 0x6eba, 0x4dfd, { 0x9d, 0xda, 0x10, 0xb0, 0x07, 0x3a, 0x37, 0x35 } } # {624B948F-6EBA-4DFD-9DDA-10B0073A3735}
+ gIioPolicyHobGuid = { 0xcabb327, 0x11fe, 0x416b, { 0xae, 0x80, 0x2d, 0xe5, 0xdf, 0x60, 0xf7, 0x7d } }
+ gEfiSmmPeiSmramMemoryReserveGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } }
+
+[Ppis]
+ gPeiBaseMemoryTestPpiGuid = { 0xb6ec423c, 0x21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 } }
+ gPeiPlatformMemorySizePpiGuid = { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 } }
+ gPeiMpServicePpiGuid = { 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0x0a, 0xc6, 0x90, 0x0d, 0xb0, 0x25, 0x0a } }
+
+[Protocols]
+ gEfiIioUdsProtocolGuid = { 0xa7ced760, 0xc71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb } }
+ gEfiIioSystemProtocolGuid = { 0xddc3080a, 0x2740, 0x4ec2, { 0x9a, 0xa5, 0xa0, 0xad, 0xef, 0xd6, 0xff, 0x9c } }
+ gEfiCpuCsrAccessGuid = { 0x0067835f, 0x9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 } }
+ gEfiQuiesceProtocolGuid = { 0x20d6e759, 0x4c4a, 0x40c0, { 0x95, 0x33, 0x2b, 0xf0, 0x06, 0x68, 0x50, 0xfd } }
+ gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } }
+ gEfiHpIoxAccessGuid = { 0x62652b53, 0x79d9, 0x4cf2, { 0xb5, 0xaa, 0xad, 0x99, 0x81, 0x0a, 0x7f, 0x17 } }
+
+ gEfiPciCallbackProtocolGuid = { 0x1ca0e202, 0xfe9e, 0x4776, { 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0x06 }}
+
+[PcdsFeatureFlag]
+ gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031
+ gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x10000001
+
+### [PcdsFixedAtBuild, PcdsPatchableInModule]
+[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic]
+ ## PCD for ServerCommonPkg\Override\IA32FamilyCpuPkg\CpuMpDxe.inf
+ ## This PCD is the AP state on POST. The value is defined as below.
+ # 1: ApInHltLoop, AP is in the Hlt-Loop state.
+ # 2: ApInMwaitLoop, AP is in the Mwait-Loop state.
+ # 3: ApInRunLoop, AP is in the Run-Loop state.
+ gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x10001004
+
+[PcdsFixedAtBuild]
+ gPlatformTokenSpaceGuid.PcdBusStack|0x06|UINT8|0x30000006
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08|UINT8|0x3000000D
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02|UINT8|0x3000000E
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC|UINT8|0x3000000F
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFD00000|UINT32|0x2000000D
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000300000|UINT32|0x2000000E
+ gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|0xFFFB0000|UINT32|0x30000004
+ gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize|0x00010000|UINT32|0x30000005
+ gCpuUncoreTokenSpaceGuid.PcdWaSlowModeEnable|0|BOOLEAN|0x30000008
+
+[PcdsDynamicEx]
+ gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007
+ gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF|UINT8|0x6000801B
+ gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009
+ gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0|UINT32|0x60008022
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0x0|UINT8|0x60008018
+ gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0|UINT64|0x60008019
+ gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0|UINT64|0x6000801C
+ gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0|UINT64|0x60008023
+ gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0|UINT8|0x6000801D
+ gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0|UINT64|0x6000801A
+ gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0|UINT64|0x60008020
+ gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0|UINT64|0x60008024
+
+[PcdsFeatureFlag]
+ ## This PCD specifies whether StatusCode is reported via USB Serial port.
+ gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE|BOOLEAN|0x1000000F
|