diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:30 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:30 +0800 |
| commit | ba037b96944c1d1a310867f1c6fb515d96444556 (patch) | |
| tree | 113ca8ca2a53af29dd57498a48f41cad4c2b0246 | |
| parent | 0c4229f0c041ae2f5990b9fce1bbf8e1bb842845 (diff) | |
| download | edk2-platforms-ba037b96944c1d1a310867f1c6fb515d96444556.tar.xz | |
PurleyRcPkg: Initial version.
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
53 files changed, 6564 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h b/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h new file mode 100644 index 0000000000..a4aaa24ba8 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include <UsraAccessType.h> + +////////////////////////////////////////////////////////////////////////// +// +// CSR to Pcie Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h b/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h new file mode 100644 index 0000000000..22b4179db3 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h @@ -0,0 +1,54 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MM_PCIE_BASE_LIB_H_ +#define _MM_PCIE_BASE_LIB_H_ + +#include <Library/UsraAccessApi.h> + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +); + +#endif // _MM_PCIE_BASE_LIB_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h b/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h new file mode 100644 index 0000000000..3f0cbf8e6f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include <UsraAccessType.h> + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmware Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; // "MCFG" Signature For this Table + UINT32 Length; // Length, in bytes, include base address allocation structures. + UINT8 Revision; // "1" + UINT8 SegMax; // The Maximum number of Segments + UINT16 ValidSegMap; // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; // Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; // PCI Segment Group Number. Default is 0. + UINT8 StartBus; // Start PCI Bus number decoded by the host bridge + UINT8 EndBus; // End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; // The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; // First Array of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param[in] MmcfgTable A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type + @param[in] NumOfSeg Number of Segments in the table + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +/** + This Lib return PCIE MMCFG Base Address + + @param[in] Address A pointer of the address of the USRA Address Structure for PCIE type + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h b/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h new file mode 100644 index 0000000000..6712b78ea6 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h @@ -0,0 +1,33 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_PLATFORM_HOOK_LIB_H__ +#define __PCIE_PLATFORM_HOOK_LIB_H__ + +typedef enum { + PcieInitStart, + BeforeBifurcation, + AfterBifurcation, + BeforePortInit, + AfterPortInit, + PcieInitEnd +} PCIE_HOOK_EVENT; + +EFI_STATUS +EFIAPI +PciePlatformHookEvent ( + IN PCIE_HOOK_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h b/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h new file mode 100644 index 0000000000..cbe365cea3 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h @@ -0,0 +1,91 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __USRA_ACCESS_API_H__ +#define __USRA_ACCESS_API_H__ + + +#include <UsraAccessType.h> + +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Access Library +// +////////////////////////////////////////////////////////////////////////// + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +GetRegisterAddress ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h b/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h new file mode 100644 index 0000000000..f380967cc4 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// This defines the maximum number of sockets supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + diff --git a/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h b/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h new file mode 100644 index 0000000000..c0f4624a8f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h @@ -0,0 +1,168 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SILICON_REG_ACCESS_PPI_H__ +#define __SILICON_REG_ACCESS_PPI_H__ + +#include <UsraAccessType.h> + +extern EFI_GUID gUsraPpiGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PPI_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PPI_REG_READ RegRead; + USRA_PPI_REG_WRITE RegWrite; + + USRA_PPI_REG_MODIFY RegModify; + USRA_PPI_GET_ADDR GetRegAddr; +} USRA_PPI; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +PeiGetRegAddr ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h b/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h new file mode 100644 index 0000000000..72e556b270 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h @@ -0,0 +1,233 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SILICON_REG_ACCESS_PROTOCOL_H__ +#define __SILICON_REG_ACCESS_PROTOCOL_H__ + +#include <UsraAccessType.h> + +extern EFI_GUID gUsraProtocolGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PROTOCOL_REG_READ RegRead; + USRA_PROTOCOL_REG_WRITE RegWrite; + USRA_PROTOCOL_REG_MODIFY RegModify; + USRA_PROTOCOL_GET_ADDR GetRegAddr; +} USRA_PROTOCOL; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +DxeGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + /** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +SmmGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h b/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h new file mode 100644 index 0000000000..d3a97a6446 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h @@ -0,0 +1,201 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __USRA_ACCESS_TYPE_H__ +#define __USRA_ACCESS_TYPE_H__ + +typedef enum { + AddrTypePCIE = 0, + AddrTypePCIEBLK, + AddrTypeCSR, + AddrTypeMMIO, + AddrTypeIO, + AddrTypeMaximum +} USRA_ADDR_TYPE; + +typedef enum { + UsraWidth8 = 0, + UsraWidth16, + UsraWidth32, + UsraWidth64, + UsraWidthFifo8, + UsraWidthFifo16, + UsraWidthFifo32, + UsraWidthFifo64, + UsraWidthFill8, + UsraWidthFill16, + UsraWidthFill32, + UsraWidthFill64, + UsraWidthMaximum +} USRA_ACCESS_WIDTH; + +typedef enum { + CsrBoxInst = 0, + CsrChId, + CsrMcId, + CsrSubTypeMax +} CSR_INST_TYPE; + +#define USRA_ENABLE 1; +#define USRA_DISABLE 0; + +#pragma pack (1) + +typedef struct + { + UINT32 RawData32[2]; // RawData of two UINT32 type, place holder + UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO, IO, SMBus ... + UINT32 AccessWidth:4; // The Access width for 8, 16,32,64 -bit access + UINT32 FastBootEn:1; // Fast Boot Flag, can be used to log register access trace for fast boot + UINT32 S3Enable:1; // S3 Enable bit, when enabled, it will save the write to script to support S3 + UINT32 HptrType:1; // Host Pointer type, below or above 4GB + UINT32 ConvertedType:1; // The address type was from converted type, use this field for address migration support + UINT32 RFU3:16; // Reserved for User use or Future Use + + UINT32 HostPtr:32; // The Host Pointer, to point to Attribute buffer etc. +} ADDR_ATTRIBUTE_TYPE; + +typedef struct + { + UINT32 Offset:12; // The PCIE Register Offset + UINT32 Func:3; // The PCIE Function + UINT32 Dev:5; // The PCIE Device + UINT32 Bus:8; // The PCIE Bus + UINT32 RFU1:4; // Reserved for User use or Future Use + + UINT32 Seg:16; // The PCI Segment + UINT32 Count:16; // Access Count + +} USRA_PCIE_ADDR_TYPE; + +typedef struct + { + UINT32 Offset; // This Offset occupies 32 bits. It's platform code's responsibilty to define the meaning of specific + // bits and use them accordingly. + UINT32 InstId:8; // The Box Instance, 0 based, Index/Port within the box, Set Index as 0 if the box has only one instances + UINT32 SocketId:8; // The socket Id + UINT32 InstType:8; // The Instance Type, it can be Box, Memory Channel etc. + UINT32 RFU:8; // Reserved for User use or Future Ues + +} USRA_CSR_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:32; // The MMIO Offset + + UINT32 OffsetH: 32; // The MMIO Offset Higher 32-bit +} USRA_MMIO_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:16; // The IO Offset + UINT32 RFU1:16; // Reserved for User use or Future Use + + UINT32 RFU2:32; // Reserved for User use or Future Use + +} USRA_IO_ADDR_TYPE; + +#pragma pack() + +typedef union { + UINT32 dwRawData[4]; + ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute type. + USRA_PCIE_ADDR_TYPE Pcie; + USRA_PCIE_ADDR_TYPE PcieBlk; + USRA_CSR_ADDR_TYPE Csr; + USRA_MMIO_ADDR_TYPE Mmio; + USRA_IO_ADDR_TYPE Io; +} USRA_ADDRESS; + +// +// Assemble macro for USRA_PCIE_ADDR_TYPE +// +#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(OFFSET) & 0x0FFF + +// +// Assemble macro for USRA_BDFO_ADDR_TYPE +// +#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BDFO >> 20) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(BDFO >> 15) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(BDFO >> 12) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(BDFO) & 0x0FFF + +// +// Assemble macro for USRA_PCIE_BLK_ADDR_TYPE +// +#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIEBLK; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Count = (UINT32)COUNT; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg = (UINT32)SEG; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset = (UINT32)(OFFSET) & 0x0FFF +// +// Assemble macro for USRA_PCIE_SEG_ADDR_TYPE +// +#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET) + +// +// Assemble macro for USRA_CSR_ADDR_TYPE +// +#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET, INSTTYPE) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType = INSTTYPE; \ + ((USRA_ADDRESS *)(&Address))->Csr.SocketId = SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstId = INSTID; \ + ((USRA_ADDRESS *)(&Address))->Csr.Offset = CSROFFSET + +// +// Assemble macro for ZERO_USRA ADDRESS +// +#define USRA_ZERO_ADDRESS(Address) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)0; \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +// +// Assemble macro for ZERO_ADDR_TYPE +// +#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)((AddressType) & 0x0FF); \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \ + ((UINT32 *)DestAddrPtr)[3] = ((UINT32 *)SourceAddrPtr)[3]; \ + ((UINT32 *)DestAddrPtr)[2] = ((UINT32 *)SourceAddrPtr)[2]; \ + ((UINT32 *)DestAddrPtr)[1] = ((UINT32 *)SourceAddrPtr)[1]; \ + ((UINT32 *)DestAddrPtr)[0] = ((UINT32 *)SourceAddrPtr)[0]; + +#endif + diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h new file mode 100644 index 0000000000..79ab649751 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h @@ -0,0 +1,306 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_CONFIG_H +#define _IIO_CONFIG_H + +#pragma pack(1) //to align members on byte boundary +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; + +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTIMP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Implemented - PCIE Capabilities (D0-10 / F0 / R0x92 / B8) + UINT16 SLOTPSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Physical slot Number - Slot Capabilities (D0-10 / F0 / R0xA4 / B31:19). Change to use 13 bits instead of 8 + UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) + UINT8 SLOTSPLS[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Scale - Slot Capabilities (D0-10 / F0 / R0xA4 / B16:15) + UINT8 SLOTSPLV[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Value - Slot Capabilities (D0-10 / F0 / R0xA4 / B14:7) + UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) + UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) + UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indicate if Port will PcieSSD capable. + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + // + // VPP Control + // + UINT8 VppEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj + UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj + UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + UINT8 Serr; + UINT8 Perr; + UINT8 IioErrorEn; + UINT8 LerEn; + UINT8 WheaPcieErrInjEn; + + // + // PciePll + // + UINT8 PciePllSsc; //On Setup + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Cb3DcaEn[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + UINT8 MctpEn; + + UINT8 LegacyVgaSoc; + UINT8 LegacyVgaStack; + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PcieSSD Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; // Indicate if PCIE AIC Device will be connected behind an specific IOUx + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + +/** +================================================================================================== +================================== Gen3 Related Setup Options ========================== +================================================================================================== +**/ + + //PCIE Global Option + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== IOAPIC Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; +/** +================================================================================================== +================================== Security Related Setup Options ========================== +================================================================================================== +**/ + UINT8 LockChipset; + UINT8 PeciInTrustControlBit; + UINT8 ProcessorX2apic; + UINT8 ProcessorMsrLockControl; + +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + UINT8 RtoEnable; // On Setup + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} IIO_CONFIG; +#pragma pack() + +#endif // _IIO_CONFIG_H diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h new file mode 100644 index 0000000000..7c980cb458 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h @@ -0,0 +1,292 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_PLATFORM_DATA_H_ +#define _IIO_PLATFORM_DATA_H_ + +#include <SysRegs.h> +#include <KtiSi.h> +#include <IioRegs.h> +#include <IioConfig.h> +#ifndef MINIBIOS_BUILD +#ifndef IA32 +#include <Uefi.h> +#include <PiDxe.h> +#include <Protocol/CpuCsrAccess.h> +#define IIO_CPU_CSR_ACCESS EFI_CPU_CSR_ACCESS_PROTOCOL +#endif +#endif + +#define IIO_HANDLE VOID * +#define IIO_STATUS UINT32 + +typedef struct { + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT32 ExtendedRegister; +} PCI_ROOT_BRIDGE_PCI_ADDRESS; + +typedef enum { + DmiTypeVc0, + DmiTypeVc1, + DmiTypeVcm, + MaxDmiVcType +} DMI_VC_TYPE; + +#define MaxDmiTcType 3 + +typedef enum { + IIOInitPhase1 = 1, + IIOInitPhase2 = 2, + IIOInitPhase3 = 4, +} IIO_INIT_PHASE; + +typedef enum { + IioBeforeBifurcation, // Point before IOU Bi-fucuation and link training, no generic inbound access at this point + IioAfterBifurcation, // Point immediately after IOU bifurcation and link training but before any PCIe root port initialization + IioPortEnumeration, // Point before Port initialization, no generic inbound access at this point + IioPortEnumProgramMISCCTRL, // Inside IioPortInit.PcieSlotInit + IioEnumEnd, + IioVtDPreEn, + IioVtDInit, + IioVtDEn, // At this point it has been decided to enable VtD through setup IioVtdInit.VtdInitialization + IioPostInitEnd, // this is the last stage of IIO PCIe port init + IioBeforeResources, // At this point IIO Ports configuration has been completed + IioAfterResources // At this point PCIe Resources allocation has been completed +} IIO_INIT_ENUMERATION; + + +extern const CHAR* IioPortLabel[]; + +#define IIO_PORT_LABEL(x) ( ((x) < NUMBER_PORTS_PER_SOCKET) ? (IioPortLabel[(x)]) : IioPortLabel[NUMBER_PORTS_PER_SOCKET] ) + +#pragma pack(1) + +typedef union{ + struct{ + UINT32 Value; + UINT32 ValueHigh; + }Address32bit; + UINT64 Address64bit; +}IIO_PTR_ADDRESS; + +typedef struct { + UINT32 Device; + UINT32 Function; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} PCI_OP_STRUCT; + +typedef struct { + UINT32 Instance; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} CSR_ACCESS_OP_STRUCT; + +typedef struct { + UINT8 Isoc; + UINT32 meRequestedSize; + UINT8 Vc1_pri_en; + UINT8 Isoc_Enable; +} ISOC_VC_TABLE_STRUCT; + +/* + * Following are the data structure defined to support multiple CBDMA types on a system + */ + +typedef struct{ + UINT32 DcaSupported : 1; + UINT32 NoSnoopSupported : 1; + UINT32 RelaxOrderSupported : 1; +}CB_CONFIG_CAPABILITY; + +typedef struct{ + UINT8 CB_VER; + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT8 MaxNoChannels; + CB_CONFIG_CAPABILITY CBConfigCap; +}CBDMA_CONTROLLER; + +typedef struct{ + CBDMA_CONTROLLER CbDmaDevice; +}DMA_HOST; + +// <<<< end of CBDMA data structures >>>> + +typedef union { +struct { + UINT32 Dev0 : 1; + UINT32 Dev1 : 1; + UINT32 Dev2 : 1; + UINT32 Dev3 : 1; + UINT32 Dev4 : 1; + UINT32 Dev5 : 1; + UINT32 Dev6 : 1; + UINT32 Dev7 : 1; + UINT32 Dev8 : 1; + UINT32 Dev9 : 1; + UINT32 Dev10 : 1; + UINT32 Dev11 : 1; + UINT32 Dev12 : 1; + UINT32 Dev13 : 1; + UINT32 Dev14 : 1; + UINT32 Dev15 : 1; + UINT32 Dev16 : 1; + UINT32 Dev17 : 1; + UINT32 Dev18 : 1; + UINT32 Dev19 : 1; + UINT32 Dev20 : 1; + UINT32 Dev21 : 1; + UINT32 Dev22 : 1; + UINT32 Dev23 : 1; + UINT32 Dev24 : 1; + UINT32 Dev25 : 1; + UINT32 Dev26 : 1; + UINT32 Dev27 : 1; + UINT32 Dev28 : 1; + UINT32 Dev29 : 1; + UINT32 Dev30 : 1; + UINT32 Dev31 : 1; + } Bits; + UINT32 Data; +} DEVHIDE_FIELD; + +typedef struct{ + UINT32 DevToHide[NUM_DEVHIDE_REGS]; +} IIO_DEVFUNHIDE; + +typedef struct{ + IIO_DEVFUNHIDE IioStackDevHide[MAX_IIO_STACK]; +}IIO_DEVFUNHIDE_TABLE; + +typedef struct { + UINT8 CpuType; + UINT8 CpuStepping; + UINT8 CpuSubType; + UINT8 IsocEnable; + UINT8 EVMode; + UINT32 meRequestedSize; + UINT8 DmiVc[MaxDmiVcType]; + UINT8 DmiVcId[MaxDmiVcType]; + UINT8 DmiTc[MaxDmiTcType]; + UINT8 PlatformType; + UINT8 IOxAPICCallbackBootEvent; + UINT8 RasOperation; + UINT8 SocketUnderOnline; + UINT8 CompletedReadyToBootEventServices; + UINT8 SocketPresent[MaxIIO]; + UINT8 SocketBaseBusNumber[MaxIIO]; + UINT8 SocketLimitBusNumber[MaxIIO]; + UINT8 StackPresentBitmap[MaxIIO]; + UINT64_STRUCT SegMmcfgBase[MaxIIO]; + UINT8 SegmentSocket[MaxIIO]; + UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 SocketUncoreBusNumber[MaxIIO]; + UINT32 PchIoApicBase; + UINT32 PciResourceMem32Base[MaxIIO]; + UINT32 PciResourceMem32Limit[MaxIIO]; + UINT8 Pci64BitResourceAllocation; + UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK]; + UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK]; + UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK]; + UINT32 RcBaseAddress; + UINT64 PciExpressBase; + UINT32 PmBase; + UINT32 PchSegRegBaseAddress; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT8 Emulation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT8 IODC; + UINT8 MultiPch; + UINT8 FpgaActive[MaxIIO]; +} IIO_V_DATA; + +typedef struct { + UINT8 Device; + UINT8 Function; +} IIO_PORT_INFO; + +typedef struct { + UINT8 Valid; + UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF) + IIO_PORT_INFO UplinkPortInfo; +}IIO_UPLINK_PORT_INFO; + +typedef struct _INTEL_IIO_PORT_INFO { + UINT8 Device; + UINT8 Function; + UINT8 RtoDevice; + UINT8 RtoFunction; + UINT8 RtoClusterDevice; + UINT8 RtoClusterFunction; + UINT8 RtoReutLinkSel; + UINT8 SuperClusterPort; +} INTEL_IIO_PORT_INFO; + +typedef struct _INTEL_DMI_PCIE_INFO { + INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} INTEL_DMI_PCIE_INFO; + +typedef struct _INTEL_IIO_PRELINK_DATA { + INTEL_DMI_PCIE_INFO PcieInfo; + IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO]; +} INTEL_IIO_PRELINK_DATA; + +typedef struct { + UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 MaxPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LinkedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 SpeedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LaneReversedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + IIO_PTR_ADDRESS PtrAddress; + IIO_PTR_ADDRESS PtrPcieTopology; + UINT64 McastRsvdMemory; + DMA_HOST DMAhost[MaxIIO]; + UINT8 resetRequired; +} IIO_OUT_DATA; + +typedef struct { + IIO_V_DATA IioVData; + INTEL_IIO_PRELINK_DATA PreLinkData; + IIO_OUT_DATA IioOutData; +} IIO_VAR; + +typedef struct { + IIO_CONFIG SetupData; + IIO_VAR IioVar; +} IIO_GLOBALS; + +#pragma pack() + +#endif //_IIO_PLATFORM_DATA_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h new file mode 100644 index 0000000000..f91a879a4e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h @@ -0,0 +1,320 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_REGS_H_ +#define _IIO_REGS_H_ + +/** +================================================================================================== +================================== General Defintions ================================== +================================================================================================== +**/ + +#define NUMBER_PORTS_PER_SOCKET 21 +#define IIO_UPLINK_PORT_INDEX 5 //Port 2A is the uplink port in Neon-City ///TODO Check if this is required for SKX/Purley SKX_TTEST +#define MaxIIO MAX_SOCKET + +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO +#endif + +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure! +#define TOTAL_SYSTEM_IIO_STACKS 32 // In term of system architecture support +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#define TOTAL_SYSTEM_IIO_STACKS 24 // In term of system architecture support +#endif + +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#endif +#define VMD_STACK_PER_SOCKET 3 +#define VMD_PORT_PER_STACK 4 +#define VMD_PORTS_PER_SOCKET 12 +#if MAX_SOCKET > 4 +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#else +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#endif + + +#define VARIABLE_FUNC3_ELEMENTS 4 +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + + +/** +================================================================================================== +================================== IIO Root Port Defintions ==================== +================================================================================================== +**/ +typedef enum { + IioPortA = 0, + IioPortB = 1, + IioPortC = 2, + IioPortD = 3 +}IIOPORTS; + +typedef enum { + IioIou0 = 0, + IioIou1, + IioIou2, + IioMcp0, + IioMcp1, + IioIouMax +} IIOIOUS; + +// +// Bifurcation control register shorthand +// +#define IIO_BIFURCATE_AUTO 0xFF + +// Ports 1D-1A, 2D-2A, 3D-3A +// +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + +#define PORT_0_INDEX 0 +#define PCIE_PORT_2_DEV 0x02 + +// IOU2 +#define PORT_1A_INDEX 1 +#define PORT_1B_INDEX 2 +#define PORT_1C_INDEX 3 +#define PORT_1D_INDEX 4 +// IOU0 +#define PORT_2A_INDEX 5 +#define PORT_2B_INDEX 6 +#define PORT_2C_INDEX 7 +#define PORT_2D_INDEX 8 +// IOU1 +#define PORT_3A_INDEX 9 +#define PORT_3B_INDEX 10 +#define PORT_3C_INDEX 11 +#define PORT_3D_INDEX 12 +//MCP0 +#define PORT_4A_INDEX 13 +#define PORT_4B_INDEX 14 +#define PORT_4C_INDEX 15 +#define PORT_4D_INDEX 16 +//MCP1 +#define PORT_5A_INDEX 17 +#define PORT_5B_INDEX 18 +#define PORT_5C_INDEX 19 +#define PORT_5D_INDEX 20 + +// +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +#define PCIE_PORT_0_DEV 0x00 +#define PCIE_PORT_0_FUNC 0x00 + +#define PCIE_PORT_1A_DEV 0x00 +#define PCIE_PORT_1B_DEV 0x01 +#define PCIE_PORT_1C_DEV 0x02 +#define PCIE_PORT_1D_DEV 0x03 +#define PCIE_PORT_1A_FUNC 0x00 +#define PCIE_PORT_1B_FUNC 0x00 +#define PCIE_PORT_1C_FUNC 0x00 +#define PCIE_PORT_1D_FUNC 0x00 + +#define PCIE_PORT_2A_DEV 0x00 +#define PCIE_PORT_2B_DEV 0x01 +#define PCIE_PORT_2C_DEV 0x02 +#define PCIE_PORT_2D_DEV 0x03 +#define PCIE_PORT_2A_FUNC 0x00 +#define PCIE_PORT_2B_FUNC 0x00 +#define PCIE_PORT_2C_FUNC 0x00 +#define PCIE_PORT_2D_FUNC 0x00 + +#define PCIE_PORT_3A_DEV 0x00 +#define PCIE_PORT_3B_DEV 0x01 +#define PCIE_PORT_3C_DEV 0x02 +#define PCIE_PORT_3D_DEV 0x03 +#define PCIE_PORT_3A_FUNC 0x00 +#define PCIE_PORT_3B_FUNC 0x00 +#define PCIE_PORT_3C_FUNC 0x00 +#define PCIE_PORT_3D_FUNC 0x00 + +#define PCIE_PORT_4A_DEV 0x00 +#define PCIE_PORT_4B_DEV 0x01 +#define PCIE_PORT_4C_DEV 0x02 +#define PCIE_PORT_4D_DEV 0x03 +#define PCIE_PORT_4A_FUNC 0x00 +#define PCIE_PORT_4B_FUNC 0x00 +#define PCIE_PORT_4C_FUNC 0x00 +#define PCIE_PORT_4D_FUNC 0x00 + +#define PCIE_PORT_5A_DEV 0x00 +#define PCIE_PORT_5B_DEV 0x01 +#define PCIE_PORT_5C_DEV 0x02 +#define PCIE_PORT_5D_DEV 0x03 +#define PCIE_PORT_5A_FUNC 0x00 +#define PCIE_PORT_5B_FUNC 0x00 +#define PCIE_PORT_5C_FUNC 0x00 +#define PCIE_PORT_5D_FUNC 0x00 + +#define PCIE_PORT_GLOBAL_RTO_DEV 0x07 +#define PCIE_PORT_GLOBAL_RTO_FUNC 0x07 + +#define PCIE_PORT_0_RTO_DEV 0x07 +#define PCIE_PORT_0_RTO_FUNC 0x00 + +#define PCIE_PORT_1A_RTO_DEV 0x07 +#define PCIE_PORT_1A_RTO_FUNC 0x00 +#define PCIE_PORT_1B_RTO_DEV 0x07 +#define PCIE_PORT_1B_RTO_FUNC 0x01 +#define PCIE_PORT_1C_RTO_DEV 0x07 +#define PCIE_PORT_1C_RTO_FUNC 0x02 +#define PCIE_PORT_1D_RTO_DEV 0x07 +#define PCIE_PORT_1D_RTO_FUNC 0x03 + + +#define PCIE_PORT_2A_RTO_DEV 0x07 +#define PCIE_PORT_2A_RTO_FUNC 0x00 +#define PCIE_PORT_2B_RTO_DEV 0x07 +#define PCIE_PORT_2B_RTO_FUNC 0x01 +#define PCIE_PORT_2C_RTO_DEV 0x07 +#define PCIE_PORT_2C_RTO_FUNC 0x02 +#define PCIE_PORT_2D_RTO_DEV 0x07 +#define PCIE_PORT_2D_RTO_FUNC 0x03 + +#define PCIE_PORT_3A_RTO_DEV 0x07 +#define PCIE_PORT_3A_RTO_FUNC 0x00 +#define PCIE_PORT_3B_RTO_DEV 0x07 +#define PCIE_PORT_3B_RTO_FUNC 0x01 +#define PCIE_PORT_3C_RTO_DEV 0x07 +#define PCIE_PORT_3C_RTO_FUNC 0x02 +#define PCIE_PORT_3D_RTO_DEV 0x07 +#define PCIE_PORT_3D_RTO_FUNC 0x03 + +#define PCIE_PORT_4A_RTO_DEV 0x07 +#define PCIE_PORT_4A_RTO_FUNC 0x00 +#define PCIE_PORT_4B_RTO_DEV 0x07 +#define PCIE_PORT_4B_RTO_FUNC 0x01 +#define PCIE_PORT_4C_RTO_DEV 0x07 +#define PCIE_PORT_4C_RTO_FUNC 0x02 +#define PCIE_PORT_4D_RTO_DEV 0x07 +#define PCIE_PORT_4D_RTO_FUNC 0x03 + +#define PCIE_PORT_5A_RTO_DEV 0x07 +#define PCIE_PORT_5A_RTO_FUNC 0x00 +#define PCIE_PORT_5B_RTO_DEV 0x07 +#define PCIE_PORT_5B_RTO_FUNC 0x01 +#define PCIE_PORT_5C_RTO_DEV 0x07 +#define PCIE_PORT_5C_RTO_FUNC 0x02 +#define PCIE_PORT_5D_RTO_DEV 0x07 +#define PCIE_PORT_5D_RTO_FUNC 0x03 + +#define PCIE_PORT_0_LINK_SEL 0x00 +#define PCIE_PORT_1A_LINK_SEL 0x00 +#define PCIE_PORT_1B_LINK_SEL 0x01 +#define PCIE_PORT_1C_LINK_SEL 0x02 +#define PCIE_PORT_1D_LINK_SEL 0x03 +#define PCIE_PORT_2A_LINK_SEL 0x00 +#define PCIE_PORT_2B_LINK_SEL 0x01 +#define PCIE_PORT_2C_LINK_SEL 0x02 +#define PCIE_PORT_2D_LINK_SEL 0x03 +#define PCIE_PORT_3A_LINK_SEL 0x00 +#define PCIE_PORT_3B_LINK_SEL 0x01 +#define PCIE_PORT_3C_LINK_SEL 0x02 +#define PCIE_PORT_3D_LINK_SEL 0x03 +#define PCIE_PORT_4A_LINK_SEL 0x00 +#define PCIE_PORT_4B_LINK_SEL 0x01 +#define PCIE_PORT_4C_LINK_SEL 0x02 +#define PCIE_PORT_4D_LINK_SEL 0x03 +#define PCIE_PORT_5A_LINK_SEL 0x00 +#define PCIE_PORT_5B_LINK_SEL 0x01 +#define PCIE_PORT_5C_LINK_SEL 0x02 +#define PCIE_PORT_5D_LINK_SEL 0x03 + +#define PCIE_PORT_0_SUPER_CLUSTER_PORT 0x00 +#define PCIE_PORT_1A_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1B_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1C_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1D_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_2A_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2B_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2C_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2D_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_3A_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3B_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3C_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3D_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_4A_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4B_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4C_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4D_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_5A_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5B_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5C_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5D_SUPER_CLUSTER_PORT 0x11 + +#define PORT_LINK_WIDTH_x16 16 +#define PORT_LINK_WIDTH_x8 8 +#define PORT_LINK_WIDTH_x4 4 +#define PORT_LINK_WIDTH_x2 2 +#define PORT_LINK_WIDTH_x1 1 + +// +// Port Config Mode +// +#define REGULAR_PCIE_OWNERSHIP 0 +#define PCIE_PORT_REGULAR_MODE 1 +#define PCIE_PORT_NTB_MODE 2 +#define VMD_OWNERSHIP 3 +#define PCIEAIC_OCL_OWNERSHIP 4 + + +/** +================================================================================================== +================================== Devide Hide Definitions ======================================= +================================================================================================== +**/ + +#define NUM_DEVHIDE_REGS 8 +// Hide all 8 Devices for every Stack +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#if MaxIIO > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MaxIIO) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MaxIIO) +#endif + +#endif //_IIO_REGS_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h new file mode 100644 index 0000000000..bd505703b0 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef IIOSETUPDEFINITIONS_H_ +#define IIOSETUPDEFINITIONS_H_ + +/** +================================================================================================== +================= Equates common for Setup options (.vfr/.hfr) and source files (.c/.h) ========== +================================================================================================== +**/ + +#define PCIE_ASPM_AUTO 7 +#define PCIE_ASPM_DISABLE 0 +#define PCIE_ASPM_L0S_ONLY 1 +#define PCIE_ASPM_L1_ONLY 2 +#define PCIE_ASPM_L0S_L1_BOTH 3 + +#define PCIE_LINK_SPEED_AUTO 0 +#define PCIE_LINK_SPEED_GEN1 1 +#define PCIE_LINK_SPEED_GEN2 2 +#define PCIE_LINK_SPEED_GEN3 3 + +#define PCIE_L0S_4US_8US 3 +#define PCIE_L1_8US_16US 4 + +#define IIO_OPTION_AUTO 2 +#define IIO_OPTION_ENABLE 1 +#define IIO_OPTION_DISABLE 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH2_CURSOR_MIN 0 +#define GEN3MANUAL_PH2_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH2_CURSOR_MAX 63 +#define GEN3MANUAL_PH2_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH2_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH2_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH2_POSTCURSOR_DEFAULT 11 + +#define GEN3MANUAL_PH3_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH3_CURSOR_MIN 0 +#define GEN3MANUAL_PH3_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH3_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH3_CURSOR_MAX 63 +#define GEN3MANUAL_PH3_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH3_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH3_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH3_POSTCURSOR_DEFAULT 11 + +#define RTO_GEN3_OVERRIDE_MODE_UNIPHY 0 +#define RTO_GEN3_OVERRIDE_MODE_MANUAL 1 +#define RTO_GEN3_OVERRIDE_MODE_TEST_CARD 2 +#define RTO_GEN3_OVERRIDE_MODE_ALTERNATE_TXEQ 3 + +#define RTO_GEN3_TEST_CARD_LAGUNA 0 +#define RTO_GEN3_TEST_CARD_NTB 1 + +#define RTO_GEN3_EQ_MODE_TESTCARD 1 +#define RTO_GEN3_EQ_MODE_NTB_TESTCARD 2 + + +#define COMPLETION_TIMEOUT_260MS_900MS 9 + +#define SNOOP_RESP_DEF_VALUE 6 + +#define MC_INDEX_POS_12 0xC + +#define MC_NUM_GROUP_8 8 + +#define CONFIG_IOU_AUTO 0xFF + +#define NTB_BARSIZE_PBAR23_DEFAULT 0xC +#define NTB_BARSIZE_PBAR45_DEFAULT 0xC +#define NTB_BARSIZE_PBAR4_DEFAULT 0xC +#define NTB_BARSIZE_PBAR5_DEFAULT 0xC +#define NTB_BARSIZE_SBAR23_DEFAULT 0xC +#define NTB_BARSIZE_SBAR45_DEFAULT 0xC +#define NTB_BARSIZE_SBAR4_DEFAULT 0xC +#define NTB_BARSIZE_SBAR5_DEFAULT 0xC +#define NTB_IIO_XLINK_CTL_DSD_USP 2 + +#define VMD_CFG_BAR_SIZE_DEFAULT 25 +#define VMD_MEM_BAR_SIZE1_DEFAULT 25 +#define VMD_MEM_BAR_SIZE2_DEFAULT 20 + +#define VMD_32BIT_NONPREFETCH 0 +#define VMD_64BIT_NONPREFETCH 1 +#define VMD_64BIT_PREFETCH 2 + +#define IODC_DISABLE 0 +#define IODC_AUTO 1 +#define IODC_EN_REM_INVITOM_PUSH 2 +#define IODC_EN_REM_INVITOM_ALLOCFLOW 3 +#define IODC_EN_REM_INVITOM_ALLOC_NONALLOC 4 +#define IODC_EN_REM_INVITOM_AND_WCILF 5 +#define IODC_GLOBAL_KTI_OPTION 6 + +#define PCIE_PORT_DISABLE 0 +#define PCIE_PORT_ENABLE 1 +#define PCIE_PORT_AUTO 2 + +#endif /* IIOSETUPDEFINITIONS_H_ */ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h new file mode 100644 index 0000000000..a393e46639 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h @@ -0,0 +1,32 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _KTI_DISCOVERY_H_ +#define _KTI_DISCOVERY_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" + +#define MAX_TREE_NODES (MAX_SOCKET + 2) // 2 additional nodes since a node will appear more than once in the tree when it is being constructed +#define MAX_RING_TREE_NODES 46 // A CPU with 3 links supported will have 1 + 1*3 + 3*2 + 6*2 + 12*2 = 46 nodes maximum in ring tree +#define MAX_RINGS 6 // Maximum number of rings possible in systems with upto 8 sockets (HyperCube) +#define CPUS_PER_RING 4 // # of CPUs in a CPU ring +#define VN0 0 +#define VN1 1 +#define TX 0 +#define RX 1 + +#endif // _KTI_DISCOVERY_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h new file mode 100644 index 0000000000..afbd81265b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h @@ -0,0 +1,142 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Definition Flag: +// 1. KTI_HW_PLATFORM -> run with real hardware or SoftIVT +// 2. KTI_SW_SIMULATION -> run with KTIRC Simulation +// 3. IA32 -> run with IA32 mode + + +#ifndef _KTI_HOST_H_ +#define _KTI_HOST_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" +#include "KtiDisc.h" + +#pragma pack(1) + +typedef INT32 KTI_STATUS; +#ifndef NULL +#define NULL 0 +#endif +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile +#define KTI_SUCCESS 0 +#define KTI_REBOOT 1 +#define KTI_SNC_CHANGED 2 +#define KTI_IGNORE 3 +#define KTI_FAILURE -1 + +// +// Warning log +// +#define MAX_WARNING_LOGS 16 + +typedef enum { + NORMAL_OPERATION = 0, + RECOVERY_OPERATION +} SNC_COLDRESET_REGISTER_OPERATION_TYPE; + +typedef enum { + KTI_GROUP = 0, +} GROUP_TYPE; + +/********************************************************* + KTIRC Host Structure Related +*********************************************************/ + +typedef enum { + KTI_LINK0 = 0x0, + KTI_LINK1, + KTI_LINK2 +} KTI_LOGIC_LINK; + +typedef enum { + FULL_SPEED = 0, + HALF_SPEED +} KTI_LINK_SPEED_TYPE; + + +// +// Definitions to be used in Eparam tables: +// +typedef enum { + PER_LANES_TXEQ_ENABLED = 0, // each lane use different TXEQ value + ALL_LANES_TXEQ_ENABLED // all lanes use same TXEQ value +} LANE_TXEQ_TYPE; + +// +// Number of Clusters. +// +typedef enum { + CLUSTER_MODE_1, + CLUSTER_MODE_2, +} CLUSTER_MODE; + +typedef enum { + LCC = 0, // 10c + MCC, // 14c + HCC, // 22c + XCC, // 28c + MAX_CHOP_TYPES +} PHYSICAL_CHOP; + + +// +// PHY settings that are system dependent. Need 1 of these for each socket/link/freq. +// + +typedef struct { + UINT8 SocketID; + UINT8 AllLanesUseSameTxeq; + UINT8 Freq; + UINT32 Link; + UINT32 TXEQL[20]; + UINT32 CTLEPEAK[5]; +} PER_LANE_EPARAM_LINK_INFO; + +// +// This is for full speed mode, all lanes have the same TXEQ setting +// +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +#define ADAPTIVE_CTLE 0x3f +#define PER_LANE_ADAPTIVE_CTLE 0X3f3f3f3f + +typedef enum { + TYPE_UBOX = 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_DISABLED, // This item must be prior to stack specific disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_NONE +} STACK_TYPE; + +#pragma pack() + +#endif // _KTI_HOST_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h new file mode 100644 index 0000000000..41904a724e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _KTI_SI_H_ +#define _KTI_SI_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" + +/********************************************************* + KTI Topology Related +*********************************************************/ +#define SI_MAX_CPU_SOCKETS 8 // Maximum CPU sockets supported by Si +#define SI_MAX_KTI_PORTS 3 // Maximum KTI ports supported by Si + +/********************************************************* + IIO Stacks +*********************************************************/ +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 + +/********************************************************* + M3KTI +*********************************************************/ +#define MAX_M3KTI 2 +#define MAX_PORT_IN_M3KTI 2 + +#endif // _KTI_SI_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h new file mode 100644 index 0000000000..4c03534e8a --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h @@ -0,0 +1,149 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPUCSRACCESS_PROTOCOL_H_
+#define _CPUCSRACCESS_PROTOCOL_H_
+
+//
+// CPU CSR Access Protocol GUID
+//
+// {0067835F-9A50-433a-8CBB-852078197814}
+#define EFI_CPU_CSR_ACCESS_GUID \
+ { \
+ 0x67835f, 0x9a50, 0x433a, 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 \
+ }
+
+//#define REG_ADDR( bus, dev, func, reg, size ) ((size << 28) + ((bus+2) << 20) + (dev << 15) + (func << 12) + reg)
+
+typedef
+UINT64
+(EFIAPI *GET_CPU_CSR_ADDRESS) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Size
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 RegOffset,
+ IN UINT32 Data
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 Offset
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset,
+ IN UINT32 Data
+ );
+
+typedef
+UINTN
+(EFIAPI *GET_MC_CPU_ADDR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_PCI_CSR) (
+ IN UINT8 socket,
+ IN UINT32 reg
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_PCI_CSR) (
+ IN UINT8 socket,
+ IN UINT32 reg,
+ IN UINT32 data
+ );
+
+typedef
+UINT32
+(EFIAPI *GET_PCI_CSR_ADDR) (
+ IN UINT8 socket,
+ IN UINT32 reg
+ );
+
+typedef
+VOID
+(EFIAPI *UPDATE_CPU_CSR_ACCESS_VAR) (
+ VOID
+ );
+
+typedef
+UINT32
+(EFIAPI *BIOS_2_PCODE_MAILBOX_WRITE) (
+ IN UINT8 socket,
+ IN UINT32 command,
+ IN UINT32 data
+ );
+
+typedef
+UINT64
+(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) (
+ IN UINT8 socket,
+ IN UINT32 command,
+ IN UINT32 data
+ );
+
+typedef
+VOID
+(EFIAPI *BREAK_AT_CHECK_POINT) (
+ IN UINT8 majorCode,
+ IN UINT8 minorCode,
+ IN UINT16 data
+ );
+
+typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL {
+ GET_CPU_CSR_ADDRESS GetCpuCsrAddress;
+ READ_CPU_CSR ReadCpuCsr;
+ WRITE_CPU_CSR WriteCpuCsr;
+ BIOS_2_PCODE_MAILBOX_WRITE Bios2PcodeMailBoxWrite;
+ BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite;
+ READ_MC_CPU_CSR ReadMcCpuCsr;
+ WRITE_MC_CPU_CSR WriteMcCpuCsr;
+ GET_MC_CPU_ADDR GetMcCpuCsrAddress;
+ UPDATE_CPU_CSR_ACCESS_VAR UpdateCpuCsrAccessVar;
+ READ_PCI_CSR ReadPciCsr;
+ WRITE_PCI_CSR WritePciCsr;
+ GET_PCI_CSR_ADDR GetPciCsrAddress;
+ BREAK_AT_CHECK_POINT BreakAtCheckpoint;
+} EFI_CPU_CSR_ACCESS_PROTOCOL;
+
+extern EFI_GUID gEfiCpuCsrAccessGuid;
+
+#endif
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h new file mode 100644 index 0000000000..2c03670a02 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h @@ -0,0 +1,176 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_UNIVERSAL_DATA_ +#define _IIO_UNIVERSAL_DATA_ + +#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include <Guid/SocketVariable.h> + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// +#define UINT64 unsigned long long + +#pragma pack(1) + + +typedef struct { + UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + UINT8 PeerPort; // Port of the peer socket +}QPI_PEER_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocketFirstBus; + UINT8 SocketLastBus; + UINT8 segmentSocket; + UINT8 PcieSegment; + UINT64_STRUCT SegMmcfgBase; + UINT8 stackPresentBitmap; + UINT8 StackBus[MAX_IIO_STACK]; + UINT8 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList; + UINT32 SocId; + QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + UINT32 VtdBarAddress; +} STACK_RES; + +typedef struct { + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + STACK_RES StackRes[MAX_IIO_STACK]; + UINT32 RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmiolBase; // Global Mmiol base + UINT32 PlatGlobalMmiolLimit; // Global Mmiol limit + UINT64 PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + UINT64 PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; +} PLATFORM_DATA; + +typedef struct { + UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) + UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 MinimumCpuStepping; + UINT8 LtsxEnable; + UINT8 MctpEn; + UINT8 cpuType; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC + UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC + UINT16 tolmLimit; + UINT32 tohmLimit; + UINT32 mmCfgBase; + UINT32 RcVersion; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD support + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 numChPerMC; + UINT8 maxCh; + UINT8 maxIMC; + UINT16 LlcSizeReg; + UINT8 chEnabled[MAX_SOCKET][MAX_CH]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + UINT8 memNode[MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 CpuAccSupport; + UINT8 SmbusErrorRecovery; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + UINT32 OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h new file mode 100644 index 0000000000..6a5f37d3d4 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef cpuhost_h +#define cpuhost_h +#include "PlatformHost.h" +#include "DataTypes.h" +#include "SysHostChipCommon.h" + +#define inline __inline + +// +// CPU ExtFamily/Family/Model bit[19:4] of cpuid(1)_eax +// +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif +#ifndef CPU_FAMILY_ICX +#define CPU_FAMILY_ICX 0x606a // IceLake CPU +#endif +#ifndef CPU_FAMILY_KNH +#define CPU_FAMILY_KNH 0x706F // KnightsHill CPU +#endif + + +//typedef INT32 CPU_STATUS; // this causes MiniBIOS build failure +typedef int CPU_STATUS; +#define CPU_SUCCESS 0 +#define CPU_FAILURE -1 + + +// +// Reset types needed post execution +// +#define POST_RESET_NO_RESET 0x0 +#define POST_RESET_WARM 0x2 // bit1 +#define POST_RESET_POWERGOOD 0x4 // bit2 +#define POST_RESET_AMI 0x8 // bit3 + +// +// Max reservable TOR entries defines +// +#define MAX_TOR_ENTRIES_ISOC 15 +#define MAX_TOR_ENTRIES_NORMAL 17 + +// +// Error Code used for LogError() +// +#define ERROR_CPU_BIST 0xC0 + #define ERROR_CPU_BIST_MINOR_SOME_SOCKET 0x01 + #define ERROR_CPU_BIST_MINOR_SOME_BISTRESULTMASK 0x02 + #define ERROR_CPU_BIST_MINOR_ALL 0x03 + +// +// Error Codes used for LogError() and LogWarning() +// +#define WARN_CPU_BIST 0xC0 +#define WARN_CPU_BIST_MINOR_LOWER_TILE_RANGE 0x01 +#define WARN_CPU_BIST_MINOR_MIDDLE_TILE_RANGE 0x02 +#define WARN_CPU_BIST_MINOR_UPPER_TILE_RANGE 0x03 +#define WARN_CPU_BIST_MINOR_ALL 0x04 + + +// +// MSR definitions +// +#ifndef MSR_IA32_PLATFORM_ID +#define MSR_IA32_PLATFORM_ID 0x0017 +#endif +#ifndef MSR_APIC_BASE +#define MSR_APIC_BASE 0x001B +#endif +#ifndef MSR_EBC_FREQUENCY_ID +#define MSR_EBC_FREQUENCY_ID 0x002C +#endif +#ifndef MSR_CORE_THREAD_COUNT +#define MSR_CORE_THREAD_COUNT 0x0035 +#endif +#ifndef MSR_SOCKET_ID +#define MSR_SOCKET_ID 0x0039 +#endif +#ifndef MSR_IA32_FEATURE_CONTROL +#define MSR_IA32_FEATURE_CONTROL 0x003A +#endif +#ifndef VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR +#define VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR 0x61 +#endif +#ifndef MCAONNONNEMCACHEABLEMMIO_BIT +#define MCAONNONNEMCACHEABLEMMIO_BIT 0x1 +#endif +#ifndef MSR_IA32_BIOS_UPDT_TRIG +#define MSR_IA32_BIOS_UPDT_TRIG 0x0079 +#endif +#ifndef MSR_TRACE_HUB_STH_ACPIBAR_BASE +#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 +#define B_MSR_TRACE_HUB_STH_ACPIBAR_BASE_LOCK BIT0 +#define V_MSR_TRACE_HUB_STH_ACPIBAR_BASE_MASK 0x0003FFFF +#endif +#ifndef PCH_TRACE_HUB_FW_BASE_ADDRESS +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#endif +#ifndef MSR_IA32_BIOS_SIGN_ID +#define MSR_IA32_BIOS_SIGN_ID 0x008B +#endif +#ifndef MSR_PLATFORM_INFO +#define MSR_PLATFORM_INFO 0x00CE +#endif +#ifndef MSR_PMG_CST_CONFIG_CONTROL +#define MSR_PMG_CST_CONFIG_CONTROL 0x00E2 +#endif +#ifndef MSR_PMG_IO_CAPTURE_BASE +#define MSR_PMG_IO_CAPTURE_BASE 0x0E4 +#endif +#ifndef MSR_MCG_CONTAIN +#define MSR_MCG_CONTAIN 0x178 +#define B_MSR_MCG_CONTAIN_PE BIT0 +#endif +#ifndef MSR_IA32_MCG_CAP +#define MSR_IA32_MCG_CAP 0x179 +#define B_MSR_MCG_CAP_GCM BIT24 +#endif +#ifndef MSR_CLOCK_FLEX_MAX +#define MSR_CLOCK_FLEX_MAX 0x0194 +#endif +#ifndef MSR_IA32_PERF_STS +#define MSR_IA32_PERF_STS 0x0198 +#endif +#ifndef MSR_IA32_PERF_CTL +#define MSR_IA32_PERF_CTL 0x0199 +#endif +#ifndef MSR_IA32_MISC_ENABLES +#define MSR_IA32_MISC_ENABLES 0x01A0 +#endif +#ifndef IA32_MISC_ENABLE +#define IA32_MISC_ENABLE 0x01A0 +#endif +#ifndef FAST_STRING_ENABLE_BIT +#define FAST_STRING_ENABLE_BIT 0x1 +#endif +#ifndef MSR_MISC_PWR_MGMT +#define MSR_MISC_PWR_MGMT 0x01AA +#endif +#ifndef MSR_TURBO_POWER_CURRENT_LIMIT +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC +#endif +#ifndef MSR_TURBO_RATIO_LIMIT +#define MSR_TURBO_RATIO_LIMIT 0x01AD +#endif +#ifndef MSR_POWER_CTRL +#define MSR_POWER_CTRL 0x01FC +#endif +#ifndef MSR_NO_EVICT_MODE +#define MSR_NO_EVICT_MODE 0x02E0 +#endif +#ifndef MSR_IA32_MC7_CTL +#define MSR_IA32_MC7_CTL 0x041C +#endif +#ifndef MSR_IA32_MC8_MISC2 +#define MSR_IA32_MC8_MISC2 0x0288 +#endif +#ifndef MSR_PCIEXBAR +#define MSR_PCIEXBAR 0x0300 +#endif +#ifndef MSR_PPIN_CTL +#define MSR_PPIN_CTL 0x004E +#endif +#ifndef MSR_PPIN +#define MSR_PPIN 0x004F +#endif +#ifndef MSR_MC_CTL +#define MSR_MC_CTL 0x0434 +#endif +#define MSR_UNCORE_FREQ 0x0620 + +#define MSR_UPI0_MC_STS 0x0415 +#define MSR_UPI1_MC_STS 0x0431 +#define MSR_UPI2_MC_STS 0x044d + +#ifndef MTRR_PHYS_BASE_0 +#define MTRR_PHYS_BASE_0 0x0200 +#define MTRR_PHYS_MASK_0 0x0201 +#define MTRR_PHYS_BASE_1 0x0202 +#define MTRR_PHYS_MASK_1 0x0203 +#define MTRR_PHYS_BASE_2 0x0204 +#define MTRR_PHYS_MASK_2 0x0205 +#define MTRR_PHYS_BASE_3 0x0206 +#define MTRR_PHYS_MASK_3 0x0207 +#define MTRR_PHYS_BASE_4 0x0208 +#define MTRR_PHYS_MASK_4 0x0209 +#define MTRR_PHYS_BASE_5 0x020A +#define MTRR_PHYS_MASK_5 0x020B +#define MTRR_PHYS_BASE_6 0x020C +#define MTRR_PHYS_MASK_6 0x020D +#define MTRR_PHYS_BASE_7 0x020E +#define MTRR_PHYS_MASK_7 0x020F +#define MTRR_FIX_64K_00000 0x0250 +#define MTRR_FIX_16K_80000 0x0258 +#define MTRR_FIX_16K_A0000 0x0259 +#define MTRR_FIX_4K_C0000 0x0268 +#define MTRR_FIX_4K_C8000 0x0269 +#define MTRR_FIX_4K_D0000 0x026A +#define MTRR_FIX_4K_D8000 0x026B +#define MTRR_FIX_4K_E0000 0x026C +#define MTRR_FIX_4K_E8000 0x026D +#define MTRR_FIX_4K_F0000 0x026E +#define MTRR_FIX_4K_F8000 0x026F +#define MTRR_DEF_TYPE 0x02FF + +#define MTRR_MEMORY_TYPE_UC 0x00 +#define MTRR_MEMORY_TYPE_WC 0x01 +#define MTRR_MEMORY_TYPE_WT 0x04 +#define MTRR_MEMORY_TYPE_WP 0x05 +#define MTRR_MEMORY_TYPE_WB 0x06 + +#define MTRR_DEF_TYPE_E 0x0800 +#define MTRR_DEF_TYPE_FE 0x0400 +#define MTRR_PHYS_MASK_VALID 0x0800 +#endif // MTRR_PHYS_BASE_0 + +// +// Memory-mapped APIC Offsets +// +#define APIC_LOCAL_APIC_ID 0x020 +#define APIC_ICR_LO 0x300 +#define APIC_ICR_HI 0x310 +#define APIC_TMR_INITIAL_CNT 0x380 +#define APIC_TMR_CURRENT_CNT 0x390 + +// +// APIC Timer runs at 133MHz and by default decrements +// the current count register at once per two clocks. +// t = time in milliseconds +// c = APIC Timer Initial Value +// c = (t * 10^(-6) sec) * (133 * 10^6 count/sec) * (1/2 clocks) +// Notice seconds and exponents cancel out leaving count value +// c = (t * 133 / 2) +// +#define APIC_TMR_1US (1 * 133 / 2) +#define APIC_TMR_10US (10 * 133 / 2) +#define APIC_TMR_20US (20 * 133 / 2) +#define APIC_TMR_100US (100 * 133 / 2) +#define APIC_TMR_200US (200 * 133 / 2) +#define APIC_TMR_10MS (10 * 1000 * 133 / 2) + + +#endif // cpuhost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h new file mode 100644 index 0000000000..62313e536f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h @@ -0,0 +1,48 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CSR_TO_PCIE_ADDRESS_H__
+#define __CSR_TO_PCIE_ADDRESS_H__
+
+
+#include <UsraAccessApi.h>
+
+//////////////////////////////////////////////////////////////////////////
+//
+// Common Silicon Address Library
+// This Lib provide the way use platform Library instance
+//
+//////////////////////////////////////////////////////////////////////////
+
+
+/**
+ This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address
+
+ @param[in] Global Global pointer
+ @param[in] Virtual Virtual address
+ @param[in] Address A pointer of the address of the USRA Address Structure
+ @param[out] AlignedAddress A pointer of aligned address converted from USRA address
+
+ @retval NULL The function completed successfully.
+ @retval <>NULL Return Error
+**/
+UINTN
+EFIAPI
+CsrGetPcieAlignAddress (
+ IN VOID *Global,
+ IN BOOLEAN Virtual,
+ IN USRA_ADDRESS *Address,
+ OUT UINTN *AlignedAddress
+ );
+
+#endif
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h new file mode 100644 index 0000000000..83c1ace657 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _datatypes_h +#define _datatypes_h + +typedef unsigned char BOOLEAN; +//typedef signed char INT8; // SKX TODO: All string/ASCII/ANSI character based functions need to be ported to use CHAR type due +// to GCC difference. After that porting occurs, then INT8 should be defined as signed type. MS compiler treats char as signed value. +// GNU compiler treats char as unsigned value. This creates havoc when trying to make code compatible with runtime libraries. So... +// henceforth all strings usage will be of type CHAR and not INT8. +typedef char CHAR; +#if defined(__GNUC__) && !defined(MINIBIOS_BUILD) +typedef signed char INT8; +#else +typedef char INT8; +#endif +typedef char CHAR8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef int INT32; +typedef unsigned int UINT32; +typedef unsigned int MMRC_STATUS; +#define MMRC_SUCCESS 0 +#define MMRC_FAILURE 0xFFFFFFFF +#ifndef CONST +#define CONST const +#endif +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif +#ifndef NULL +#define NULL ((VOID *) 0) +#endif +#ifdef MINIBIOS_BUILD +typedef unsigned long long UINT64; +#endif +typedef unsigned char UCHAR8; +typedef unsigned short CHAR16; +//typedef signed long long SINT64; +//typedef signed long SINT32; +//typedef signed short SINT16; +//typedef signed char SINT8; +#define SINT8 INT8 +#define SINT16 INT16 +#define SINT32 INT32 + +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +typedef UINT64 UINTX; + +typedef struct u64_struct { + UINT32 lo; + UINT32 hi; +} UINT64_STRUCT, *PUINT64_STRUCT; + +typedef struct u128_struct { + UINT32 one; + UINT32 two; + UINT32 three; + UINT32 four; +} UINT128; + +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} GUID_RC; + +#ifndef NT32_BUILD +#if defined (RC_SIM) || defined (MINIBIOS_BUILD) +typedef GUID_RC EFI_GUID; +#endif // #if defined (RC_SIM) || defined (MINIBIOS_BUILD) + +#ifdef MINIBIOS_BUILD +typedef INT32 INTN; +typedef UINT32 UINTN; +typedef UINTN RETURN_STATUS; +#define MAX_BIT (1 << ((sizeof (UINTN) << 3) - 1)) +#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode))) +#define RETURN_SUCCESS 0 +#define RETURN_UNSUPPORTED ENCODE_ERROR (3) +#define EFIAPI +#define PcdUsraSupportS3 FALSE + +#endif // #ifdef MINIBIOS_BUILD +#endif // #ifndef NT32_BUILD + + +#define MAX_STRING_LENGTH 0x100 + +#endif // _datatypes_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h new file mode 100644 index 0000000000..e9bc5fddf9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h @@ -0,0 +1,333 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memhost_h +#define _memhost_h +#include "DataTypes.h" +#include "PlatformHost.h" +#include "SysRegs.h" +#include "MemRegs.h" +#include "MemDefaults.h" +#include "MrcCommonTypes.h" +#include "MemHostChipCommon.h" +#include "KtiSi.h" + +#define MAX_DIMMTABLEINDEX (MAX_CH * MAX_DIMM) + + +#define MAXFIELDVAL(bitfield) (bitfield = 0xffffffff) + +//EFI_GUID definition locations for different BDAT/BSSA cases + +#include <PiPei.h> + +// Debug Build code +// These should be disabled for all normal builds and only enable on demand for debugging +//#define DEBUG_TURNAROUNDS 1 +#define DEBUG_PERFORMANCE_STATS 1 +//#define DEBUG_RDRAND 1 +//#define DEBUG_SENSEAMP 1 + +#ifdef DEBUG_PERFORMANCE_STATS +#define MAX_NOZONE 20 +#endif // DEBUG_PERFORMANCE_STATS + +#define PGT_TIMER_ENABLE 1 +#define PGT_TIMER_DISABLE 0 + +// +// DDR3 frequencies 800 - 2666 +// DDR4 frequencies 1333 - 4200 +// +#define MAX_SUP_FREQ 28 // 26 frequencies are supported (800, 1067, 1333, 1600, 1867, 2133, 2400, 2666, 2933, + // 3200, 3400, 3467, 3600, 3733, 3800, 4000, 4200, 4266, 4400) + + + + +/// +/// External signal names +/// +typedef enum { + RAS_N, CAS_N, WE_N, + BA0, BA1, BA2, + A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, + CS0_N, CS1_N, CS2_N, CS3_N, CS4_N, CS5_N, CS6_N, CS7_N, CS8_N, CS9_N, + CKE0, CKE1, CKE2, CKE3, CKE4, CKE5, + ODT0, ODT1, ODT2, ODT3, ODT4, ODT5, + PAR, ALERT_N, + BG0, BG1, ACT_N, C0, C1, C2, + CK0, CK1, CK2, CK3, CK4, CK5, + FNV_GOOD_PARITY, DESELECT, PRECHARGE, GNT, // these are actually commands as opposed to signals + gsmCsnDelim = INT32_MAX +} GSM_CSN; + +typedef struct { + INT16 left; + INT16 right; +} SIGNAL_EYE; + +#define MAX_PHASE 2 // MAX_PHASE + +// +// Common Core dummy defines +// + +#ifndef MAX_MC_CH +#define MAX_MC_CH 2 // Max channels per MC +#endif +#ifndef MAX_CLUSTERS +#define MAX_CLUSTERS 1 // Maximum number of clusters supported +#endif + +#ifndef MAX_EDC +#define MAX_EDC 1 // Maximum number of EDC supported +#endif + +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#pragma pack(push, 1) + +extern const UINT16 rankSize[MAX_TECH]; ///< Rank size in 64 MB units +extern const UINT16 rankSizeDDR4[MAX_TECH]; ///< Rank size in 64 MB units + + +#define ALL_DRAMS 0xFF // Indicates to write to all DRAMs when in PDA mode +#define ALL_DATABUFFERS 0xFF // Indicates to write to all Buffers in PBA Mode + +typedef enum { +INVALID_BUS, +SMBUS, +EMRS, +CPGC, +SAD, +} BUS_TYPE; + +#ifdef SERIAL_DBG_MSG +#define MemDebugPrint(dbgInfo) debugPrintMem dbgInfo +#define MspDebugPrint(dbgInfo) debugPrintMsp dbgInfo +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) +#else +#define MemDebugPrint(dbgInfo) +#define MspDebugPrint(dbgInfo) +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) OutputCheckpoint dbgInfo +#endif + + +typedef enum +{ + MRC_PF_NULL, // All policy flags turned off. + MRC_PF_COLD = BIT0, // Execute MRC function on cold reset. + MRC_PF_FAST = BIT1, // Execute MRC function on cold reset when S3 data is present. + MRC_PF_WARM = BIT2, // Execute MRC function on warm reset. + MRC_PF_S3 = BIT3, // Execute MRC function on S3 exit. + //MRC_PF_FULL_MRC = BIT4, // Execute MRC function when in Full MRC mode. + //MRC_PF_MINI_MRC = BIT5, // Execute MRC function when in Mini-MRC mode. + MRC_PF_ALL = 0xF // All policy flags turned off. +} PFSelectorType; + +typedef enum +{ + MRC_MP_NULL, // All policy flags turned off + MRC_MP_SERIAL = BIT0, // Execute function when in serial mode + MRC_MP_PARALLEL = BIT1, // Execute function when in parallel mode + MRC_MP_LOOP = BIT2, // Execute function for each socket when in serial mode + MRC_MP_BOTH = MRC_MP_SERIAL | MRC_MP_PARALLEL, // Execute function in both modes + MRC_MP_BOTH_LOOP = MRC_MP_SERIAL | MRC_MP_PARALLEL | MRC_MP_LOOP, // Execute function in both modes and loop +} MPSelectorType; + +// +// TRR defines +// +#define PTRR_MODE BIT0 +#define TRR_MODE_A BIT1 +#define TRR_IMMUNE BIT2 +#ifdef TRR_MODE_B_SUPPORT +#define TRR_MODE_B BIT3 +#endif //TRR_MODE_B_SUPPORT + +typedef struct { + UINT8 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket + UINT8 StackBus[MAX_SOCKET][MAX_IIO_STACK]; ///< Bus of each stack + UINT8 SocketFirstBus[MAX_SOCKET]; + UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only + UINT8 SocketLastBus[MAX_SOCKET]; + UINT8 segmentSocket[MAX_SOCKET]; + UINT8 cpuType; + UINT8 stepping; + UINT32 socketPresentBitMap; + UINT32 FpgaPresentBitMap; + UINT32 mmCfgBase; + UINT8 maxCh; + UINT8 maxIMC; + UINT8 numChPerMC; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + CPU_CSR_ACCESS_VAR_CHIP ///< Chip hook to enable CPU_CSR_ACCESS_VAR fields +} CPU_CSR_ACCESS_VAR; + +#pragma pack(pop) + +/// +/// (MPT_MT - MemeoryPowerTraining_MarginType)param type for power training steps +/// +typedef enum { + GetMargin = 0, + TerMargin = 1, + BerMargin = 2 +} MPT_MT; + +/// +/// (MPT_PT - MemeoryPowerTraining_ParamType)param type for power training steps +/// +typedef enum { + PerChPerByte = 0, + PerRank = 1, + PerStrobe = 2, + PerCh = 3, + PerMC = 4 +} MPT_PT; + +/// +/// (MPT_P - MemeoryPowerTraining_Param)param for power training steps +/// +typedef enum { + traindramron = 0, + trainmcodt = 1, + trainnontgtodt = 2, + trainrttwr = 3, + trainmcron = 4, + traintxeq = 5, + trainimode = 6, + trainctle = 7, + traintcocomp = 8, +} MPT_P; + +#define IMC0 0 +#define IMC1 1 + +// +// PPR Status +// +#define PPR_STS_SUCCESS 0x00 +#define PPR_STS_ADDR_VALID 0x01 +#define PPR_STS_FAILED 0x02 + +#define DRAM_UNKNOWN 0xFF + +#pragma pack(push, 1) +// +// ----------------------------------------------------------------------------- + +// +// NVRAM structures for S3 state +// + +#define MAX_CMD_CSR 16 +#define MAX_SIDE 2 + +// +// ----------------------------------------------------------------------------- +// +// ddrChannelSetup STRUCT 4t ; Channel setup structure declaration +// +// enabled BYTE ? ; Channel enable switch: +// ; 0 = channel disabled +// ; 1 = channel enabled +// +// options BYTE ? ; Bit-mapped options: +// +// numDimmSlots BYTE ? ; Number of Dimm slots per channel +// ; Valid options are 1, 2 or 3 +// ; MAX_DIMM is defined in mrcplatform.h. This option can be no larger than MAX_DIMM. +// ; It overrides MAX_DIMM when it is smaller. +// +// ddrChannelSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +// +// ----------------------------------------------------------------------------- +// +// Node bit-mapped options +// +// ddrSocketSetup STRUCT 4t ; Socket setup structure declaration +// +// enabled BYTE ? ; imc enable switch: +// ; 0 = imc disabled +// ; 1 = imc enabled +// +// options BYTE ? ; Bit-mapped options per socket: +// +// vrefDefaultValue BYTE ? ; Default DCP value per socket for DIMM Vref = Vddq/2 +// +// vrefDcp smbDevice <> ; Defines override of DCP SMBus device and address +// ; compId = DCP_ISL9072X or DCP_AD5247 +// ; strapAddress +// ; busSegment +// +// ddrSocketSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +/// +/// PPR DRAM Address +/// +typedef struct { + UINT8 dimm; + UINT8 rank; + UINT8 subRank; + UINT32 dramMask; + UINT8 bank; + UINT32 row; +} PPR_ADDR; + +// HIGH_ADDR_EN enables extention of the MMIO hole to force memory to high address region +#define HIGH_ADDR_EN BIT0 +#define CR_MIXED_SKU BIT2 //used to enable(1)- halt on mixed sku discovery and disable(0) - warn on mixed sku discovery + +//#pragma pack(pop) + +/// +/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot types and paths through QPIRC/MRC - NormalBoot and S3Resume. +/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, fast warm, fast cold, and ADR resume. These are populated +/// at the beginning of MRC so they are not applicable for QPIRC. +/// +typedef enum SubBootMode +{ + ColdBoot = 8, // Normal path through MRC with full mem detection, init, training, etc. + WarmBoot = 9, // Warm boot path through MRC. Some functionality can be skipped for speed. + WarmBootFast = 10, // Fast warm boot path uses the NVRAM structure to skip as much MRC + // code as possible to try to get through MRC fast. Should be as close + // as possible to the S3 flow. + ColdBootFast = 11, // Fast cold boot path uses the NVRAM structure to skip as much MRC + // code as possible on a cold boot. + AdrResume = 12, // ADR flow can skip most of MRC (i.e. take the S3 path) for DIMMs that + // are in self-refresh. But the DIMMs that are not in self-refresh + // must go through more of MRC. + Reserved13 = 13 +} SubBootMode; + +#define MAX_ADV_MT_LOG 16 + +#define MEM_CHIP_POLICY_DEF(x) host->var.mem.memChipPolicy.x +#define MEM_CHIP_POLICY_VALUE(host, x) host->var.mem.memChipPolicy.x +#define CHIP_FUNC_CALL(host, x) x + +#pragma pack(pop) + +#endif // _memhost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h new file mode 100644 index 0000000000..8a0de60293 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h @@ -0,0 +1,128 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memhostchipcommon_h +#define _memhostchipcommon_h + +#include "SysHostChipCommon.h" + +#define NODE_TO_SKT(node) (node / MAX_IMC) +#define SKT_TO_NODE(socket, mc) ((socket << 1) | (mc & BIT0)) +#define NODE_TO_MC(node) (node % MAX_IMC) +#define SKTMC_TO_NODE(socket, mc) ((socket * MAX_IMC) | (mc % MAX_IMC)) +#define NODECH_TO_SKTCH(node, ch) (((node % MAX_IMC)*MAX_MC_CH) + ch) + +// + +// +//MAX_CHANNELS and DYNVAR_MAX were previously defined in MmrcProjectDefinitionsGenerated.h, but +// now are here and must be manually updated as needed depending on MMRC tool execution (they have been +// removed from automatic generation by the tool) +// +// Channels +// +#define MAX_CHANNELS 6 + +#define DYNVAR_MAX 51 + +#define MAX_IMC 2 + +#define MAX_MC_CH 3 // Max channels per MC +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes +#define MAX_DIMM 2 // Max DIMM per channel + +#define MAX_DIMM3 3 // Max DIMM per channel +#define MAX_TECH 19 // Number of entries in DRAM technology table + +#define MAX_RIR 4 // Number of Rank Interleave Register rules for DDR +#define MAX_RIR_DDRT 4 // Number of Rank Interleave Register rules for NVMDIMM +#define MAX_RIR_WAYS 8 // Number of interleave ways for RIR for DDR +#define TAD_RULES 8 // Number of TAD rule registers +#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES +#define SAD_RULES 24 // Number of SAD rule registers +#define MAX_SAD_RULES 24 // Number of SAD rule registers +#define MAX_STROBE 18 // Number of strobe groups +#define MAX_SEEDS 10 // Maximum +#if QR_DIMM_SUPPORT +#define MAX_RANK_DIMM 4 // Max ranks per DIMM +#else +#define MAX_RANK_DIMM 2 // Max ranks per DIMM +#endif +#define MAX_RANK_CH 8 // Max ranks per channel +#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel +#define SPD_MODULE_PART 18 // Number of bytes of module part - DDR3 +#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4 +#define SAD_RULES_ADDR_RANGE 4 // Max IOT rules = 4, Total address limits (lower(4) entries each) +// Ctl FUBs +#define NUM_CTL_PLATFORM_GROUPS 4 + +// SPD Defines +//----------------------------------------------------------------------------- + +#pragma pack(1) + +// +// Define the WDB line. The WDB line is like the cache line. +// +#define MRC_WDB_LINES 32 +#define MRC_WDB_LINE_SIZE 64 +#define CADB_LINES 16 +// Define in the Critical Section function on what to wait. +// +typedef enum { + DoneAndRefDrained, + Done, + Immediate +} EWaitOn; + +typedef enum { + ssOne = 0, + ssTwo, + ssThree, + ssFour, +} TSubSequencesNumber; + +#define MAX_PHASE_IN_FINE_ADJUSTMENT 64 +#pragma pack() + +#define SKX_PCKG_TYPE 4 //CMD_CTL_DELAY_H + +#define CHIP_IOGPDLY_PSECS SKX_PCKG_TYPE + +// +// Chip specific section of the struct CPU_CSR_ACCESS_VAR +// +#define CPU_CSR_ACCESS_VAR_CHIP \ + + +typedef enum { + TYPE_SCF_BAR = 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + + +// Output structures based on scope +#define MAX_BITS 72 + +#endif // _memhostchipcommon_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h new file mode 100644 index 0000000000..5e68cab7c5 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memregs_h +#define _memregs_h + +#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes + +#endif // _memregs_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..3f444664b0 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h @@ -0,0 +1,26 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#include "DataTypes.h" + +#define INT32_MIN (0x80000000) +#ifndef INT32_MAX //INT32_MAX->Already defined +#define INT32_MAX (0x7FFFFFFF) +#endif +#define INT16_MIN (0x8000) +#define INT16_MAX (0x7FFF) + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h new file mode 100644 index 0000000000..00882a17e6 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h @@ -0,0 +1,71 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include <UsraAccessApi.h> + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmwar Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; ///< “MCFG”. Signature For this Table + UINT32 Length; ///< Length, in bytes, include base address allocation structures. + UINT8 Revision; ///< "1" + UINT8 SegMax; ///< The Maximum number of Segments + UINT16 ValidSegMap; ///< Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; ///< Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; ///< Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; ///< PCI Segment Group Number. Default is 0. + UINT8 StartBus; ///< Start PCI Bus number decoded by the host bridge + UINT8 EndBus; ///< End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; ///< The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; ///< First Arrary of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h new file mode 100644 index 0000000000..082c6effd5 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h @@ -0,0 +1,80 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _printf_h +#define _printf_h + +#include "DataTypes.h" + +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MAJOR 0xCF +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MINOR 0x01 + +#define TAB_STOP 4 +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMON_PREFIX_ZERO 0x08 +#define LONG_TYPE 0x10 + +#define INT_SIGNED 0x20 +#define COMA_TYPE 0x40 +#define LONG_LONG_TYPE 0x80 +#define TO_UPPER 0x100 + +#define CHAR_CR 0x0d +#define CHAR_LF 0x0a + +// +// ANSI Escape sequences for color +// +#define ANSI_FOREGROUND_BLACK 30 +#define ANSI_FOREGROUND_RED 31 +#define ANSI_FOREGROUND_GREEN 32 +#define ANSI_FOREGROUND_YELLOW 33 +#define ANSI_FOREGROUND_BLUE 34 +#define ANSI_FOREGROUND_MAGENTA 35 +#define ANSI_FOREGROUND_CYAN 36 +#define ANSI_FOREGROUND_WHITE 37 + +#define ANSI_BACKGROUND_BLACK 40 +#define ANSI_BACKGROUND_RED 41 +#define ANSI_BACKGROUND_GREEN 42 +#define ANSI_BACKGROUND_YELLOW 43 +#define ANSI_BACKGROUND_BLUE 44 +#define ANSI_BACKGROUND_MAGENTA 45 +#define ANSI_BACKGROUND_CYAN 46 +#define ANSI_BACKGROUND_WHITE 47 + +#define ANSI_ATTRIBUTE_OFF 0 +#define ANSI_ATTRIBUTE_BOLD 1 +#define ANSI_ATTRIBUTE_UNDERSCORE 4 +#define ANSI_ATTRIBUTE_BLINK 5 +#define ANSI_ATTRIBUTE_REVERSE 7 +#define ANSI_ATTRIBUTE_CONCEAL 8 + +#ifndef INT32_MAX +#define INT32_MAX 0x7fffffffU +#endif + +#ifndef va_start +typedef INT8 * va_list; +#define _INTSIZEOF(n) ((sizeof (n) + sizeof (UINT32) - 1) &~(sizeof (UINT32) - 1)) +#define va_start(ap, v) (ap = (va_list) & v + _INTSIZEOF (v)) +#define va_arg(ap, t) (*(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t))) +#define va_end(ap) (ap = (va_list) 0) +#endif + +#define ISDIGIT(_c) (((_c) >= '0') && ((_c) <= '9')) +#define ISHEXDIGIT(_c) (((_c) >= 'a') && ((_c) <= 'f')) + +#endif // _printf_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h new file mode 100644 index 0000000000..c3b6693a0b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h @@ -0,0 +1,142 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _syshost_h +#define _syshost_h +//#define CCMRC 1 + + +#define RC_SIM_FASTCADB 0 + + + +// +// Host reset states (0-7 are definable) +// +typedef enum BootMode { + NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc. + // Some of these MRC specific init routines can be skipped based on MRC input params + // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc). + S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3 + // init and be optimized for speed. +} BootMode; + + +typedef struct sysHost SYSHOST, *PSYSHOST; + +#include "DataTypes.h" +#include "SysHostChipCommon.h" +#include "Printf.h" +#include "PlatformHost.h" +#include "CpuHost.h" +#include "MemHost.h" +#include "KtiHost.h" +#include "UsbDebugPort.h" + +#include "SysRegs.h" +#include "IioPlatformData.h" + +// +// ------------------------------------- +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:24] = Major revision number +// [23:16] = Minor revision number +// [15:8] = Release Candidate number +// +#define CCMRC_REVISION 0x00500000 + +#define SUCCESS 0 + +#define SDBG_MIN BIT0 +#define SDBG_MAX BIT1 +#define SDBG_TRACE BIT2 +#define SDBG_MEM_TRAIN BIT3 + SDBG_MAX +#define SDBG_TST BIT4 +#define SDBG_CPGC BIT5 +#define SDBG_RCWRITETAG BIT6 +#define SDBG_REG_ACCESS BIT6 // Displays all register accesses. +#define SDBG_MINMAX SDBG_MIN + SDBG_MAX + +#define SDBG_BUF_ENABLE 1 +#define SDBG_BUF_DISABLE 0 +#define SDBG_BUF_EN_DEFAULT SDBG_BUF_DISABLE // Default disable + +#define SDBG_PIPE_ENABLE 1 +#define SDBG_PIPE_DISABLE 0 +#define SDBG_PIPE_DEFAULT SDBG_PIPE_DISABLE + +#define SDBG_PIPE_COMPRESS_ENABLE 1 +#define SDBG_PIPE_COMPRESS_DISABLE 0 +#define SDBG_PIPE_COMPRESS_DEFAULT SDBG_PIPE_COMPRESS_DISABLE + + +// +// ----------------------------------------------------------------------------- +// Variable structures +// + +// +// Warning log +// +#define MAX_LOG 64 + +#define USB_BUF_LIMIT (4096-160) +#define USB_BUF_SIZE (USB_BUF_LIMIT + 160) + +// +// System previous boot error structure +// +#define MC_BANK_STATUS_REG 1 +#define MC_BANK_ADDRESS_REG 2 +#define MC_BANK_MISC_REG 3 + +#define MSR_LOG_VALID BIT31 +#define MSR_LOG_UC BIT29 +#define MSR_LOG_EN BIT28 + +// Bit definitions for commonSetup.options +// ; PROMOTE_WARN_EN enables warnings to be treated as fatal error +// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be treated as fatal error +// ; HALT_ON_ERROR_EN enables errors to loop forever +#define PROMOTE_WARN_EN BIT0 +#define PROMOTE_MRC_WARN_EN BIT1 +#define HALT_ON_ERROR_EN BIT2 + + +// ----------------------------------------------------------------------------- +// + +// +// Handle assertions with RC_ASSERT +// +#if defined(SIM_BUILD) || defined(IA32) || defined (HEADLESS_MRC) + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + DebugPrintRc (host, 0xFF, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + FatalError (host, majorCode, minorCode);\ + } + +#else + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + CpuCsrAccessError (host, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + } + +#endif + + +#endif // _syshost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h new file mode 100644 index 0000000000..2b0685674f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYSHOST_CHIP_COMMON_H_ +#define _SYSHOST_CHIP_COMMON_H_ + +#ifndef SEGMENT_ACCESS +#define SEGMENT_ACCESS +#endif + +// +// Steppings +// +#define A0_REV 0x00 + +//TODO:Need to remove the old ones. Keep for noe to allow building +#define CPU_HSX 0 +#define CPU_IVT 1 +#define CPU_BDX 2 +#define CPU_SKX 0 + +// Defines for socketType +// +#define SOCKET_2S 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 + +// +// CpuPciAccess +// +#define READ_ACCESS 0 +#define WRITE_ACCESS 1 + +#pragma pack(1) + +typedef union { + struct { + UINT32 Bit0:1; + UINT32 Bit1:1; + UINT32 Bit2:1; + UINT32 Bit3:1; + UINT32 Bit4:1; + UINT32 Bit5:1; + UINT32 Bit6:1; + UINT32 Bit7:1; + UINT32 Bit8:1; + UINT32 Bit9:1; + UINT32 Bit10:1; + UINT32 Bit11:1; + UINT32 Bit12:1; + UINT32 Bit13:1; + UINT32 Bit14:1; + UINT32 Bit15:1; + UINT32 Bit16:1; + UINT32 Bit17:1; + UINT32 Bit18:1; + UINT32 Bit19:1; + UINT32 Bit20:1; + UINT32 Bit21:1; + UINT32 Bit22:1; + UINT32 Bit23:1; + UINT32 Bit24:1; + UINT32 Bit25:1; + UINT32 Bit26:1; + UINT32 Bit27:1; + UINT32 Bit28:1; + UINT32 Bit29:1; + UINT32 Bit30:1; + UINT32 Bit31:1; + } Bits; + UINT32 Data; +} DUMMY_REG; + +#pragma pack() + +// +// System previous boot error structure +// +#define MAX_PREV_BOOT_ERR_ENTRIES 15 + + +#endif // _SYSHOST_CHIP_COMMON_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h new file mode 100644 index 0000000000..565d13db60 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _sysregs_h +#define _sysregs_h + +#include "DataTypes.h" + +#ifndef BIT0 +#define BIT0 1 +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) +#endif +#ifndef BIT10 +#define BIT10 (1 << 10) +#define BIT11 (1 << 11) +#define BIT12 (1 << 12) +#define BIT13 (1 << 13) +#define BIT14 (1 << 14) +#define BIT15 (1 << 15) +#define BIT16 (1 << 16) +#define BIT17 (1 << 17) +#define BIT18 (1 << 18) +#define BIT19 (1 << 19) +#define BIT20 (1 << 20) +#define BIT21 (1 << 21) +#define BIT22 (1 << 22) +#define BIT23 (1 << 23) +#define BIT24 (1 << 24) +#define BIT25 (1 << 25) +#define BIT26 (1 << 26) +#define BIT27 (1 << 27) +#define BIT28 (1 << 28) +#define BIT29 (1 << 29) +#define BIT30 (1 << 30) +#define BIT31 (UINT32) (1 << 31) +#endif + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif + +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-x) : (x)) +#endif +// +// disable compiler warning to use bit fields on unsigned short/long types +// +#ifdef _MSC_VER +#pragma warning(disable : 4214) +#endif + +#endif // _sysregs_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h new file mode 100644 index 0000000000..e6d9d37ba9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h @@ -0,0 +1,324 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _USB_DEBUG_PORT_INTERNAL_H +#define _USB_DEBUG_PORT_INTERNAL_H + +#include "DataTypes.h" + +#define PCI_VENDOR_ID_OFFSET 0x00 +#define PCI_DEVICE_ID_OFFSET 0x02 +#define PCI_COMMAND_OFFSET 0x04 +#define PCI_PRIMARY_STATUS_OFFSET 0x06 +#define PCI_REVISION_ID_OFFSET 0x08 +#define PCI_CLASSCODE_OFFSET 0x09 +#define PCI_SUBCLASSCODE_OFFSET 0x0A +#define PCI_BASECLASSCODE_OFFSET 0x0B // Base Class Code Register +#define PCI_CACHELINE_SIZE_OFFSET 0x0C +#define PCI_LATENCY_TIMER_OFFSET 0x0D +#define PCI_HEADER_TYPE_OFFSET 0x0E +#define PCI_BIST_OFFSET 0x0F +#define PCI_BASE_ADDRESSREG_OFFSET 0x10 +#define PCI_CARDBUS_CIS_OFFSET 0x28 +#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id +#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C +#define PCI_SID_OFFSET 0x2E // SubSystem ID +#define PCI_SUBSYSTEM_ID_OFFSET 0x2E +#define PCI_EXPANSION_ROM_BASE 0x30 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 +#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register +#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register +#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register +#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register + +#define PCI_CLASS_SERIAL 0x0C +#define PCI_CLASS_SERIAL_USB 0x03 + +#define IS_BIT_SET(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) != 0) +#define IS_BIT_CLEAR(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) == 0) + +#define SET_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue |= (UINT32)(BitMask); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_AND_SET_R32_BIT(Register, BitMask, Value) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + RegisterValue |= (UINT32)(Value); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define SET_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue |= (UINT16)(BitMask); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define CLR_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue &= (UINT16)(~(BitMask)); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define SET_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue |= (UINT8)(BitMask); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define CLR_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue &= (UINT8)(~(BitMask)); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define PCI_CLASS_SERIAL_USB_EHCI 0x20 +#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A + +#define PCI_USB2_SBRN_OFFSET 0x60 +#define PCI_PRIMARY_BUS_NUMBER_OFFSET 0x18 +#define PCI_SECONDARY_BUS_NUMBER_OFFSET 0x19 +#define PCI_SUBORDINATE_BUS_NUMBER_OFFSET 0x1A + +#define PCI_BRIDGE_MBASE_OFFSET 0x20 +#define PCI_BRIDGE_MLIMIT_OFFSET 0x22 + +#define PCI_EHCI_DEFAULT_BUS_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEVICE_NUMBER 0x1D +#define PCI_EHCI_DEFAULT_FUNCTION_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEBUG_CAPID_OFFSET 0x58 +#define PCI_EHCI_DEFAULT_DEBUG_BASE_OFFSET 0x5A + +// +// USB PIDs +// +#define USB2_PID_TOKEN_OUT 0xE1 +#define USB2_PID_TOKEN_IN 0x69 +#define USB2_PID_TOKEN_SOF 0xA5 +#define USB2_PID_TOKEN_SETUP 0x2D + +#define USB2_PID_DATA0 0xC3 +#define USB2_PID_DATA1 0x4B +#define USB2_PID_DATA2 0x87 +#define USB2_PID_MDATA 0x0F + +#define USB2_PID_HANDSHAKE_ACK 0xD2 +#define USB2_PID_HANDSHAKE_NAK 0x5A +#define USB2_PID_HANDSHAKE_STALL 0x1E +#define USB2_PID_HANDSHAKE_NYET 0x96 + +#define USB2_PID_SPECIAL_PRE 0x3C +#define USB2_PID_SPECIAL_ERR 0x3C +#define USB2_PID_SPECIAL_SPLIT 0x78 +#define USB2_PID_SPECIAL_PING 0xB4 +#define USB2_PID_SPECIAL_RESERVED 0xF0 + +// +// USB2 Debug Port Register +// +#define USB2_DEBUG_PORT_STATUS_OWNER 0x40000000 +#define USB2_DEBUG_PORT_STATUS_ENABLED 0x10000000 +#define USB2_DEBUG_PORT_STATUS_DONE 0x00010000 +#define USB2_DEBUG_PORT_STATUS_INUSE 0x00000400 +#define USB2_DEBUG_PORT_STATUS_EXCEPTION 0x00000380 +#define USB2_DEBUG_PORT_STATUS_ERROR 0x00000040 +#define USB2_DEBUG_PORT_STATUS_GO 0x00000020 +#define USB2_DEBUG_PORT_STATUS_WRITE 0x00000010 +#define USB2_DEBUG_PORT_STATUS_LENGTH 0x0000000F + +#define USB2_DEBUG_PORT_DEFAULT_ADDRESS 127 + +#define USB2_DEBUG_PORT_DEVICE_BUFFER_MAX 8 + +typedef struct _USB2_DEBUG_PORT_REGISTER { + UINT32 ControlStatus; + UINT8 TokenPid; + UINT8 SendPid; + UINT8 ReceivedPid; + UINT8 Reserved1; + UINT8 DataBuffer[USB2_DEBUG_PORT_DEVICE_BUFFER_MAX]; + UINT8 UsbEndPoint; + UINT8 UsbAddress; + UINT8 Reserved2; + UINT8 Reserved3; +}USB2_DEBUG_PORT_REGISTER; + +typedef struct _USB2_EHCI_CAPABILITY_REGISTER { + UINT8 CapLength; + UINT8 Reserved; + UINT16 HciVersion; + UINT32 HcsParams; + UINT32 HccParams; + UINT32 HcspPortRoute; +}USB2_EHCI_CAPABILITY_REGISTER; + +#define USB2_EHCI_USBCMD_RUN 0x00000001 +#define USB2_EHCI_USBCMD_RESET 0x00000002 + +#define USB2_EHCI_USBSTS_HC_HALTED 0x00001000 + +#define USB2_EHCI_PORTSC_PORT_OWNER 0x00002000 +#define USB2_EHCI_PORTSC_PORT_POWER 0x00001000 +#define USB2_EHCI_PORTSC_PORT_RESET 0x00000100 +#define USB2_EHCI_PORTSC_PORT_SUSPEND 0x00000080 +#define USB2_EHCI_PORTSC_PORT_ENABLED 0x00000004 + +typedef struct _USB2_EHCI_OPERATIONAL_REGISTER { + UINT32 UsbCommand; + UINT32 UsbStatus; + UINT32 UsbInterruptEnable; + UINT32 UsbFrameIndex; + UINT32 SegmentSelector; + UINT32 FrameListBaseAddress; + UINT32 NextAsyncListAddress; + UINT32 Reserved[9]; + UINT32 ConfigFlag; + UINT32 PortSc[0x0F]; +}USB2_EHCI_OPERATIONAL_REGISTER; + +#define USB2_DEBUG_PORT_DRIVER_BUFFER_MAX USB2_DEBUG_PORT_DEVICE_BUFFER_MAX * 2 + +typedef struct _USB2_DEBUG_PORT_INSTANCE { + + UINT32 EhciCapRegister; + UINT32 EhciOpRegister; + UINT32 PortSc; + UINT32 DebugRegister; + + BOOLEAN Ready; + + UINT8 PciBusNumber; + UINT8 PciDeviceNumber; + UINT8 PciDeviceFunction; + + UINT8 Reserved1; + UINT8 BarIndex; + UINT16 BarOffset; + + UINT32 PortBase; + UINT8 PortNumber; + UINT8 PortAddress; + UINT8 ReadEndpoint; + UINT8 WriteEndpoint; + + UINT8 ReadEndpointDataToggle; + UINT8 WriteEndpointDataToggle; + UINT8 Reserved2[2]; + + INT32 TempDataLength; + INT32 TempDataIndex; + UINT8 TempData[USB2_DEBUG_PORT_DRIVER_BUFFER_MAX]; +}USB2_DEBUG_PORT_INSTANCE; + +// +// Setup Packet +// +// Data phase transfer direction +// +#define USB2_REQUEST_TYPE_HOST_TO_DEVICE 0x00 +#define USB2_REQUEST_TYPE_DEVICE_TO_HOST 0x80 + +// +// Type +// +#define USB2_REQUEST_TYPE_STANDARD 0x00 +#define USB2_REQUEST_TYPE_CLASS 0x20 +#define USB2_REQUEST_TYPE_VENDOR 0x40 + +// +// Recipient +// +#define USB2_REQUEST_TYPE_DEVICE 0x00 +#define USB2_REQUEST_TYPE_INTERFACE 0x01 +#define USB2_REQUEST_TYPE_ENDPOINT 0x02 +#define USB2_REQUEST_TYPE_OTHER 0x03 + +// +// Request +// +#define USB2_REQUEST_GET_STATUS 0x00 +#define USB2_REQUEST_CLEAR_FEATURE 0x01 +#define USB2_REQUEST_SET_FEATURE 0x03 +#define USB2_REQUEST_SET_ADDRESS 0x05 +#define USB2_REQUEST_GET_DESCRIPTOR 0x06 +#define USB2_REQUEST_SET_DESCRIPTOR 0x07 +#define USB2_REQUEST_GET_CONFIGURATION 0x08 +#define USB2_REQUEST_SET_CONFIGURATION 0x09 +#define USB2_REQUEST_GET_INTERFACE 0x0A +#define USB2_REQUEST_SET_INTERFACE 0x11 + +// +// Descriptor Types +// +#define USB2_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB2_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB2_DESCRIPTOR_TYPE_STRING 0x03 +#define USB2_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB2_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB2_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB2_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB2_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB2_DESCRIPTOR_TYPE_OTG 0x09 +#define USB2_DESCRIPTOR_TYPE_DEBUG 0x0A + +// +// Standard Feature Selectors +// +#define USB2_FEATURE_DEVICE_REMOTE_WAKEUP 0x01 +#define USB2_FEATURE_ENDPOINT_HALT 0x00 +#define USB2_FEATURE_TEST_MODE 0x02 +#define USB2_FEATURE_OTG_B_HNP_ENABLE 0x03 +#define USB2_FEATURE_OTG_A_HNP_SUPPORT 0x04 +#define USB2_FEATURE_OTG_A_ALT_HNP_SUPPORT 0x05 +#define USB2_FEATURE_DEBUG_MODE 0x06 + +typedef struct _USB2_SETUP_PACKET { + UINT8 RequestType; + UINT8 Request; + UINT8 Value[2]; + UINT16 Index; + UINT16 Length_; +}USB2_SETUP_PACKET; + +typedef struct _USB2_DEBUG_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 DebugInEndpoint; + UINT8 DebugOutEndpoint; +}USB2_DEBUG_DESCRIPTOR_TYPE; + +typedef struct _USB2_ENDPOINT_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 EndpointAddress; + UINT8 Attributes; + UINT16 MaxPacketSize; + UINT8 Interval; +}USB2_ENDPOINT_DESCRIPTOR_TYPE; + +#endif /* _USB_DEBUG_PORT_H */ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h new file mode 100644 index 0000000000..54e8fb7351 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h @@ -0,0 +1,21 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _mem_defaults_h +#define _mem_defaults_h + +#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created + +#define PPM_AUTO 0xFF + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h new file mode 100644 index 0000000000..747e6c2b5d --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h @@ -0,0 +1,87 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _mem_platform_h +#define _mem_platform_h + +#include "DataTypes.h" + +#ifdef SERIAL_DBG_MSG +#define MRC_TRACE 1 +#endif + + +// +// Compatible BIOS Data Structure +// +#define BDAT_SUPPORT 0 //Memory Data Schema 4 and RMT Schema 5 of BDAT 4.0 + +// +// QR support +// +#define QR_DIMM_SUPPORT 1 + +// +// Define to enable DIMM margin checking +// +#define MARGIN_CHECK 1 + +// +// Define to enable SODIMM module support +// +#define SODIMM_SUPPORT 1 + +// +// Define to enable ME UMA support +// +//#define ME_SUPPORT_FLAG 1 + +// +// Define to enable XMP +// +#define XMP_SUPPORT 1 + +// Define to enable DEBUG for NVMCTLR (LATE CMD CLK) +//#define DEBUG_LATECMDCLK 1 + +// Define to enable MRS Stacking +//#define MRS_STACKING 1 + +// +// Define to max ppr +// +#define MAX_PPR_ADDR_ENTRIES 20 + +// +//------------------------------------- +// DVP Platform-specific defines +//------------------------------------- +// +#ifdef DVP_PLATFORM +#endif // DVP_PLATFORM + +// +//------------------------------------- +// CRB Platform-specific defines +//------------------------------------- +// +#ifdef CRB_PLATFORM +#endif // CRB_PLATFORM + +#ifndef MAX_HA +#define MAX_HA 2 // Number of Home Agents / IMCs +#endif + +//SKX_TODO: I have removed NonPOR elements, I will delete this line before submit + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h new file mode 100644 index 0000000000..89a5dc80e9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h @@ -0,0 +1,176 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _platformhost_h
+#define _platformhost_h
+
+//
+// MAX Number of Processor supported by Intel platform
+//
+#include "MaxSocket.h"
+
+#ifndef MAX_CORE
+#define MAX_CORE 28 // Maximum cores per CPU (SKX)
+#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU
+#endif
+
+#ifndef MAX_KTI_PORTS
+#define MAX_KTI_PORTS 3 // Max KTI ports supported
+#endif
+
+//
+// Post Package Repair
+//
+#define PPR_SUPPORT 1
+#define MAX_PPR_ADDR_ENTRIES 20
+
+// Select one of the following platforms
+//#define DVP_PLATFORM 1 // DVP
+//
+#define CRB_PLATFORM 1 // SRP
+
+#ifndef DVP_PLATFORM
+#ifndef CRB_PLATFORM
+
+/*
+ MULTIPLE_PLATFORM_SUPPORT should be defined when the user KNOWS that inputs
+ (the ones defined to zero under this flag below) are given via sysSetup structure
+*/
+#define MULTIPLE_PLATFORM_SUPPORT 1
+#endif
+#endif
+
+#if !defined(SILENT_MODE)
+#define SERIAL_DBG_MSG 1
+#endif
+#define RC_BEGIN_END_DEBUG_HOOKS
+
+//#define HW_EMULATION 1
+
+#define SOFT_SDV_FLAG BIT0 // flag to indicate running on Soft SDV
+#define VP_FLAG BIT1 // flag to indicate running on VP
+#define SIMICS_FLAG BIT2 // flag to indicate running on Simics
+#define RTL_SIM_FLAG BIT3 // flag to indicate running on the RTL simulator
+#define QUIET_MODE BIT16 // flag to enable minimal debug messages
+#define RANDOM_TRAINING BIT17 // flag to enable random training responses from Simics
+#define FORCE_SETUP BIT18 // flag to force BIOS setup
+#define DDR_TRAINING_EN BIT19 // flag to tell the BIOS to execute DDR training
+//
+// Enumerated Platform SMBUS controllers
+//
+
+#define PLATFORM_SMBUS_CONTROLLER_PROCESSOR 0
+#define PLATFORM_SMBUS_CONTROLLER_PCH 1
+
+#ifndef TypePlatformDefault
+//
+// Platform types - if not defined already
+//
+typedef enum {
+ TypeNeonCityEPRP = 0x00,
+ TypeNeonCityEPECB,
+ TypeOpalCitySTHI,
+ TypePurleyLBGEPDVP,
+ TypeWolfPass,
+ TypeBuchananPass,
+ TypeCrescentCity,
+ TypeHedtEV,
+ TypeHedtCRB,
+ TypeLightningRidgeEXRP,
+ TypeLightningRidgeEXECB1,
+ TypeLightningRidgeEXECB2,
+ TypeLightningRidgeEXECB3,
+ TypeLightningRidgeEXECB4,
+ TypeLightningRidgeEX8S1N,
+ TypeLightningRidgeEX8S2N,
+ TypeBarkPeak,
+ TypeKyanite,
+ TypeSawtoothPass, // We need to keep the value of TypeSawtoothPass unchanged
+ TypeNeonCityFPGA,
+ TypeOpalCityFPGA,
+ TypeYubaCityRP
+} EFI_PLATFORM_TYPE;
+
+
+#define TypePlatformUnknown 0xFF
+#define TypePlatformMin TypeNeonCityEPRP
+#define TypePlatformMax TypeYubaCityRP
+#define TypePlatformDefault TypeNeonCityEPRP
+#define TypePlatformOpalCityPPV 6
+#define TypePlatformOpalCityCPV 7
+#endif
+
+
+//
+// Enumerated Unique Platform Component IDs
+//
+#define NOT_INITIALIZED 0
+#define SPD 1
+#define DCP_ISL9072X 2
+#define DCP_AD5247 3
+#define MTS 4 //TSOD
+#define RSTPLD 5
+#define NO_DEV 0xFFFF
+//
+// Default I/O base addresses
+//
+#define REG_ACPI_BASE_ADDRESS 0x40
+#define PM_ENABLE 0x44
+#define IO_REG_ACPI_TIMER 0x08
+#define REG_GPIO_BASE_ADDRESS 0x48
+#ifdef MINIBIOS_BUILD
+#define ICH_PMBASE_ADDR 0x500
+#endif //MINIBIOS_BUILD
+
+//
+//#define ICH_GPIOBASE_ADDR 0x500
+#define ICH_SMBBASE_ADDR 0x700
+#define R_PCH_SMBUS_PCICMD 0x04
+#define B_PCH_SMBUS_PCICMD_IOSE BIT0
+#define R_PCH_SMBUS_BASE 0x20
+#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0
+#define R_PCH_SMBUS_HOSTC 0x40
+#define B_PCH_SMBUS_HOSTC_HST_EN BIT0
+//
+#define SERIAL_DBG_COM_BASE 0x3F8
+//
+// Platform SMBUS definitions
+//
+#define SMB_SEG0 0
+#define SMB_SEG1 1
+#define SMB_SEG2 2
+#define SMB_SEG3 3
+
+//
+// Major Warning codes
+//
+#define WARN_SETUP_INVALID 0x01
+#define WARN_MINOR_WILDCARD 0xff
+
+#define SMB_TIMEOUT 100000 // 100 ms
+#define SMB_RETRY_LIMIT 20 // 2 sec
+#define CATCHALL_TIMEOUT 100000 // 100 ms
+
+#define FOUR_GB_MEM 0x40 // 4GB in 64MB units
+#define MAX_MEM_ADDR 0x40000 // 46-bit addressing (256MB units)
+#define HIGH_GAP 1 // High gap (256 MB units)
+#define MMCFG_SIZE 256*1024*1024 // MMCFG Size (in Bytes)
+#define MMIOH_SIZE 0 // MMIOH Size Granularity per stack (1GB, (1<<(2*size)))
+#define DEFAULT_COM_PORT 0x80
+//
+//-----------------------------------------------------------------------------
+//
+#include "MemPlatform.h"
+
+#endif // _platformhost_h
+
diff --git a/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf b/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf new file mode 100644 index 0000000000..572fa786c9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf @@ -0,0 +1,73 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseCsrToPcieLibNull
+ FILE_GUID = 848E908E-BD11-428E-94F9-7A0EEFCD37A6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CsrToPcieLib
+
+## {848E908E-BD11-428E-94F9-7A0EEFCD37A6}
+##{ 0x848e908e, 0xbd11, 0x428e, { 0x94, 0xf9, 0x7a, 0xe, 0xef, 0xcd, 0x37, 0xa6 } };
+
+
+[Sources]
+ CsrToPcieLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+
+
diff --git a/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c b/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c new file mode 100644 index 0000000000..cbdc4a8672 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c @@ -0,0 +1,47 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/CsrToPcieAddress.h> + +////////////////////////////////////////////////////////////////////////// +// +// USRA Csr to PCIE Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + USRA_ADDRESS PcieAddress; + USRA_ZERO_ADDRESS_TYPE(PcieAddress, AddrTypePCIE); + return 0; +}; + diff --git a/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c new file mode 100644 index 0000000000..ca10f59d7e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c @@ -0,0 +1,95 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/MmPciBaseLib.h> + +#include <PiDxe.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Protocol/SiliconRegAccess.h> +#include <Library/DebugLib.h> +#include <Guid/DxeServices.h> +#include <Library/UefiLib.h> + +USRA_PROTOCOL *mPciUsra = NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +DxeMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra == NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status = gBS->LocateProtocol (&gUsraProtocolGuid, NULL, (VOID **)&mPciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra != NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf new file mode 100644 index 0000000000..bf09f99bfc --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf @@ -0,0 +1,66 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSmmMmPciLib
+ FILE_GUID = 28D4B296-EFCE-46E4-8DA7-DA54D17AEDEF
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MmPciLib
+ CONSTRUCTOR = DxeMmPciLibConstructor
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+[Sources]
+ DxeMmPciBaseLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ UefiLib
+ IoLib
+ DebugLib
+ PcdLib
+
+[Protocols]
+ gEfiSmmCpuIo2ProtocolGuid
+ gUsraProtocolGuid ## CONSUMES
+
+[Depex]
+ gUsraProtocolGuid
\ No newline at end of file diff --git a/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c new file mode 100644 index 0000000000..913e90809f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/SmmServicesTableLib.h> +#include <Protocol/SiliconRegAccess.h> +#include <Library/DebugLib.h> +#include <Library/UefiLib.h> + +USRA_PROTOCOL *mPciUsra = NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SmmMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra == NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status = gSmst->SmmLocateProtocol (&gUsraProtocolGuid, NULL, &mPciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra != NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf new file mode 100644 index 0000000000..8202be4831 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf @@ -0,0 +1,66 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSmmMmPciLib
+ FILE_GUID = 96D31DB6-CCFC-4B80-B850-FC070806CA78
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MmPciLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmMmPciLibConstructor
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+[Sources]
+ SmmMmPciBaseLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ UefiBootServicesTableLib
+ IoLib
+ DebugLib
+ UefiLib
+ SmmServicesTableLib
+
+[Protocols]
+ gEfiSmmCpuIo2ProtocolGuid
+ gUsraProtocolGuid ## CONSUMES
+
+[Depex.common.DXE_SMM_DRIVER]
+ gEfiSmmCpuIo2ProtocolGuid
+
diff --git a/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.c b/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.c new file mode 100644 index 0000000000..6381cb30eb --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.c @@ -0,0 +1,75 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/MmPciBaseLib.h> + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + + if (!FeaturePcdGet (PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static PcdPciExpressBaseAddress + // + return ((UINTN) (PcdGet64(PcdPciExpressBaseAddress)) + (UINTN) (Address.Attribute.RawData32[0] & 0x00ffffff)); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + + if (!FeaturePcdGet(PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static PcdPciExpressBaseAddress + // + return ((UINTN)(PcdGet64(PcdPciExpressBaseAddress)) + (UINTN)(Address.Attribute.RawData32[0] & 0x00ffffff)); +} diff --git a/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.inf b/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.inf new file mode 100644 index 0000000000..4c3411b4ff --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/MmPciBaseLib/MmPciBaseLib.inf @@ -0,0 +1,61 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiDxeSmmMmPciLib
+ FILE_GUID = AA112999-A913-4F96-A9C4-28BFA0BD83EE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MmPciLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+[Sources]
+ MmPciBaseLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+ [Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ SiliconAccessLib
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+[Pcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.c b/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.c new file mode 100644 index 0000000000..23c05347d5 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.c @@ -0,0 +1,189 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/PcieAddress.h> +#include <Library/BaseMemoryLib/MemLibInternals.h> + +#pragma optimize ("",off) +////////////////////////////////////////////////////////////////////////// +// +// Pcie Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +PCIE_MMCFG_TABLE_TYPE mMmcfgTable =\ + { + { + {'M', 'C', 'F', 'G'}, // Signature + 0x00000090, // Length + 0x01, // Revision + 0x08, // The Maximum number of Segments + 0x00FF, // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0000, // Segment 0 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + } +}; +// +// Segment 1 ~ 7 +// +PCIE_MMCFG_BASE_ADDRESS_TYPE mMmcfgAddr[] = \ +{ + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0001, // Segment 1 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0002, // Segment 2 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0003, // Segment 3 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0004, // Segment 4 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0005, // Segment 5 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0006, // Segment 6 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0007, // Segment 7 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + } +}; + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param[in] MmcfgTable A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type + @param[in] NumOfSeg Number of Segments in the table + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg + ) +{ + UINT32 MmcfgTableSize; + PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable; + + union { + UINTN D64; + UINT32 D32[2]; + } Data; + + Data.D32[0] = Data.D32[1] = 0; + MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSeg * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE)); + + HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr); + ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr)); + + InternalMemCopyMem(HobMmcfgTable, MmcfgTable, PcdGetSize (PcdPcieMmcfgTablePtr)); + MmcfgTable->Header.Length = MmcfgTableSize; + if((MmcfgTable->MmcfgBase[0].BaseAddressL == 0) && (MmcfgTable->MmcfgBase[0].BaseAddressH == 0)) + { + // + // The first time default should be the PcdPciExpressBaseAddress + // + Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + HobMmcfgTable->MmcfgBase[0].BaseAddressL = Data.D32[0]; + HobMmcfgTable->MmcfgBase[0].BaseAddressH = Data.D32[1]; + }; + return 0; +}; + +/** + This Lib return PCIE MMCFG Base Address + + @param[in] Address A pointer of the address of the USRA Address Structure for PCIE type + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ) +{ + PCIE_MMCFG_TABLE_TYPE *MmcfgTable=NULL; + UINTN SegMmcfgBase; + + if(Address->Attribute.HostPtr == 0) + { + MmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr); + if(MmcfgTable->Header.Length == 0) + { + // + // if it is not valid MMCFG pointer, initialize it to use the predefined default MMCFG Table + // + SetPcieSegMmcfgTable(&mMmcfgTable, PcdGet32 (PcdNumOfPcieSeg)); + } + } + else + { + ((UINT32*)&MmcfgTable)[0] = Address->Attribute.HostPtr; + } + ASSERT(Address->Pcie.Seg < MmcfgTable->Header.SegMax); + ASSERT( (1<<Address->Pcie.Seg) & MmcfgTable->Header.ValidSegMap); + return SegMmcfgBase = *((UINTN*)(&MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressL)); +}; + diff --git a/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.inf b/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.inf new file mode 100644 index 0000000000..d88e65e593 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/PcieAddressLib/PcieAddressLib.inf @@ -0,0 +1,72 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieAddrLib
+ FILE_GUID = 45F8D21D-0584-4119-BC0A-65815CDDAE21
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PcieAddrLib
+
+
+[Sources]
+ PcieAddressLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ BaseMemoryLib
+
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+ gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg
+
+
diff --git a/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/CsrAccess.c b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/CsrAccess.c new file mode 100644 index 0000000000..b8f2663591 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/CsrAccess.c @@ -0,0 +1,124 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "UsraAccessLib.h" + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CsrGetPcieAlignAddress (Global, Virtual, Address, AlignedAddress); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribute.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + + UINT64 Data; + UINT8 WidthTable[] = {1,2,4,8}; + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attribute.AccessWidth]); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, &Data); + + return RETURN_SUCCESS; +} diff --git a/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/PcieAccess.c b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/PcieAccess.c new file mode 100644 index 0000000000..5af2c5953a --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/PcieAccess.c @@ -0,0 +1,360 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "UsraAccessLib.h" + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] = { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 0, // UsraWidthFifo8 + 0, // UsraWidthFifo16 + 0, // UsraWidthFifo32 + 0, // UsraWidthFifo64 + 1, // UsraWidthFill8 + 2, // UsraWidthFill16 + 4, // UsraWidthFill32 + 8 // UsraWidthFill64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] = { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 1, // UsraWidthFifo8 + 2, // UsraWidthFifo16 + 4, // UsraWidthFifo32 + 8, // UsraWidthFifo64 + 0, // UsraWidthFill8 + 0, // UsraWidthFill16 + 0, // UsraWidthFill32 + 0 // UsraWidthFill64 +}; + + +/** + This API gets the Pcie address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + INTN MmCfgBase; + + MmCfgBase = GetPcieSegMmcfgBaseAddress(Address); + // TODO: add Error Check for NULL later + *AlignedAddress = MmCfgBase + (UINTN)(Address->Attribute.RawData32[0] & 0x0fffffff); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + return RETURN_SUCCESS; +} + +/** + Check parameters to PcieBlkRegisterRead() function request. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + UsraWidth64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The parameters for this request pass the checks. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +RETURN_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN USRA_ACCESS_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer == NULL) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >= UsraWidthMaximum) { + return RETURN_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >= UsraWidthFifo8 && Width <= UsraWidthFifo64) { + Count = 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width = (USRA_ACCESS_WIDTH) (Width & 0x03); + if (!MmioOperation && (Width == UsraWidth64)) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) { + return RETURN_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the maximum + // allowed address. The maximum address implied by the parameters passed in is + // Address + Size * Count. If the following condition is met, then the transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count == 0) { + if (Address > Limit) { + return RETURN_UNSUPPORTED; + } + } else { + MaxCount = RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return RETURN_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return RETURN_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.) + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) { + return RETURN_UNSUPPORTED; + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCheckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 ReadCount = Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, ReadCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Address->Attribute.AccessWidth]; + OutStride = mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer = Buffer; ReadCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, ReadCount--) { + UsraRegAlignedRead((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress(NULL, 0, Address, &AlignedAddress); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribute.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCheckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 WriteCount = Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, WriteCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Address->Attribute.AccessWidth]; + OutStride = mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer = Buffer; WriteCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, WriteCount--) { + UsraRegAlignedWrite((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) { + if(Address->Attribute.S3Enable) { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)(Address->Attribute.AccessWidth & 0x03), (UINT64)AlignedAddress, 1, (VOID *)UINT8Buffer); + } + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + UINT64 Data; + UINT8 WidthTable[] = {1,2,4,8}; + + PcieRegisterRead(Address, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attribute.AccessWidth]); + PcieRegisterWrite(Address, &Data); + + return RETURN_SUCCESS; +} + diff --git a/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.c b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.c new file mode 100644 index 0000000000..d01d69192f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.c @@ -0,0 +1,241 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "UsraAccessLib.h" + +GET_ALLIGNED_ACCESS_ADDRESS mAccessAddrPtr[] = +{ + &GetPcieAccessAddress, // AddrTypePCIE + &GetPcieAccessAddress, // AddrTypePCIEBLK + &GetCsrAccessAddress, // AddrTypeCSR +}; + +REGISTER_READ mRegisterReadPtr[] = +{ + &PcieRegisterRead, // AddrTypePCIE + &PcieBlkRegisterRead, // AddrTypePCIEBLK + &CsrRegisterRead, // AddrTypeCSR +}; + +REGISTER_WRITE mRegisterWritePtr[] = +{ + &PcieRegisterWrite, // AddrTypePCIE + &PcieBlkRegisterWrite, // AddrTypePCIEBLK + &CsrRegisterWrite, // AddrTypeCSR +}; + +REGISTER_MODIFY mRegisterModifyPtr[] = +{ + &PcieRegisterModify, // AddrTypePCIE + &PcieRegisterModify, // AddrTypePCIEBLK + &CsrRegisterModify, // AddrTypeCSR +}; + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + *((UINT8*)Buffer) = MmioRead8 (AlignedAddress); + break; + case UsraWidth16: + *((UINT16*)Buffer) = MmioRead16 (AlignedAddress); + break; + case UsraWidth32: + *((UINT32*)Buffer) = MmioRead32 (AlignedAddress); + break; + default: + *((UINT64*)Buffer) = MmioRead64 (AlignedAddress); + break; + } + + return RETURN_SUCCESS; +}; + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + MmioWrite8 (AlignedAddress,*((UINT8*)Buffer)); + break; + case UsraWidth16: + MmioWrite16 (AlignedAddress,*((UINT16*)Buffer)); + break; + case UsraWidth32: + MmioWrite32 (AlignedAddress,*((UINT32*)Buffer)); + break; + default: + MmioWrite64 (AlignedAddress, *((UINT64*)Buffer)); + break; + } + return RETURN_SUCCESS; +} + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be performed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +) +{ + union{ + UINT64 QW; + UINT8 Byte[8]; + } Buffer; + UINT8 AndData[8], OrData[8], i; + + Buffer.QW = *Data; + for(i=0;i<NumOfByte;i++) + { + if (AndBuffer == NULL) + ((UINT8*)AndData)[i] = 0xff; + else + AndData[i] = ((UINT8*)AndBuffer)[i]; + if (OrBuffer == NULL) + ((UINT8*)OrData)[i] = 0; + else + OrData[i] = ((UINT8*)OrBuffer)[i]; + Buffer.Byte[i] = (Buffer.Byte[i] & AndData[i]) | OrData[i]; + } + + *Data = Buffer.QW; +} + +////////////////////////////////////////////////////////////////////////// +// +// USRA Hardware Access Library +// +////////////////////////////////////////////////////////////////////////// + +/** + This API gets the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +GetRegisterAddress ( + IN USRA_ADDRESS *Address + ) +{ + UINTN AlignedAddress; + + mAccessAddrPtr[Address->Attribute.AddrType] (NULL, 0, Address, &AlignedAddress); + + return AlignedAddress; +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + return mRegisterReadPtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + return mRegisterWritePtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + return mRegisterModifyPtr[Address->Attribute.AddrType] (Address, AndBuffer, OrBuffer); +}; diff --git a/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.h b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.h new file mode 100644 index 0000000000..f41c0a548e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.h @@ -0,0 +1,263 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __USRA_ACCESS_LIB_H__ +#define __USRA_ACCESS_LIB_H__ + +#include <Base.h> +#include <Library/UsraAccessApi.h> +#include <Library/CsrToPcieAddress.h> +#include <Library/PcieAddress.h> +#include <Library/BaseLib.h> +#include <Library/IoLib.h> +#include <Library/S3BootScriptLib.h> + +// +// Get Aligned Access Address +// +typedef + VOID + (EFIAPI *GET_ALLIGNED_ACCESS_ADDRESS) (VOID*, BOOLEAN, USRA_ADDRESS*, UINTN*); + +// +// Register Read +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_READ) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_WRITE) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_MODIFY) (USRA_ADDRESS *, VOID *, VOID *); + +/** + This API get the Pcie address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be performed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +); + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.inf b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.inf new file mode 100644 index 0000000000..ecb5eccf44 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/UsraAccessLib/UsraAccessLib.inf @@ -0,0 +1,68 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconAccessLib
+ FILE_GUID = 6CF9B31D-C5E9-4F5F-8030-78883D66CDF0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconAccessLib
+
+## { 0x6cf9b31d, 0xc5e9, 0x4f5f, { 0x80, 0x30, 0x78, 0x88, 0x3d, 0x66, 0xcd, 0xf0 } };
+
+[Sources]
+ UsraAccessLib.c
+ CsrAccess.c
+ PcieAccess.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ S3BootScriptLib
+ CsrToPcieLib
+ PcieAddrLib
+ HobLib
+ BaseLib
+ IoLib
+
+[Guids]
+
+[FeaturePcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3
+
+
+
diff --git a/Silicon/Intel/PurleyRcPkg/RcCommonLib.dsc b/Silicon/Intel/PurleyRcPkg/RcCommonLib.dsc new file mode 100644 index 0000000000..9ef96c2c1d --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/RcCommonLib.dsc @@ -0,0 +1,20 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.common]
+ PcieAddrLib|$(RC_PKG)/Library/PcieAddressLib/PcieAddressLib.inf
+ SiliconAccessLib|$(RC_PKG)/Library/UsraAccessLib/UsraAccessLib.inf
+ CsrToPcieLib|$(RC_PKG)/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf
+ PcieAddrLib|$(RC_PKG)/Library/PcieAddressLib/PcieAddressLib.inf
+ MmPciLib|$(RC_PKG)/Library/MmPciBaseLib/MmPciBaseLib.inf
diff --git a/Silicon/Intel/PurleyRcPkg/RcDxeLib.dsc b/Silicon/Intel/PurleyRcPkg/RcDxeLib.dsc new file mode 100644 index 0000000000..a52e22a58b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/RcDxeLib.dsc @@ -0,0 +1,27 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.common.DXE_DRIVER]
+ MmPciLib|$(RC_PKG)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ MmPciLib|$(RC_PKG)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf
+
+[LibraryClasses.common.DXE_SMM_DRIVER]
+ MmPciLib|$(RC_PKG)/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+ MmPciLib|$(RC_PKG)/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf
+
+[LibraryClasses.X64.UEFI_APPLICATION]
diff --git a/Silicon/Intel/PurleyRcPkg/RcPeiLib.dsc b/Silicon/Intel/PurleyRcPkg/RcPeiLib.dsc new file mode 100644 index 0000000000..6503f1799a --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/RcPeiLib.dsc @@ -0,0 +1,14 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
diff --git a/Silicon/Intel/PurleyRcPkg/RcPkg.dec b/Silicon/Intel/PurleyRcPkg/RcPkg.dec new file mode 100644 index 0000000000..90cc93288b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/RcPkg.dec @@ -0,0 +1,96 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PurleyRcPkg
+ PACKAGE_GUID = 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+ Include/Library
+ Library/BaseMemoryCoreLib/Core
+ Library/BaseMemoryCoreLib/Core/Include
+ Library/BaseMemoryCoreLib/Platform/Purley/Include
+
+ Library/BaseMemoryCoreLib/Chip/Skx
+ Library/BaseMemoryCoreLib/Chip/Skx/Include
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup
+
+[LibraryClasses]
+
+ ## @libraryclass Provides services to get the silicon access library.
+ SiliconAccessLib|Include/Library/UsraAccessApi.h
+
+ ## @libraryclass Provides services to convert CSR to PCIE address library.
+ CsrToPcieLib|PurleyRcPkg/Include/Library/CsrToPcieAddress.h
+
+ ## @libraryclass Provides services to PCIE address library.
+ PcieAddrLib|PurleyRcPkg/Include/Library/PcieAddress.h
+
+ ## @libraryclass Provides services to get PCI Express Address Base library.
+ MmPciLib|PurleyRcPkg/Include/Library/MmPciBaseLib.h
+
+ ## @libraryclass Provides services to get the silicon access library.
+ UsraLib|PurleyRcPkg/Include/Protocol/SiliconRegAccess.h
+
+[Guids]
+
+ ## Include/Guid/CpRcPkgTokenSpace.h
+ gEfiCpRcPkgTokenSpaceGuid = { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
+
+[Protocols]
+ ## Include/Protocol/SiliconRegAccess.h
+ gUsraProtocolGuid = { 0xfd480a76, 0xb134, 0x4ef7, { 0xad, 0xfe, 0xb0, 0xe0, 0x54, 0x63, 0x98, 0x7 }}
+
+[PPIs]
+ ## Include/Protocol/SiliconRegAccess.h
+ gUsraPpiGuid = { 0x90766a99, 0x9ca5, 0x44de, { 0x94, 0xda, 0xdc, 0xc1, 0xd2, 0xd6, 0xda, 0x1f }}
+
+[PcdsFeatureFlag]
+ ## Indicate whether USRA can support S3
+ gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012
+
+ ## Use this feature PCD to support Single PCIe segment with static MMCFG Base
+ gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014
+
+ ## enable/disable USRA trace.
+ gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016
+
+ ## enable/disable Quiesce feature.
+ gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017
+
+[PcdsFixedAtBuild]
+ ## Indicates the size of each PCIE segment
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010
+ gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013
+ ## Indicates the max nested level
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018
+ ## Maximum number of sockets supported for this firmware build.
+ # This PCD should be used sparingly. Dynamic allocation of data and
+ # dynamic control flows are preferred over using this PCD for static
+ # data allocation and control.
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019
+
+[PcdsDynamicEx]
+ ## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 |
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011
+ gEfiCpRcPkgTokenSpaceGuid.PcdRcRevision|0|UINT32|0x00000015
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+
+
|