diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-08-11 16:26:37 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-08-14 16:04:38 +0800 |
| commit | be52a15fc34fcdd34bbe645abdde98aed35b73e2 (patch) | |
| tree | ca59433a0c17dd9af06b15aba96c2566d5a5929c | |
| parent | 24726ac8c67cc8defd5555984df3b8ad006ec387 (diff) | |
| download | edk2-platforms-be52a15fc34fcdd34bbe645abdde98aed35b73e2.tar.xz | |
KabylakeOpenBoardPkg: Enable performance build.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
| -rw-r--r-- | Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc | 3 | ||||
| -rw-r--r-- | Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 9 |
2 files changed, 12 insertions, 0 deletions
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc index 84528eb79d..3fd015bd6d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc @@ -131,3 +131,6 @@ !else
gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
!endif
+
+ gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable|FALSE
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index d9b6ac4e6a..c39c1335d9 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -34,6 +34,11 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
[PcdsFixedAtBuild.common]
+!if gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+!endif
+
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
@@ -180,6 +185,10 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+!if gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
+!endif
+
[PcdsDynamicDefault]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFCF0070
|