Separate FspMT.

Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Brett Wang  <brett.wang@intel.com>
Cc: Daocheng Bu <daocheng.bu@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>

6 files changed, 29 insertions, 19 deletions

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf
index 283c4e9b40..4133c6649f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf
@@ -44,7 +44,9 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                     = 0x00500
 SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                       = 0x000A0000  #

 SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset              = 0x005A0000  # Flash addr (0xFFDA0000)

 SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize                = 0x00060000  #

-SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset             = 0x00600000  # Flash addr (0xFFE00000)

-SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize               = 0x000C0000  #

+SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMOffset              = 0x00600000  # Flash addr (0xFFE00000)

+SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMSize                = 0x000BC000  #

+SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTOffset              = 0x006BC000  # Flash addr (0xFFEBC000)

+SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTSize                = 0x00004000  #

 SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset         = 0x006C0000  # Flash addr (0xFFEC0000)

 SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize           = 0x00140000  #

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index 0be9b995c1..5933c71053 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -166,10 +166,15 @@ gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformModuleTokenSpace
 # FSP_S Section

 FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd

 

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize

-# FSP_M & T Section

-FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M_T.fd

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMSize

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMSize

+# FSP_M Section

+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd

+

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTSize

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTSize

+# FSP_T Section

+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd

 

 gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize

 gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 150218e6e0..6a11cfa0a8 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -121,7 +121,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
   gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80

   !endif

 

-  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFE5F000

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000

   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000

 

   ## Specifies max supported number of Logical Processors.

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat
index 56ce0e1f93..c8620322fa 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat
@@ -60,9 +60,7 @@ if exist %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc attrib -r %WORKSPACE
 

 cd %WORKSPACE%

 

-copy /y /b %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_T.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M_T.fd

-@REM prefix pad.bin file which adds 0xC bytes of data (Note: Section will add 4 bytes of SECTION Header). This is done to align the FSP Header to 16 bytes

-copy /y /b %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\pad.bin+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd

+copy /y /b %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_T.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased.fd

 :SkipPatchFspBinFvsBaseAddress

 

 

diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index 71a2afcb93..c4ee28c768 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -108,12 +108,15 @@ gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000000|UINT
 gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x00000000|UINT32|0x2000001A

 gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x00000000|UINT32|0x2000001B

 

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTBase|0x00000000|UINT32|0x20000021

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize|0x00000000|UINT32|0x20000022

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset|0x00000000|UINT32|0x20000023

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x20000024

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x20000025

-gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x20000026

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|0x20000021

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0x20000022

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32|0x20000023

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32|0x20000024

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|0x20000025

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT32|0x20000026

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x20000027

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x20000028

+gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x20000029

 

 gMinPlatformModuleTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000000

 gMinPlatformModuleTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT32|0x80000001

diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
index 1558ad9bc3..7fe26df1d9 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
@@ -57,12 +57,14 @@ flashBase = long(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
 # Based on Build Target, select the section in the FlashMap file

 flashmap = data

 

-# Get FSP-S & FSP-M-T offset & calculate the base

+# Get FSP-S & FSP-M & FSP-T offset & calculate the base

 for line in flashmap.split("\n"):

   if "PcdFlashFvFspSOffset" in line:

     fspSBaseOffset = long(line.split("=")[1].split()[0], 16)

-  if "PcdFlashFvFspMTOffset" in line:

+  if "PcdFlashFvFspMOffset" in line:

     fspMBaseOffset = long(line.split("=")[1].split()[0], 16)

+  if "PcdFlashFvFspTOffset" in line:

+    fspTBaseOffset = long(line.split("=")[1].split()[0], 16)

 file.close()

 

 #

@@ -80,7 +82,7 @@ for line in FsptInfo[1].split("\n"):
 # Calculate FSP-S/M/T base address, to which re-base has to be done

 fspSBaseAddress = flashBase + fspSBaseOffset + fvOffset

 fspMBaseAddress = flashBase + fspMBaseOffset

-fspTBaseAddress = flashBase + fspMBaseOffset + fspMSize

+fspTBaseAddress = flashBase + fspTBaseOffset

 

 #

 # Re-base FSP bin file to new address and save it as fspBinFileRebased using SplitFspBin.py