diff options
author | Jaben Carsey <jaben.carsey@intel.com> | 2014-08-22 17:02:11 +0000 |
---|---|---|
committer | jcarsey <jcarsey@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-22 17:02:11 +0000 |
commit | f056e4c18047e9a0157a915175d07afbd8b8c581 (patch) | |
tree | e737d285a90563dec768c4ce8d99cbad56a4b879 | |
parent | c173a7b9d6f239e3a002f4e9c37db98a8f98f771 (diff) | |
download | edk2-platforms-f056e4c18047e9a0157a915175d07afbd8b8c581.tar.xz |
ShellPkg: Update 'pci' command for updated class codes
This updated the strings to be compliant with PCI CODE AND ID ASSIGNMENT SPECIFICATION 1.5.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15885 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r-- | ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c | 448 |
1 files changed, 430 insertions, 18 deletions
diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c index 25c3dfef6c..75c56ecb86 100644 --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c @@ -1,7 +1,7 @@ /** @file
Main file for Pci shell Debug1 function.
- Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
+ (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.
Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -20,7 +20,6 @@ #include <IndustryStandard/Acpi.h>
#include "Pci.h"
-#define PCI_CLASS_STRING_LIMIT 54
//
// Printable strings for Pci class code
//
@@ -63,9 +62,19 @@ PCI_CLASS_ENTRY PCISubClass_0e[]; PCI_CLASS_ENTRY PCISubClass_0f[];
PCI_CLASS_ENTRY PCISubClass_10[];
PCI_CLASS_ENTRY PCISubClass_11[];
+PCI_CLASS_ENTRY PCISubClass_12[];
+PCI_CLASS_ENTRY PCISubClass_13[];
+PCI_CLASS_ENTRY PCIPIFClass_0100[];
PCI_CLASS_ENTRY PCIPIFClass_0101[];
+PCI_CLASS_ENTRY PCIPIFClass_0105[];
+PCI_CLASS_ENTRY PCIPIFClass_0106[];
+PCI_CLASS_ENTRY PCIPIFClass_0107[];
+PCI_CLASS_ENTRY PCIPIFClass_0108[];
+PCI_CLASS_ENTRY PCIPIFClass_0109[];
PCI_CLASS_ENTRY PCIPIFClass_0300[];
PCI_CLASS_ENTRY PCIPIFClass_0604[];
+PCI_CLASS_ENTRY PCIPIFClass_0609[];
+PCI_CLASS_ENTRY PCIPIFClass_060b[];
PCI_CLASS_ENTRY PCIPIFClass_0700[];
PCI_CLASS_ENTRY PCIPIFClass_0701[];
PCI_CLASS_ENTRY PCIPIFClass_0703[];
@@ -76,6 +85,8 @@ PCI_CLASS_ENTRY PCIPIFClass_0803[]; PCI_CLASS_ENTRY PCIPIFClass_0904[];
PCI_CLASS_ENTRY PCIPIFClass_0c00[];
PCI_CLASS_ENTRY PCIPIFClass_0c03[];
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];
PCI_CLASS_ENTRY PCIPIFClass_0e00[];
//
@@ -173,6 +184,16 @@ PCI_CLASS_ENTRY gClassStringList[] = { PCISubClass_11
},
{
+ 0x12,
+ L"Processing Accelerators",
+ PCISubClass_12
+ },
+ {
+ 0x13,
+ L"Non-Essential Instrumentation",
+ PCISubClass_13
+ },
+ {
0xff,
L"Device does not fit in any defined classes",
PCIBlankEntry
@@ -221,8 +242,8 @@ PCI_CLASS_ENTRY PCISubClass_00[] = { PCI_CLASS_ENTRY PCISubClass_01[] = {
{
0x00,
- L"SCSI controller",
- PCIBlankEntry
+ L"SCSI",
+ PCIPIFClass_0100
},
{
0x01,
@@ -245,6 +266,31 @@ PCI_CLASS_ENTRY PCISubClass_01[] = { PCIBlankEntry
},
{
+ 0x05,
+ L"ATA controller with ADMA interface",
+ PCIPIFClass_0105
+ },
+ {
+ 0x06,
+ L"Serial ATA controller",
+ PCIPIFClass_0106
+ },
+ {
+ 0x07,
+ L"Serial Attached SCSI (SAS) controller ",
+ PCIPIFClass_0107
+ },
+ {
+ 0x08,
+ L"Non-volatile memory subsystem",
+ PCIPIFClass_0108
+ },
+ {
+ 0x09,
+ L"Universal Flash Storage (UFS) controller ",
+ PCIPIFClass_0109
+ },
+ {
0x80,
L"Other mass storage controller",
PCIBlankEntry
@@ -283,6 +329,21 @@ PCI_CLASS_ENTRY PCISubClass_02[] = { PCIBlankEntry
},
{
+ 0x05,
+ L"WorldFip controller",
+ PCIBlankEntry
+ },
+ {
+ 0x06,
+ L"PICMG 2.14 Multi Computing",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"InfiniBand controller",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other network controller",
PCIBlankEntry
@@ -339,6 +400,11 @@ PCI_CLASS_ENTRY PCISubClass_04[] = { PCIBlankEntry
},
{
+ 0x03,
+ L"Mixed mode device",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other multimedia device",
PCIBlankEntry
@@ -420,6 +486,21 @@ PCI_CLASS_ENTRY PCISubClass_06[] = { PCIBlankEntry
},
{
+ 0x09,
+ L"Semi-transparent PCI-to-PCI bridge",
+ PCIPIFClass_0609
+ },
+ {
+ 0x0A,
+ L"InfiniBand-to-PCI host bridge",
+ PCIBlankEntry
+ },
+ {
+ 0x0B,
+ L"Advanced Switching to PCI host bridge",
+ PCIPIFClass_060b
+ },
+ {
0x80,
L"Other bridge type",
PCIBlankEntry
@@ -453,6 +534,16 @@ PCI_CLASS_ENTRY PCISubClass_07[] = { PCIPIFClass_0703
},
{
+ 0x04,
+ L"GPIB (IEEE 488.1/2) controller",
+ PCIBlankEntry
+ },
+ {
+ 0x05,
+ L"Smart Card",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other communication device",
PCIBlankEntry
@@ -491,6 +582,21 @@ PCI_CLASS_ENTRY PCISubClass_08[] = { PCIBlankEntry
},
{
+ 0x05,
+ L"SD Host controller",
+ PCIBlankEntry
+ },
+ {
+ 0x06,
+ L"IOMMU",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"Root Complex Event Collector",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other system peripheral",
PCIBlankEntry
@@ -609,8 +715,8 @@ PCI_CLASS_ENTRY PCISubClass_0b[] = { PCI_CLASS_ENTRY PCISubClass_0c[] = {
{
0x00,
- L"Firewire(IEEE 1394)",
- PCIPIFClass_0c03
+ L"IEEE 1394",
+ PCIPIFClass_0c00
},
{
0x01,
@@ -625,7 +731,7 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = { {
0x03,
L"USB",
- PCIPIFClass_0c00
+ PCIPIFClass_0c03
},
{
0x04,
@@ -638,6 +744,26 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = { PCIBlankEntry
},
{
+ 0x06,
+ L"InfiniBand",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"IPMI",
+ PCIPIFClass_0c07
+ },
+ {
+ 0x08,
+ L"SERCOS Interface Standard (IEC 61491)",
+ PCIBlankEntry
+ },
+ {
+ 0x09,
+ L"CANbus",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other bus type",
PCIBlankEntry
@@ -657,8 +783,8 @@ PCI_CLASS_ENTRY PCISubClass_0d[] = { },
{
0x01,
- L"Consumer IR controller",
- PCIBlankEntry
+ L"",
+ PCIPIFClass_0d01
},
{
0x10,
@@ -666,6 +792,26 @@ PCI_CLASS_ENTRY PCISubClass_0d[] = { PCIBlankEntry
},
{
+ 0x11,
+ L"Bluetooth",
+ PCIBlankEntry
+ },
+ {
+ 0x12,
+ L"Broadband",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"Ethernet (802.11a – 5 GHz)",
+ PCIBlankEntry
+ },
+ {
+ 0x21,
+ L"Ethernet (802.11b – 2.4 GHz)",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other type of wireless controller",
PCIBlankEntry
@@ -692,26 +838,31 @@ PCI_CLASS_ENTRY PCISubClass_0e[] = { PCI_CLASS_ENTRY PCISubClass_0f[] = {
{
- 0x00,
+ 0x01,
L"TV",
PCIBlankEntry
},
{
- 0x01,
+ 0x02,
L"Audio",
PCIBlankEntry
},
{
- 0x02,
+ 0x03,
L"Voice",
PCIBlankEntry
},
{
- 0x03,
+ 0x04,
L"Data",
PCIBlankEntry
},
{
+ 0x80,
+ L"Other satellite communication controller",
+ PCIBlankEntry
+ },
+ {
0x00,
NULL,
/* null string ends the list */NULL
@@ -748,6 +899,21 @@ PCI_CLASS_ENTRY PCISubClass_11[] = { PCIBlankEntry
},
{
+ 0x01,
+ L"Performance Counters",
+ PCIBlankEntry
+ },
+ {
+ 0x10,
+ L"Communications synchronization plus time and frequency test/measurement ",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"Management card",
+ PCIBlankEntry
+ },
+ {
0x80,
L"Other DAQ & SP controllers",
PCIBlankEntry
@@ -759,9 +925,68 @@ PCI_CLASS_ENTRY PCISubClass_11[] = { }
};
+PCI_CLASS_ENTRY PCISubClass_12[] = {
+ {
+ 0x00,
+ L"Processing Accelerator",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCISubClass_13[] = {
+ {
+ 0x00,
+ L"Non-Essential Instrumentation Function",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
//
// Programming Interface entries
//
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {
+ {
+ 0x00,
+ L"SCSI controller",
+ PCIBlankEntry
+ },
+ {
+ 0x11,
+ L"SCSI storage device SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x12,
+ L"SCSI controller SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x13,
+ L"SCSI storage device and controller SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x21,
+ L"SCSI storage device SOP using NVMe",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
{
0x00,
@@ -930,6 +1155,106 @@ PCI_CLASS_ENTRY PCIPIFClass_0101[] = { }
};
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {
+ {
+ 0x20,
+ L"Single stepping",
+ PCIBlankEntry
+ },
+ {
+ 0x30,
+ L"Continuous operation",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"AHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"Serial Storage Bus",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"Obsolete",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"NVMHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"NVM Express",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"UFSHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0300[] = {
{
0x00,
@@ -966,6 +1291,42 @@ PCI_CLASS_ENTRY PCIPIFClass_0604[] = { }
};
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {
+ {
+ 0x40,
+ L"Primary PCI bus side facing the system host processor",
+ PCIBlankEntry
+ },
+ {
+ 0x80,
+ L"Secondary PCI bus side facing the system host processor",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {
+ {
+ 0x00,
+ L"Custom",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"ASI-SIG Defined Portal",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0700[] = {
{
0x00,
@@ -1198,12 +1559,40 @@ PCI_CLASS_ENTRY PCIPIFClass_0904[] = { PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
{
0x00,
- L"Universal Host Controller spec",
+ L"",
PCIBlankEntry
},
{
0x10,
- L"Open Host Controller spec",
+ L"Using 1394 OpenHCI spec",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
+ {
+ 0x00,
+ L"UHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x10,
+ L"OHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"EHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x30,
+ L"xHCI",
PCIBlankEntry
},
{
@@ -1223,15 +1612,38 @@ PCI_CLASS_ENTRY PCIPIFClass_0c00[] = { }
};
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {
{
0x00,
- L"",
+ L"SMIC",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"Keyboard Controller Style",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"Block Transfer",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {
+ {
+ 0x00,
+ L"Consumer IR controller",
PCIBlankEntry
},
{
0x10,
- L"Using 1394 OpenHCI spec",
+ L"UWB Radio controller",
PCIBlankEntry
},
{
|