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authorniruiyu <niruiyu@6f19259b-4bc3-4df7-8a09-765794883524>2013-04-27 02:03:58 +0000
committerniruiyu <niruiyu@6f19259b-4bc3-4df7-8a09-765794883524>2013-04-27 02:03:58 +0000
commit41f3989842ae4f2eff46e0eadde5b2e37d0c99bc (patch)
tree516d206847a3dc78d9f3464e9591d9fdee46831d
parent9d00d20ed40fb56d8b5a8e1a3f7ae3e491ceaf94 (diff)
downloadedk2-platforms-41f3989842ae4f2eff46e0eadde5b2e37d0c99bc.tar.xz
Fix the bug which incorrectly programs the 64bit base address register in the PCI to PCI bridge.
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Elvin Li <elvin.li@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14318 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r--MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c46
1 files changed, 42 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index e17f4bae44..d8d988cbfc 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -1,7 +1,7 @@
/** @file
PCI resouces support functions implemntation for PCI Bus module.
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1472,7 +1472,14 @@ ProgramPpbApperture (
case PPB_BAR_0:
case PPB_BAR_1:
- PciIo->Pci.Write (
+ switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
+
+ PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@@ -1480,9 +1487,40 @@ ProgramPpbApperture (
&Address
);
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
+
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
+ Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
+
+ Address32 = (UINT32) RShiftU64 (Address, 32);
+
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
+
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
+
+ default:
+ break;
+ }
break;
case PPB_IO_RANGE: