diff options
| author | jyao1 <jyao1> | 2014-08-04 06:34:41 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-04 06:34:41 +0000 |
| commit | a0e0fb6d9fa37f430c483c04e6333e3c32308a56 (patch) | |
| tree | 8fc6ea28d5eaaff48c91b515ca9be225efae9523 | |
| parent | 4e07e87fe4c12718101b592bf8c88a9447fc0965 (diff) | |
| download | edk2-platforms-a0e0fb6d9fa37f430c483c04e6333e3c32308a56.tar.xz | |
Clean up code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed off by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15743 6f19259b-4bc3-4df7-8a09-765794883524
5 files changed, 15 insertions, 4 deletions
diff --git a/IntelFspPkg/FspSecCore/SecMain.c b/IntelFspPkg/FspSecCore/SecMain.c index 22706c8a8b..971a3a1b82 100644 --- a/IntelFspPkg/FspSecCore/SecMain.c +++ b/IntelFspPkg/FspSecCore/SecMain.c @@ -41,6 +41,7 @@ UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL; @param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
+ @param[in] PeiCoreEntry Pei Core entrypoint.
@return This function never returns.
@@ -50,7 +51,8 @@ EFIAPI SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
- IN VOID *BootFirmwareVolume
+ IN VOID *BootFirmwareVolume,
+ IN UINTN PeiCoreEntry
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@@ -119,7 +121,7 @@ SecStartup ( //
// Call PeiCore Entry
//
- PeiCore = (PEI_CORE_ENTRY)(*(UINTN *)((&BootFirmwareVolume) + 1));
+ PeiCore = (PEI_CORE_ENTRY)(PeiCoreEntry);
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//
diff --git a/IntelFspPkg/FspSecCore/SecMain.h b/IntelFspPkg/FspSecCore/SecMain.h index 4dfbc850b3..a9b48d1205 100644 --- a/IntelFspPkg/FspSecCore/SecMain.h +++ b/IntelFspPkg/FspSecCore/SecMain.h @@ -107,6 +107,7 @@ InitializeFloatingPointUnits ( @param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
+ @param[in] PeiCoreEntry Pei Core entrypoint.
@return This function never returns.
@@ -116,7 +117,8 @@ EFIAPI SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
- IN VOID *BootFirmwareVolume
+ IN VOID *BootFirmwareVolume,
+ IN UINTN PeiCoreEntry
);
/**
diff --git a/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c b/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c index f293dc8be8..b370a4ad56 100644 --- a/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c +++ b/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c @@ -244,6 +244,8 @@ FspHobProcess ( LowMemorySize
);
+ S3PeiMemBase = 0;
+ S3PeiMemSize = 0;
Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);
ASSERT_EFI_ERROR (Status);
DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));
diff --git a/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/Fsp.h b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/Fsp.h index 289d6638b0..e145b4eb02 100644 --- a/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/Fsp.h +++ b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/Fsp.h @@ -12,6 +12,9 @@ **/
+#ifndef __FSP_H__
+#define __FSP_H__
+
//
// Fv Header
//
@@ -41,3 +44,5 @@ //
#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
+
+#endif
diff --git a/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecPeiFspPlatformSecLibSample.inf b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecPeiFspPlatformSecLibSample.inf index 09b8036918..7df2abdeac 100644 --- a/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecPeiFspPlatformSecLibSample.inf +++ b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecPeiFspPlatformSecLibSample.inf @@ -52,7 +52,7 @@ Ia32/PeiCoreEntry.asm
Ia32/AsmSaveSecContext.asm
Ia32/Stack.asm
-
+ Ia32/Fsp.h
Ia32/SecEntry.S
Ia32/PeiCoreEntry.S
Ia32/AsmSaveSecContext.S
|