diff options
| author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-05-03 12:30:46 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-07-14 22:36:50 +0100 |
| commit | d61262ca0818842c1c3a32d3a4deb8217aee8580 (patch) | |
| tree | 1022985e88897b7bf0065905b5cb26f9a71fff25 | |
| parent | 455396bda43fbf008811fdd5f549ae60c1cce877 (diff) | |
| download | edk2-platforms-d61262ca0818842c1c3a32d3a4deb8217aee8580.tar.xz | |
Platform,Silicon: import AMD Styx SoC support and platforms
Common files for AMD Overdrive, SoftIron Overdrive 1000
and LeMaker Cello, as well as actual platform support.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
69 files changed, 13116 insertions, 0 deletions
diff --git a/Platform/AMD/License.txt b/Platform/AMD/License.txt new file mode 100644 index 0000000000..ff85835d63 --- /dev/null +++ b/Platform/AMD/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb Binary files differnew file mode 100644 index 0000000000..c8e5fd980b --- /dev/null +++ b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dts new file mode 100644 index 0000000000..4039f66600 --- /dev/null +++ b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -0,0 +1,510 @@ +/*
+ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board
+ *
+ * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
+ compatible = "amd,seattle-overdrive", "amd,seattle";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-controller@e1101000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ reg = <0x0 0xe1110000 0x0 0x1000>,
+ <0x0 0xe112f000 0x0 0x2000>,
+ <0x0 0xe1140000 0x0 0x2000>,
+ <0x0 0xe1160000 0x0 0x2000>;
+ interrupts = <0x1 0x9 0xf04>;
+ ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
+ linux,phandle = <0x1>;
+ phandle = <0x1>;
+
+ v2m@e0080000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x80000 0x0 0x1000>;
+ linux,phandle = <0x4>;
+ phandle = <0x4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0xff04>,
+ <0x1 0xe 0xff04>,
+ <0x1 0xb 0xff04>,
+ <0x1 0xa 0xff04>;
+ };
+
+ smb {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ /*
+ * dma-ranges is 40-bit address space containing:
+ * - GICv2m MSI register is at 0xe0080000
+ * - DRAM range [0x8000000000 to 0xffffffffff]
+ */
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+ clk100mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "adl3clk_100mhz";
+ };
+
+ clk375mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <375000000>;
+ clock-output-names = "ccpclk_375mhz";
+ };
+
+ clk333mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <333000000>;
+ clock-output-names = "sataclk_333mhz";
+ linux,phandle = <0x2>;
+ phandle = <0x2>;
+ };
+
+ clk500mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "pcieclk_500mhz";
+ };
+
+ clk500mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "dmaclk_500mhz";
+ };
+
+ clk250mhz_4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "miscclk_250mhz";
+ linux,phandle = <0xd>;
+ phandle = <0xd>;
+ };
+
+ clk100mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "uartspiclk_100mhz";
+ linux,phandle = <0x3>;
+ phandle = <0x3>;
+ };
+
+ sata0_smmu: smmu@e0200000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0200000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = /* Uses combined intr for both
+ * global and context
+ */
+ <0 332 4>,
+ <0 332 4>;
+ #iommu-cells = <2>;
+ dma-coherent;
+ };
+
+ sata1_smmu: smmu@e0c00000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0c00000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = /* Uses combined intr for both
+ * global and context
+ */
+ <0 331 4>,
+ <0 331 4>;
+ #iommu-cells = <2>;
+ dma-coherent;
+ };
+
+ sata@e0300000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0300000 0x0 0xf0000>;
+ interrupts = <0x0 0x163 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */
+ };
+
+ sata@e0d00000 {
+ status = "disabled";
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0d00000 0x0 0xf0000>;
+ interrupts = <0x0 0x162 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */
+ };
+
+ i2c@e1000000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe1000000 0x0 0x1000>;
+ interrupts = <0x0 0x165 0x4>;
+ clocks = <0xd>;
+ };
+
+ i2c@e0050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe0050000 0x0 0x1000>;
+ interrupts = <0x0 0x154 0x4>;
+ clocks = <0xd>;
+ };
+
+ serial@e1010000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xe1010000 0x0 0x1000>;
+ interrupts = <0x0 0x148 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ ssp@e1020000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1020000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x14a 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ssp@e1030000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1030000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x149 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ num-cs = <0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ sdcard@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3200 3400>;
+ pl022,hierarchy = <0x0>;
+ pl022,interface = <0x0>;
+ pl022,com-mode = <0x0>;
+ pl022,rx-level-trig = <0x0>;
+ pl022,tx-level-trig = <0x0>;
+ };
+ };
+
+ gpio@e1050000 { /* [0 : 7] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe1050000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x166 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0020000 { /* [8 : 15] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0020000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16e 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0030000 { /* [16 : 23] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0030000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16d 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0080000 { /* [24] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0080000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x169 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ccp: ccp@e0100000 {
+ compatible = "amd,ccp-seattle-v1a";
+ reg = <0x0 0xe0100000 0x0 0x10000>;
+ interrupts = <0x0 0x3 0x4>;
+ dma-coherent;
+ amd,zlib-support = <0x1>;
+ };
+
+ pcie: pcie@f0000000 {
+ compatible = "pci-host-ecam-generic";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
+ device_type = "pci";
+ bus-range = <0x0 0x7f>;
+ msi-parent = <0x4>;
+ reg = <0x0 0xf0000000 0x0 0x10000000>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
+ <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
+ <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
+ <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>,
+
+ <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>,
+ <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>,
+ <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>,
+ <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>,
+
+ <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>,
+ <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>,
+ <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>,
+ <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>;
+ dma-coherent;
+ dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
+ ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
+ <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
+ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
+ };
+
+ pcie_smmu: smmu@e0a00000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0a00000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = /* Uses combined intr for both
+ * global and context
+ */
+ <0 333 4>,
+ <0 333 4>;
+ #iommu-cells = <1>;
+ dma-coherent;
+ };
+
+ ccn@0xe8000000 {
+ compatible = "arm,ccn-504";
+ reg = <0x0 0xe8000000 0x0 0x1000000>;
+ interrupts = <0x0 0x17c 0x4>;
+ };
+
+ gwdt@e0bb0000 {
+ status = "disabled";
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0xe0bb0000 0x0 0x10000
+ 0x0 0xe0bc0000 0x0 0x10000>;
+ reg-names = "refresh", "control";
+ interrupts = <0x0 0x151 0x4>;
+ interrupt-names = "ws0";
+ };
+
+ kcs@e0010000 {
+ status = "disabled";
+ compatible = "ipmi-kcs";
+ device_type = "ipmi";
+ reg = <0x0 0xe0010000 0 0x8>;
+ interrupts = <0 389 4>;
+ interrupt-names = "ipmi_kcs";
+ reg-size = <1>;
+ reg-spacing = <4>;
+ };
+
+ clk250mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_dma_250mhz";
+ linux,phandle = <0x5>;
+ phandle = <0x5>;
+ };
+
+ clk250mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_ptp_250mhz";
+ linux,phandle = <0x6>;
+ phandle = <0x6>;
+ };
+
+ clk250mhz_2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_dma_250mhz";
+ linux,phandle = <0x7>;
+ phandle = <0x7>;
+ };
+
+ clk250mhz_3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_ptp_250mhz";
+ linux,phandle = <0x8>;
+ phandle = <0x8>;
+ };
+
+ phy@e1240800 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x143 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0x9>;
+ phandle = <0x9>;
+ };
+
+ phy@e1240c00 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x142 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0xa>;
+ phandle = <0xa>;
+ };
+
+ xgmac0_smmu: smmu@e0600000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0600000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = /* Uses combined intr for both
+ * global and context
+ */
+ <0 336 4>,
+ <0 336 4>;
+ #iommu-cells = <2>;
+ dma-coherent;
+ };
+
+ xgmac1_smmu: smmu@e0800000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0800000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = /* Uses combined intr for both
+ * global and context
+ */
+ <0 335 4>,
+ <0 335 4>;
+ #iommu-cells = <2>;
+ dma-coherent;
+ };
+
+ xgmac@e0700000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
+ interrupts = <0x0 0x145 0x4>,
+ <0x0 0x15a 0x1>,
+ <0x0 0x15b 0x1>,
+ <0x0 0x15c 0x1>,
+ <0x0 0x15d 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 a1 a2 a3 a4 a5];
+ clocks = <0x5 0x6>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0x9>;
+ phy-mode = "xgmii";
+ dma-coherent;
+ iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */
+ linux,phandle = <0xb>;
+ phandle = <0xb>;
+ };
+
+ xgmac@e0900000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
+ interrupts = <0x0 0x144 0x4>,
+ <0x0 0x155 0x1>,
+ <0x0 0x156 0x1>,
+ <0x0 0x157 0x1>,
+ <0x0 0x158 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 b1 b2 b3 b4 b5];
+ clocks = <0x7 0x8>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0xa>;
+ phy-mode = "xgmii";
+ dma-coherent;
+ iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */
+ linux,phandle = <0xc>;
+ phandle = <0xc>;
+ };
+ };
+
+ chosen {
+ stdout-path = "/smb/serial@e1010000";
+ /* Note:
+ * Linux support for pci-probe-only DT is not
+ * stable. Disable this for now and let Linux
+ * take care of the resource assignment.
+ */
+ // linux,pci-probe-only;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ };
+};
diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc new file mode 100644 index 0000000000..f256ffb97a --- /dev/null +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -0,0 +1,762 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE DO_XGBE = 1
+DEFINE NUM_CORES = 8
+DEFINE DO_PSCI = 1
+DEFINE DO_ISCP = 1
+DEFINE DO_KCS = 1
+DEFINE DO_FLASHER = FALSE
+
+ PLATFORM_NAME = Overdrive
+ PLATFORM_GUID = B2296C02-9DA1-4CD1-BD48-4D4F0F1276EB
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Overdrive
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/AMD/OverdriveBoard/OverdriveBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Allow dynamic PCDs
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # ARM PL011 UART Driver
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+ #
+ # PCI support
+ #
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciHostBridgeLib|Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+ #
+ # Styx specific libraries
+ #
+ AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+ AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+ MemoryInitPeiLib|Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ *_*_*_ASL_FLAGS = -tc -li -l -so
+ *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS)
+ *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS)
+
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+ GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ # All pages are cached by default
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+ ## created by ConsplitterDxe. It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle"
+
+ # Number of configured cores
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+ # Declare system memory base
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+ # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+ # that)
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal (Atlas UART)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ # serial port is clocked at 100MHz
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+ #
+ # AMD's B1 based Overdrive has 14 SATA ports across 2 controllers. However,
+ # it appears that Softiron's Overdrive 3000, which is also B1 based, does
+ # not have the second SATA controller enabled, and any attempts to use it
+ # will crash the firmware. So use the first controller only.
+ #
+ gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xffff
+
+ # PCIe Support
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0
+ gArmTokenSpaceGuid.PcdPciBusMax|0x7F
+
+ gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+ ## Use PCI emulation for ATA PassThru
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE
+
+ ## ACPI (no tables < 4GB)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"AMDINC"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20454c5454414553 # SEATTLE
+
+ #
+ # Enable strict image permissions for all images. (This applies
+ # only to images that were built with >= 4 KB section alignment.)
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
+
+ #
+ # Enable NX memory protection for all non-code regions, including OEM and OS
+ # reserved ones, with the exception of LoaderData regions, of which OS loaders
+ # (i.e., GRUB) may assume that its contents are executable.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
+
+!if $(DO_PSCI)
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE
+!endif
+
+!if $(DO_ISCP)
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE
+!endif
+
+ # SMBIOS 3.0 only
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+ # map the stack as non-executable when entering the DXE phase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+!if $(DO_XGBE)
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|TRUE
+
+ gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|0
+ gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|0
+ gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1
+ gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdEthMacA|0x02A1A2A3A4A5
+ gAmdStyxTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5
+
+[PcdsPatchableInModule]
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|TRUE
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|2
+!endif
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x4
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicHii]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ #
+ # Console IO support
+ #
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+ <LibraryClasses>
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ DtPlatformDtbLoaderLib|Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
+ }
+
+ #
+ # PCI support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+!if $(DO_XGBE)
+ #
+ # SNP support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf
+ Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+ }
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <LibraryClasses>
+ NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+ }
+
+ Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Logo/LogoDxe.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+!if $(DO_FLASHER) == TRUE
+ OpenPlatformPkg/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf {
+ <LibraryClasses>
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ }
+!endif
diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf new file mode 100644 index 0000000000..23e57befcd --- /dev/null +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -0,0 +1,415 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00500000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = Platform/AMD/OverdriveBoard/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include Silicon/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+
+ FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+ SECTION RAW = Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb
+ }
+
+ #
+ # PCI support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+!if $(DO_XGBE)
+ #
+ # SNP support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf
+ INF Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ INF Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Logo/LogoDxe.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ INF Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+[FV.STYX_EFI]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ INF Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.Binary]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE Align = Auto |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
+
diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc new file mode 100644 index 0000000000..dc6f3e332c --- /dev/null +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -0,0 +1,700 @@ +#
+# Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE NUM_CORES = 4
+DEFINE DO_KCS = 0
+DEFINE DO_FLASHER = FALSE
+
+ PLATFORM_NAME = Cello
+ PLATFORM_GUID = 77861b3e-74b0-4ff3-8d18-c5ba5803e1bf
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Cello
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/LeMaker/CelloBoard/CelloBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Allow dynamic PCDs
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # ARM PL011 UART Driver
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+ #
+ # PCI support
+ #
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciHostBridgeLib|Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+ #
+ # Styx specific libraries
+ #
+ AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+ AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+ MemoryInitPeiLib|Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ *_*_*_ASL_FLAGS = -tc -li -l -so
+ *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS)
+ *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS)
+
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+ GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ # All pages are cached by default
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+ ## created by ConsplitterDxe. It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"LeMaker Cello"
+
+ # Number of configured cores
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+ # Declare system memory base
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+ # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+ # that)
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal (Atlas UART)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ # serial port is clocked at 100MHz
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+ #
+ # Cello has 2 SATA ports on the first controller.
+ #
+ gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xf
+
+ # PCIe Support
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0
+ gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+ gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+ ## ACPI (no tables < 4GB)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+ #
+ # Enable strict image permissions for all images. (This applies
+ # only to images that were built with >= 4 KB section alignment.)
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
+
+ #
+ # Enable NX memory protection for all non-code regions, including OEM and OS
+ # reserved ones, with the exception of LoaderData regions, of which OS loaders
+ # (i.e., GRUB) may assume that its contents are executable.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
+
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+
+ # SMBIOS 3.0 only
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+ # map the stack as non-executable when entering the DXE phase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x2x2
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicHii]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ #
+ # Console IO support
+ #
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+ <LibraryClasses>
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ DtPlatformDtbLoaderLib|Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
+ }
+
+ #
+ # PCI support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <LibraryClasses>
+ NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+ }
+
+ Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+!ifdef $(RENESAS_XHCI_FW_DIR)
+ OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
+!endif
+
+!if $(DO_FLASHER) == TRUE
+ Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf {
+ <LibraryClasses>
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ }
+!endif
diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.fdf b/Platform/LeMaker/CelloBoard/CelloBoard.fdf new file mode 100644 index 0000000000..c4e6748b6a --- /dev/null +++ b/Platform/LeMaker/CelloBoard/CelloBoard.fdf @@ -0,0 +1,406 @@ +#
+# Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00500000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = Platform/LeMaker/CelloBoard/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include Silicon/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 72b41709-8499-4841-a383-f432de6fce2a
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+
+ FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+ SECTION RAW = Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb
+ }
+
+ #
+ # PCI support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ INF Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ INF Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # Renesas PD720202 XHCI firmware uploader, requires firmware image
+ # in directory $(RENESAS_XHCI_FW_DIR)
+ #
+!ifdef $(RENESAS_XHCI_FW_DIR)
+ INF OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
+ FILE FREEFORM = A059EBC4-D73D-4279-81BF-E4A89308B923 {
+ SECTION RAW = $(RENESAS_XHCI_FW_DIR)/K2013080.mem
+ }
+!endif
+
+[FV.STYX_EFI]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ INF Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.Binary]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE Align = Auto |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
+
diff --git a/Platform/LeMaker/License.txt b/Platform/LeMaker/License.txt new file mode 100644 index 0000000000..ff85835d63 --- /dev/null +++ b/Platform/LeMaker/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Platform/SoftIron/License.txt b/Platform/SoftIron/License.txt new file mode 100644 index 0000000000..ff85835d63 --- /dev/null +++ b/Platform/SoftIron/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb b/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb Binary files differnew file mode 100644 index 0000000000..ba5d494f9f --- /dev/null +++ b/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb diff --git a/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts b/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts new file mode 100644 index 0000000000..d99b48d084 --- /dev/null +++ b/Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts @@ -0,0 +1,434 @@ +/*
+ * DTS file for SoftIron Overdrive 1000, based on AMD Seattle (Rev.B1)
+ *
+ * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "SoftIron Overdrive 1000 (AMD Seattle (Rev.B1))";
+ compatible = "amd,seattle-overdrive", "amd,seattle";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-controller@e1101000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ reg = <0x0 0xe1110000 0x0 0x1000>,
+ <0x0 0xe112f000 0x0 0x2000>,
+ <0x0 0xe1140000 0x0 0x10000>,
+ <0x0 0xe1160000 0x0 0x10000>;
+ interrupts = <0x1 0x9 0xf04>;
+ ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
+ linux,phandle = <0x1>;
+ phandle = <0x1>;
+
+ v2m@e0080000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x80000 0x0 0x1000>;
+ linux,phandle = <0x4>;
+ phandle = <0x4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0xff04>,
+ <0x1 0xe 0xff04>,
+ <0x1 0xb 0xff04>,
+ <0x1 0xa 0xff04>;
+ };
+
+ smb {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ /*
+ * dma-ranges is 40-bit address space containing:
+ * - GICv2m MSI register is at 0xe0080000
+ * - DRAM range [0x8000000000 to 0xffffffffff]
+ */
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+ clk100mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "adl3clk_100mhz";
+ };
+
+ clk375mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <375000000>;
+ clock-output-names = "ccpclk_375mhz";
+ };
+
+ clk333mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <333000000>;
+ clock-output-names = "sataclk_333mhz";
+ linux,phandle = <0x2>;
+ phandle = <0x2>;
+ };
+
+ clk500mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "pcieclk_500mhz";
+ };
+
+ clk500mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "dmaclk_500mhz";
+ };
+
+ clk250mhz_4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "miscclk_250mhz";
+ linux,phandle = <0xd>;
+ phandle = <0xd>;
+ };
+
+ clk100mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "uartspiclk_100mhz";
+ linux,phandle = <0x3>;
+ phandle = <0x3>;
+ };
+
+ sata@e0300000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0300000 0x0 0xf0000>;
+ interrupts = <0x0 0x163 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ };
+
+ sata@e0d00000 {
+ status = "disabled";
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0d00000 0x0 0xf0000>;
+ interrupts = <0x0 0x162 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ };
+
+ i2c@e1000000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe1000000 0x0 0x1000>;
+ interrupts = <0x0 0x165 0x4>;
+ clocks = <0xd>;
+ };
+
+ i2c@e0050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe0050000 0x0 0x1000>;
+ interrupts = <0x0 0x154 0x4>;
+ clocks = <0xd>;
+ };
+
+ serial@e1010000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xe1010000 0x0 0x1000>;
+ interrupts = <0x0 0x148 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ ssp@e1020000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1020000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x14a 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ssp@e1030000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1030000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x149 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ num-cs = <0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ sdcard@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3200 3400>;
+ pl022,hierarchy = <0x0>;
+ pl022,interface = <0x0>;
+ pl022,com-mode = <0x0>;
+ pl022,rx-level-trig = <0x0>;
+ pl022,tx-level-trig = <0x0>;
+ };
+ };
+
+ gpio@e1050000 { /* [0 : 7] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe1050000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x166 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0020000 { /* [8 : 15] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0020000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16e 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0030000 { /* [16 : 23] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0030000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16d 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0080000 { /* [24] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0080000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x169 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ccp: ccp@e0100000 {
+ compatible = "amd,ccp-seattle-v1a";
+ reg = <0x0 0xe0100000 0x0 0x10000>;
+ interrupts = <0x0 0x3 0x4>;
+ dma-coherent;
+ amd,zlib-support = <0x1>;
+ };
+
+ pcie: pcie@f0000000 {
+ compatible = "pci-host-ecam-generic";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ device_type = "pci";
+ bus-range = <0x0 0x7f>;
+ msi-parent = <0x4>;
+ reg = <0x0 0xf0000000 0x0 0x10000000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
+ <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
+ <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
+ <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
+ dma-coherent;
+ dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
+ ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
+ <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
+ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
+ };
+
+ ccn@0xe8000000 {
+ compatible = "arm,ccn-504";
+ reg = <0x0 0xe8000000 0x0 0x1000000>;
+ interrupts = <0x0 0x17c 0x4>;
+ };
+
+ gwdt@e0bb0000 {
+ status = "disabled";
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0xe0bb0000 0x0 0x10000
+ 0x0 0xe0bc0000 0x0 0x10000>;
+ reg-names = "refresh", "control";
+ interrupts = <0x0 0x151 0x4>;
+ interrupt-names = "ws0";
+ };
+
+ kcs@e0010000 {
+ status = "disabled";
+ compatible = "ipmi-kcs";
+ device_type = "ipmi";
+ reg = <0x0 0xe0010000 0 0x8>;
+ interrupts = <0 389 4>;
+ interrupt-names = "ipmi_kcs";
+ reg-size = <1>;
+ reg-spacing = <4>;
+ };
+
+ clk250mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_dma_250mhz";
+ linux,phandle = <0x5>;
+ phandle = <0x5>;
+ };
+
+ clk250mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_ptp_250mhz";
+ linux,phandle = <0x6>;
+ phandle = <0x6>;
+ };
+
+ clk250mhz_2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_dma_250mhz";
+ linux,phandle = <0x7>;
+ phandle = <0x7>;
+ };
+
+ clk250mhz_3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_ptp_250mhz";
+ linux,phandle = <0x8>;
+ phandle = <0x8>;
+ };
+
+ phy@e1240800 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x143 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0x9>;
+ phandle = <0x9>;
+ };
+
+ phy@e1240c00 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x142 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0xa>;
+ phandle = <0xa>;
+ };
+
+ xgmac@e0700000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
+ interrupts = <0x0 0x145 0x4>,
+ <0x0 0x15a 0x1>,
+ <0x0 0x15b 0x1>,
+ <0x0 0x15c 0x1>,
+ <0x0 0x15d 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 a1 a2 a3 a4 a5];
+ clocks = <0x5 0x6>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0x9>;
+ phy-mode = "xgmii";
+ #stream-id-cells = <0x18>;
+ dma-coherent;
+ linux,phandle = <0xb>;
+ phandle = <0xb>;
+ };
+
+ xgmac@e0900000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
+ interrupts = <0x0 0x144 0x4>,
+ <0x0 0x155 0x1>,
+ <0x0 0x156 0x1>,
+ <0x0 0x157 0x1>,
+ <0x0 0x158 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 b1 b2 b3 b4 b5];
+ clocks = <0x7 0x8>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0xa>;
+ phy-mode = "xgmii";
+ #stream-id-cells = <0x18>;
+ dma-coherent;
+ linux,phandle = <0xc>;
+ phandle = <0xc>;
+ };
+ };
+
+ chosen {
+ stdout-path = "/smb/serial@e1010000";
+ /* Note:
+ * Linux support for pci-probe-only DT is not
+ * stable. Disable this for now and let Linux
+ * take care of the resource assignment.
+ */
+ // linux,pci-probe-only;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ };
+};
+
+
diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc new file mode 100644 index 0000000000..882653eb80 --- /dev/null +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -0,0 +1,713 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE NUM_CORES = 4
+DEFINE DO_PSCI = 1
+DEFINE DO_ISCP = 1
+DEFINE DO_KCS = 1
+DEFINE DO_FLASHER = FALSE
+
+ PLATFORM_NAME = Overdrive1000
+ PLATFORM_GUID = 36774DD7-20DE-4C5B-8722-f8861DFF1F16
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Overdrive1000
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Allow dynamic PCDs
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # ARM PL011 UART Driver
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+ #
+ # PCI support
+ #
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciHostBridgeLib|Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+ #
+ # Styx specific libraries
+ #
+ AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+ AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmPlatformLib|Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+ MemoryInitPeiLib|Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ *_*_*_ASL_FLAGS = -tc -li -l -so
+ *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS)
+ *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS)
+
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+ GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ # All pages are cached by default
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+ ## created by ConsplitterDxe. It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"SoftIron Overdrive 1000"
+
+ # Number of configured cores
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+ # Declare system memory base
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+ # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+ # that)
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal (Atlas UART)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ # serial port is clocked at 100MHz
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+ #
+ # 2 ports active on Overdrive 1000
+ #
+ gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xf
+
+
+ # PCIe Support
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0
+ gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+ gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+ ## Use PCI emulation for ATA PassThru
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE
+
+ ## ACPI (no tables < 4GB)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+!if $(DO_PSCI)
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE
+!endif
+
+!if $(DO_ISCP)
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE
+!endif
+
+ # SMBIOS 3.0 only
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+ # map the stack as non-executable when entering the DXE phase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x2x2 (=2 See Include/FDKGionb.h)
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|0
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicHii]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ #
+ # Console IO support
+ #
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+ <LibraryClasses>
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ DtPlatformDtbLoaderLib|Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
+ }
+
+ #
+ # PCI support
+ #
+ Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Marvell Yukon Ethernet (Overdrive 1000 has 88e8059)
+ #
+!if 0
+ OptionRomPkg/MarvellYukonDxe/MarvellYukonDxe.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+ }
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <LibraryClasses>
+ NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+ }
+ Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+!if $(DO_FLASHER) == TRUE
+ OpenPlatformPkg/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf {
+ <LibraryClasses>
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ }
+!endif
diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf new file mode 100644 index 0000000000..38344fa406 --- /dev/null +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -0,0 +1,416 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.Overdrive1000_ROM]
+BaseAddress = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00500000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = Platform/SoftIron/Overdrive1000Board/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include Silicon/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+
+ FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+ SECTION RAW = Platform/SoftIron/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb
+ }
+
+ #
+ # PCI support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ INF Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+ #
+ # SNP support
+ #
+ INF Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf
+ INF Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+ #
+ # Marvell Ethernet Driver (Overdrive 1000)
+ #
+!if 0
+ INF OptionRomPkg/MarvellYukonDxe/MarvellYukonDxe.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ INF Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf
+ INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ INF Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+[FV.STYX_EFI]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf
+ INF Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.Binary]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE Align = Auto |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
+
diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf b/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf new file mode 100644 index 0000000000..08a7aabe82 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf @@ -0,0 +1,29 @@ +#/** @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiAml
+ FILE_GUID = 2df2a2ee-5f34-4dea-b4b6-da724e455f33
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..cfffc73894 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -0,0 +1,90 @@ +#/** @file
+# Sample ACPI Platform Driver
+#
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#
+# Derived from:
+# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxAcpiLib
+ FILE_GUID = 74850e9e-371c-43af-b1fe-794d61505ad0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdStyxAcpiLib
+
+[Sources]
+ Gtdt.c
+ Fadt.c
+ Dbg2.c
+ Spcr.c
+ Madt.c
+ Mcfg.c
+ Csrt.c
+ Dsdt.c
+ Iort.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## CONSUMED
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdGicVersion
+ gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase
+ gAmdStyxTokenSpaceGuid.PcdCntControlBase
+ gAmdStyxTokenSpaceGuid.PcdCntReadBase
+ gAmdStyxTokenSpaceGuid.PcdCntCTLBase
+ gAmdStyxTokenSpaceGuid.PcdCntBase0
+ gAmdStyxTokenSpaceGuid.PcdCntEL0Base0
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV
+ gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Depex]
+ gAmdMpCoreInfoProtocolGuid
diff --git a/Silicon/AMD/Styx/AcpiTables/Csrt.c b/Silicon/AMD/Styx/AcpiTables/Csrt.c new file mode 100644 index 0000000000..f25f90da53 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Csrt.c @@ -0,0 +1,107 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+//
+// CSRT for ARM_CCN504 (L3 CACHE)
+//
+#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0
+#define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H')
+#define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510
+#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04
+#define AMD_ACPI_ARM_CCN504_DESC_VERSION 1
+#define AMD_ACPI_ARM_CCN504_HNF_COUNT 8
+#define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL
+#define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL
+
+//
+// Ensure proper (byte-packed) structure formats
+//
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT32 Version;
+ UINT8 HnfRegionCount;
+ UINT8 Reserved[3];
+ UINT64 BaseAddress;
+ UINT64 CacheSize;
+} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT16 ResourceType;
+ UINT16 ResourceSubtype;
+ UINT32 UID;
+ AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT32 VendorId;
+ UINT32 SubvendorId;
+ UINT16 DeviceId;
+ UINT16 SubdeviceId;
+ UINT16 Revision;
+ UINT8 Reserved[2];
+ UINT32 SharedInfoLength;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup;
+} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE;
+
+
+AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE,
+ AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE,
+ AMD_ACPI_ARM_CCN504_CSRT_REVISION),
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length
+ AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId
+ 0, // UINT32 RsrcGroup.SubvendorId
+ AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId
+ 0, // UINT16 RsrcGroup.SubdeviceId
+ 0, // UINT16 RsrcGroup.Revision
+ { 0 }, // UINT8 RsrcGroup.Reserved[]
+ 0, // UINT32 RsrcGroup.SharedInfoLength
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length
+ AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType
+ 0, // UINT16 RsrcDesc.ResourceSubtype
+ 0, // UINT32 RsrcDesc.UID
+ { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version
+ AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount
+ { 0 }, // UINT8 Ccn504Desc.Reserved[]
+ AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress
+ AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize
+ },
+ },
+ },
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+CsrtHeader (
+ VOID
+ )
+{
+ return &AcpiCsrt.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Dbg2.c b/Silicon/AMD/Styx/AcpiTables/Dbg2.c new file mode 100644 index 0000000000..5d6cf82dba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dbg2.c @@ -0,0 +1,114 @@ +/** @file
+
+ Microsoft Debug Port Table 2 (DBG2)
+ © 2012 Microsoft. All rights reserved.<BR>
+ http://go.microsoft.com/fwlink/p/?linkid=403551
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_DBG2_REVISION 0
+#define DBG2_NUM_DEBUG_PORTS 1
+#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1
+#define DBG2_NAMESPACESTRING_FIELD_SIZE 8
+#define DBG2_OEM_DATA_FIELD_SIZE 0
+#define DBG2_OEM_DATA_FIELD_OFFSET 0
+
+#define DBG2_DEBUG_PORT_SUBTYPE_PL011 0x0003 // Sub type for Pl011
+#define DBG2_DEBUG_PORT_SUBTYPE_UEFI 0x0007 // Sub type for UEFI Debug Port
+#define PL011_UART_LENGTH 0x1000
+
+#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
+#define NAME_STR_UEFI {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'}
+
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
+} DBG2_TABLE;
+
+
+#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \
+ { \
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision; */ \
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length; */ \
+ NumReg, /* UINT8 NumberofGenericAddressRegisters; */ \
+ DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset; */ \
+ DBG2_OEM_DATA_FIELD_SIZE, /* UINT16 OemDataLength; */ \
+ DBG2_OEM_DATA_FIELD_OFFSET, /* UINT16 OemDataOffset; */ \
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type; */ \
+ SubType, /* UINT16 Port Subtype; */ \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2]; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset; */ \
+ }, \
+ AMD_GASN (UartBase), /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
+ UartAddrLen, /* UINT32 AddressSize */ \
+ UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \
+ }
+
+
+STATIC DBG2_TABLE AcpiDbg2 = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_REVISION),
+ OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo),
+ DBG2_NUM_DEBUG_PORTS // UINT32 NumberDbgDeviceInfo
+ },
+ {
+ /*
+ * Kernel Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 0)
+ DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
+ DBG2_DEBUG_PORT_SUBTYPE_PL011,
+ FixedPcdGet64(PcdSerialDbgRegisterBase),
+ PL011_UART_LENGTH,
+ NAME_STR_UART1),
+#endif
+ /*
+ * UEFI Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 1)
+ DBG2_DEBUG_PORT_DDI(0,
+ DBG2_DEBUG_PORT_SUBTYPE_UEFI,
+ 0,
+ 0,
+ NAME_STR_UEFI),
+#endif
+ }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+Dbg2Header (
+ VOID
+ )
+{
+ return &AcpiDbg2.Description.Header;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl new file mode 100644 index 0000000000..4741bb487c --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl @@ -0,0 +1,817 @@ +/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl
+
+**/
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+#if (NUM_CORES > 1)
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 2)
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 3)
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 4)
+ Device (CPU4)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x200) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 5)
+ Device (CPU5)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x201) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 6)
+ Device (CPU6)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x300) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 7)
+ Device (CPU7)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x301) // _UID: Unique ID
+ }
+#endif
+
+ Device (AHC0)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0300000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0000078, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, }
+ })
+ }
+
+ Device (AHC1)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0D00000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE000007C, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
+ })
+ }
+
+#if DO_XGBE
+ Device (ETH0)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0700000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0780000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240800, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250000, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500F8, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+
+ Device (ETH1)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0900000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0980000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240C00, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250080, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500FC, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+#endif // DO_XGBE
+
+ Device (SPI0)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, }
+ })
+ }
+
+ Device (SPI1)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, }
+ })
+
+ Device(SDC0)
+ {
+ Name(_HID, "AMDI0501") // SD Card/MMC slot
+ Name(_CRS, ResourceTemplate()
+ {
+ SPISerialBus(1, // DeviceSelection
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 20000000, // ConnectionSpeed
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\SB.SPI1", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ ) // SPISerialBus()
+
+ // SD Card “Detect” signal
+ GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6}
+ }) // ResourceTemplate()
+
+ } // Device()
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "AMDI0511") // _HID: Hardware ID
+ Name (_CID, "ARMH0011") // _CID: Compatible ID
+ Name (_ADR, 0xE1010000) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1010000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, }
+ })
+ }
+
+ Device (GIO0)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0080000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
+ })
+ }
+
+ Device (GIO1)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, }
+ })
+ }
+
+ Device (GIO2)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
+ })
+ }
+
+ Device (GIO3)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
+ })
+ }
+
+ Device (I2C0)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ }
+ }
+
+ Device (I2C1)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ }
+ }
+
+ Device (CCP0)
+ {
+ Name (_HID, "AMDI0C00") // _HID: Hardware ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0100000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, }
+ })
+
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"amd,zlib-support", 1}
+ }
+ })
+ }
+
+#if DO_KCS
+ //
+ // IPMI/KCS
+ //
+ Device (KCS0)
+ {
+ Name (_HID, "AMDI0300")
+ Name (_CID, "IPI0001")
+ Name (_STR, Unicode("IPMI_KCS"))
+ Name (_UID, 0)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xE0010000, 0x1) // KCS Data In/Out
+ Memory32Fixed(ReadWrite, 0xE0010004, 0x1) // KCS Control/Status
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 421 } // GSIV
+ })
+ Method (_IFT) { // Interface Type
+ Return ( 0x01) // IPMI KCS
+ }
+
+ Method (_SRV) { // Spec Revision
+ Return (0x200) // IPMI Spec v2.0
+ }
+ }
+#endif // DO_KCS
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ // INTA of the bridge device itself
+ Package () { 0x2FFFF, 0x0, 0x0, 0x140 }
+ })
+
+ Device (EXP1)
+ {
+ Name (_ADR, 0x20001) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x140 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x141 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x142 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x143 }
+ }) // _PRT
+ }
+ Device (EXP2)
+ {
+ Name (_ADR, 0x20002) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x144 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x145 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x146 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x147 }
+ }) // _PRT
+ }
+ Device (EXP3)
+ {
+ Name (_ADR, 0x20003) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x148 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x149 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x14A },
+ Package () { 0xFFFF, 0x3, 0x0, 0x14B }
+ }) // _PRT
+ }
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x007F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x40000000, // Range Minimum
+ 0x5FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x60000000, // Range Minimum
+ 0x7FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Range Minimum
+ 0x9FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xA0000000, // Range Minimum
+ 0xBFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000001FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000100000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000003FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000200000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000400000000, // Range Minimum
+ 0x00000007FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000400000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000800000000, // Range Minimum
+ 0x0000000FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000001000000000, // Range Minimum
+ 0x0000001FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000001000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000002000000000, // Range Minimum
+ 0x0000003FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000002000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004000000000, // Range Minimum
+ 0x0000007FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000004000000000 // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0xEFFF0000, // Translation Address
+ 0x00010000, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF0000000, 0x8000000)
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+
+ //
+ // Device-Specific Methods
+ //
+ Method(_DSM, 0x4, NotSerialized) {
+ If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+ switch (ToInteger(Arg2)) {
+ //
+ // Function 0: Return supported functions
+ //
+ case(0) {
+ Return (Buffer() {0xFF})
+ }
+
+ //
+ // Function 1: Return PCIe Slot Information
+ //
+ case(1) {
+ Return (Package(2) {
+ One, // Success
+ Package(3) {
+ 0x1, // x1 PCIe link
+ 0x1, // PCI express card slot
+ 0x1 // WAKE# signal supported
+ }
+ })
+ }
+
+ //
+ // Function 2: Return PCIe Slot Number.
+ //
+ case(2) {
+ Return (Package(1) {
+ Package(4) {
+ 2, // Source ID
+ 4, // Token ID: ID refers to a slot
+ 0, // Start bit of the field to use.
+ 7 // End bit of the field to use.
+ }
+ })
+ }
+
+ //
+ // Function 3: Return Vendor-specific Token ID Strings.
+ //
+ case(3) {
+ Return (Package(0) {})
+ }
+
+ //
+ // Function 4: Return PCI Bus Capabilities
+ //
+ case(4) {
+ Return (Package(2) {
+ One, // Success
+ Buffer() {
+ 1,0, // Version
+ 0,0, // Status, 0:Success
+ 24,0,0,0, // Length
+ 1,0, // PCI
+ 16,0, // Length
+ 0, // Attributes
+ 0x0D, // Current Speed/Mode
+ 0x3F,0, // Supported Speeds/Modes
+ 0, // Voltage
+ 0,0,0,0,0,0,0 // Reserved
+ }
+ })
+ }
+
+ //
+ // Function 5: Return Ignore PCI Boot Configuration
+ //
+ case(5) {
+ Return (Package(1) {1})
+ }
+
+ //
+ // Function 6: Return LTR Maximum Latency
+ //
+ case(6) {
+ Return (Package(4) {
+ Package(1){0}, // Maximum Snoop Latency Scale
+ Package(1){0}, // Maximum Snoop Latency Value
+ Package(1){0}, // Maximum No-Snoop Latency Scale
+ Package(1){0} // Maximum No-Snoop Latency Value
+ })
+ }
+
+ //
+ // Function 7: Return PCI Express Naming
+ //
+ case(7) {
+ Return (Package(2) {
+ Package(1) {0},
+ Package(1) {Unicode("PCI0")}
+ })
+ }
+
+ //
+ // Not supported
+ //
+ default {
+ }
+ }
+ }
+ Return (Buffer(){0})
+ } // Method(_DSM)
+
+ //
+ // Root-Complex 0
+ //
+ Device (RP0)
+ {
+ Name (_ADR, 0xF0000000) // _ADR: Bus 0, Dev 0, Func 0
+ }
+ }
+ }
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c new file mode 100644 index 0000000000..360a446f76 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.c @@ -0,0 +1,192 @@ +/** @file
+
+ C language wrapper to build DSDT generated data.
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Dsdt.hex>
+#include <Dsdt.offset.h>
+
+
+UINTN
+ShiftLeftByteToUlong (
+ IN UINT8 Byte,
+ IN UINTN Shift
+ )
+{
+ UINTN Data;
+
+ Data = (UINTN)Byte;
+ Data <<= Shift;
+ return Data;
+}
+
+UINTN
+AmlGetPkgLength (
+ IN UINT8 *Buffer,
+ OUT UINTN *PkgLength
+ )
+{
+ UINTN Bytes, Length;
+
+ Bytes = (UINTN)((Buffer[0] >> 6) & 0x3) + 1;
+ switch (Bytes) {
+ case 1:
+ Length = (UINTN)Buffer[0];
+ break;
+
+ case 2:
+ Length = ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ case 3:
+ Length = ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ default: /* 4 bytes */
+ Length = ShiftLeftByteToUlong(Buffer[3], 20) +
+ ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+ }
+
+ *PkgLength = Length;
+ return Bytes;
+}
+
+UINT8 *
+AmlSearchStringPackage (
+ IN UINT8 *Buffer,
+ IN UINTN Length,
+ IN CHAR8 *String
+ )
+{
+ UINTN StrLength;
+
+ StrLength = AsciiStrLen (String) + 1;
+ if (Length > StrLength ) {
+ Length -= StrLength;
+ while (AsciiStrCmp((CHAR8 *)Buffer, String) != 0 && Length) {
+ --Length;
+ ++Buffer;
+ }
+ if (Length) {
+ return &Buffer[StrLength];
+ }
+ }
+ return NULL;
+}
+
+VOID
+OverrideMacAddr (
+ IN UINT8 *DSD_Data,
+ IN UINT64 MacAddr
+ )
+{
+ UINT8 *MacAddrPkg;
+ UINTN Bytes, Length, Index = 0;
+
+ // AML encoding: PackageOp
+ if (DSD_Data[0] == 0x12) {
+ // AML encoding: PkgLength
+ Bytes = AmlGetPkgLength (&DSD_Data[1], &Length);
+
+ // Search for "mac-address" property
+ MacAddrPkg = AmlSearchStringPackage (&DSD_Data[Bytes + 1],
+ Length - Bytes,
+ "mac-address");
+ if (MacAddrPkg &&
+ MacAddrPkg[0] == 0x12 && // PackageOp
+ MacAddrPkg[1] == 0x0E && // PkgLength
+ MacAddrPkg[2] == 0x06) { // NumElements (element must have a BytePrefix)
+
+ MacAddrPkg += 3;
+ do {
+ MacAddrPkg[0] = 0x0A; // BytePrefix
+ MacAddrPkg[1] = (UINT8)(MacAddr & 0xFF);
+ MacAddrPkg += 2;
+ MacAddr >>= 8;
+ } while (++Index < 6);
+ }
+ }
+}
+
+VOID
+OverrideStatus (
+ IN UINT8 *DSD_Data,
+ IN BOOLEAN Enable
+ )
+{
+ if (Enable) {
+ // AML encoding: ReturnOp + BytePrefix
+ if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x0F;
+ }
+ } else {
+ // AML encoding: ReturnOp
+ if (DSD_Data[1] == 0xA4) {
+ // AML encoding: BytePrefix?
+ if (DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x00;
+ } else {
+ DSD_Data[2] = 0x00;
+ }
+ }
+ }
+}
+
+EFI_ACPI_DESCRIPTION_HEADER *
+DsdtHeader (
+ VOID
+ )
+{
+ AML_OFFSET_TABLE_ENTRY *Table;
+ BOOLEAN EnableOnB1;
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Enable features on Styx-B1 or later
+ EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F);
+
+ Table = &DSDT_SEATTLE__OffsetTable[0];
+ while (Table->Pathname) {
+ if (AsciiStrCmp(Table->Pathname, "_SB_.ETH0._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacA));
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB));
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset],
+ EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0);
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+
+ ++Table;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0];
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Fadt.c b/Silicon/AMD/Styx/AcpiTables/Fadt.c new file mode 100644 index 0000000000..bcbff37988 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Fadt.c @@ -0,0 +1,104 @@ +/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#define FADT_FLAGS ( EFI_ACPI_5_1_HW_REDUCED_ACPI | \
+ EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_5_1_HEADLESS )
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ 0, // UINT16 ArmBootArch
+ 1, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+FadtTable (
+ VOID
+ )
+{
+ if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) {
+ AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT;
+ }
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Gtdt.c b/Silicon/AMD/Styx/AcpiTables/Gtdt.c new file mode 100644 index 0000000000..139c9ae0ba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Gtdt.c @@ -0,0 +1,189 @@ +/** @file
+
+ Generic Timer Description Table (GTDT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#pragma pack(push, 1)
+
+#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase)
+#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase)
+#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase)
+#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0)
+#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0)
+#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase)
+#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase)
+#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV)
+#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV)
+
+
+/*
+ * Section 8.2.3 of Cortex-A15 r2p1 TRM
+ */
+#define CP15_TIMER_SEC_INTR 29
+#define CP15_TIMER_NS_INTR 30
+#define CP15_TIMER_VIRT_INTR 27
+#define CP15_TIMER_NSHYP_INTR 26
+
+/* SBSA Timers */
+ #define PLATFORM_TIMER_COUNT 2
+ #define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+
+/*
+// GTDT Table timer flags.
+
+Bit 0: Timer interrupt Mode
+ This bit indicates the mode of the timer interrupt
+ 1: Interrupt is Edge triggered
+ 0: Interrupt is Level triggered
+Timer Interrupt polarity
+ This bit indicates the polarity of the timer interrupt
+ 1: Interrupt is Active low
+ 0: Interrupt is Active high
+Reserved 2 30 Reserved, must be zero.
+
+From A15 TRM:
+ 9.2 Generic Timer functional description
+ ...
+ Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is
+ sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for
+ the ID and PPI allocation of the Timer interrupts.
+ PPI6 Virtual Maintenance Interrupt.
+ PPI5 Hypervisor timer event.
+ PPI4 Virtual timer event.
+ PPI3 nIRQ.
+ PPI2 Non-secure physical timer event.
+ PPI1 Secure physical timer event.
+ PPI0-5 Active-LOW level-sensitive.
+ PPI6 Active-HIGH level-sensitive.*/
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_NON_SECURE 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED 0
+#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH 0
+#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE 0
+#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT 0
+#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
+
+#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
+#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH 0
+#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE 0
+#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+
+#define AMD_SBSA_GTX { \
+ EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \
+ 1, /* UINT32 GTBlockTimerCount */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \
+ }
+
+#define AMD_SBSA_GTX_TIMER { \
+ 0, /* UINT8 GTFrameNumber */ \
+ {0, 0, 0}, /* UINT8 Reserved[3] */ \
+ CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \
+ CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \
+ SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
+ 0, /* UINT32 GTxVirtualTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
+ GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
+ }
+
+#define AMD_SBSA_WATCHDOG { \
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \
+ SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \
+ SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \
+ SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \
+ }
+
+typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer;
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog;
+} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE;
+
+STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = {
+ {
+ AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ AMD_ACPI_5_1_ARM_GTDT_STRUCTURE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress
+ PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
+ PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset
+ },
+ AMD_SBSA_GTX,
+ AMD_SBSA_GTX_TIMER,
+ AMD_SBSA_WATCHDOG,
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+GtdtHeader (
+ VOID
+ )
+{
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Check BaseModel and Stepping: Styx-B0 or prior?
+ if (((CpuId & 0xFF0) == 0) || ((CpuId & 0x00F) == 0)) {
+ AcpiGtdt.Gtdt.Header.Length = sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE);
+ AcpiGtdt.Gtdt.PlatformTimerCount = 0;
+ AcpiGtdt.Gtdt.PlatformTimerOffset = 0;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiGtdt.Gtdt.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 0000000000..80872773ba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,375 @@ +/** @file
+
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/IoRemappingTable.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#define STYX_PCIE_SMMU_BASE 0xE0A00000
+#define STYX_PCIE_SMMU_SIZE 0x10000
+#define STYX_PCIE_SMMU_INTERRUPT 0x16d
+
+#define STYX_ETH0_SMMU_BASE 0xE0600000
+#define STYX_ETH0_SMMU_SIZE 0x10000
+#define STYX_ETH0_SMMU_INTERRUPT 0x170
+
+#define STYX_ETH1_SMMU_BASE 0xE0800000
+#define STYX_ETH1_SMMU_SIZE 0x10000
+#define STYX_ETH1_SMMU_INTERRUPT 0x16f
+
+#define STYX_SATA0_SMMU_BASE 0xE0200000
+#define STYX_SATA0_SMMU_SIZE 0x10000
+#define STYX_SATA0_SMMU_INTERRUPT 0x16c
+
+#define STYX_SATA1_SMMU_BASE 0xE0C00000
+#define STYX_SATA1_SMMU_SIZE 0x10000
+#define STYX_SATA1_SMMU_INTERRUPT 0x16b
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1];
+} STYX_SMMU_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
+} STYX_RC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node;
+ CONST CHAR8 Name[11];
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32];
+} STYX_NC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
+ STYX_SMMU_NODE PciSmmuNode;
+ STYX_RC_NODE PciRcNode;
+
+#if DO_XGBE
+ STYX_SMMU_NODE Eth0SmmuNode;
+ STYX_NC_NODE Eth0NamedNode;
+ STYX_SMMU_NODE Eth1SmmuNode;
+ STYX_NC_NODE Eth1NamedNode;
+#endif
+
+ STYX_SMMU_NODE Sata0SmmuNode;
+ STYX_NC_NODE Sata0NamedNode;
+ STYX_SMMU_NODE Sata1SmmuNode;
+ STYX_NC_NODE Sata1NamedNode;
+} STYX_IO_REMAPPING_STRUCTURE;
+
+#define __STYX_SMMU_NODE(Base, Size, Irq) \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_SMMUv1v2, \
+ sizeof(STYX_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ 0x0, \
+ 0x0, \
+ }, \
+ Base, \
+ Size, \
+ EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \
+ EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \
+ FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
+ SMMU_NSgIrpt), \
+ 0x1, \
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ 0x0, \
+ 0x0, \
+ }, { \
+ { \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ }, \
+ }
+
+#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \
+ { \
+ In, \
+ Num, \
+ Out, \
+ FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
+ Flags \
+ }
+
+#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \
+ { \
+ 0x0, \
+ 0x0, \
+ Out, \
+ FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \
+ }
+
+#define __STYX_NAMED_COMPONENT_NODE(Name) \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_NAMED_COMP, \
+ sizeof(STYX_NC_NODE), \
+ 0x0, \
+ 0x0, \
+ 0x20, \
+ FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \
+ }, \
+ 0x0, \
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \
+ 0x0, \
+ 0x0, \
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \
+ 40, \
+ }, \
+ Name
+
+STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = {
+ {
+ AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+ STYX_IO_REMAPPING_STRUCTURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+#if DO_XGBE
+ 10, // NumNodes
+#else
+ 6, // NumNodes
+#endif
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0 // Reserved
+ }, {
+ // PciSmmuNode
+ __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE,
+ STYX_PCIE_SMMU_SIZE,
+ STYX_PCIE_SMMU_INTERRUPT)
+ }, {
+ // PciRcNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof(STYX_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x0, // PciSegmentNumber
+ }, {
+ __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0),
+ }
+#if DO_XGBE
+ }, {
+ // Eth0SmmuNode
+ __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE,
+ STYX_ETH0_SMMU_SIZE,
+ STYX_ETH0_SMMU_INTERRUPT)
+ }, {
+ // Eth0NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode),
+ }
+ }, {
+ // Eth1SmmuNode
+ __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE,
+ STYX_ETH1_SMMU_SIZE,
+ STYX_ETH1_SMMU_INTERRUPT)
+ }, {
+ // Eth1NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode),
+ }
+#endif
+ }, {
+ // Sata0SmmuNode
+ __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE,
+ STYX_SATA0_SMMU_SIZE,
+ STYX_SATA0_SMMU_INTERRUPT)
+ }, {
+ // Sata0NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode),
+ }
+ }, {
+ // Sata1SmmuNode
+ __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE,
+ STYX_SATA1_SMMU_SIZE,
+ STYX_SATA1_SMMU_INTERRUPT)
+ }, {
+ // Sata1NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode),
+ }
+ }
+};
+
+#pragma pack()
+
+#define STYX_SOC_VERSION_MASK 0xFFF
+#define STYX_SOC_VERSION_A0 0x000
+#define STYX_SOC_VERSION_B0 0x010
+#define STYX_SOC_VERSION_B1 0x011
+
+EFI_ACPI_DESCRIPTION_HEADER *
+IortHeader (
+ VOID
+ )
+{
+ if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
+ //
+ // Silicon revisions prior to B1 have only one SATA port,
+ // so omit the nodes of the second port in this case.
+ //
+ AcpiIort.Iort.NumNodes -= 2;
+ }
+ return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Madt.c b/Silicon/AMD/Styx/AcpiTables/Madt.c new file mode 100644 index 0000000000..96182e790f --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Madt.c @@ -0,0 +1,336 @@ +/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
+
+**/
+
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL;
+
+
+// ARM PL390 General Interrupt Controller
+#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase))
+#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase))
+#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase))
+#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase))
+#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt))
+#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase))
+#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase))
+#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion))
+
+#define GICD_ID ( 0 )
+#define GICD_VECTOR ( 0 )
+
+#define GICM_ID ( 0 )
+#define GICM_SPI_COUNT ( 0x100 )
+#define GICM_SPI_BASE ( 0x40 )
+#define GSIV_SPI_OFFSET ( 32 )
+
+#if STYX_A0
+ #define MSI_TYPER_FLAG ( 1 ) // Ignore TYPER register and use Count/Base fields
+#else
+ #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields
+#endif
+
+#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion))
+#define PARKED_OFFSET ( 4096 )
+
+#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster))
+#define PARKED_ADDRESS(Base, ClusterId, CoreId) \
+ ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET)
+
+
+/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
+#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \
+ EFI_ACPI_5_1_GIC, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \
+ CpuNum, /* UINT32 CPUInterfaceNumber */ \
+ (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \
+ EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \
+ PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \
+ PerfInt, /* UINT32 PerformanceInterruptGsiv */ \
+ 0, /* UINT64 ParkedAddress */ \
+ GIC_BASE, /* UINT64 PhysicalBaseAddress */ \
+ GICV_BASE, /* UINT64 GICV */ \
+ GICH_BASE, /* UINT64 GICH */ \
+ VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \
+ GICVR_BASE, /* UINT64 GICRBaseAddress */ \
+ (ClusterId << 8) | CoreId /* UINT64 MPIDR */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */
+#define AMD_GICD(Id, Vec) { \
+ EFI_ACPI_5_1_GICD, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicId */ \
+ GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
+ Vec, /* UINT32 SystemVectorBase */ \
+ EFI_ACPI_RESERVED_DWORD /* UINT32 Reserved2 */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */
+#define AMD_GICM(Id, SpiCount, SpiBase) { \
+ EFI_ACPI_5_1_GIC_MSI_FRAME, /* UINT8 Type */ \
+ sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicMsiFrameId */ \
+ GIC_MSI_FRAME, /* UINT64 PhysicalBaseAddress */ \
+ MSI_TYPER_FLAG, /* UINT32 Flags */ \
+ SpiCount, /* UINT16 SPICount */ \
+ SpiBase /* UINT16 SPIBase */ \
+ }
+
+
+//
+// NOTE: NUM_CORES is a pre-processor macro passed in with -D option
+//
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_1_GIC_STRUCTURE GicC[NUM_CORES];
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM;
+} EFI_ACPI_5_1_ARM_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_ARM_MADT_STRUCTURE,
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ GIC_BASE, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ /*
+ * GIC Interface for Cluster 0 CPU 0
+ */
+ AMD_GIC(0, 0, 0, 39), // EFI_ACPI_5_1_GIC_STRUCTURE
+#if (NUM_CORES > 1)
+ /*
+ * GIC Interface for Cluster 0 CPU 1
+ */
+ AMD_GIC(1, 0, 1, 40), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 2)
+ /*
+ * GIC Interface for Cluster 1 CPU 0
+ */
+ AMD_GIC(2, 1, 0, 41), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 3)
+ /*
+ * GIC Interface for Cluster 1 CPU 1
+ */
+ AMD_GIC(3, 1, 1, 42), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 4)
+ /*
+ * GIC Interface for Cluster 2 CPU 0
+ */
+ AMD_GIC(4, 2, 0, 43), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 5)
+ /*
+ * GIC Interface for Cluster 2 CPU 1
+ */
+ AMD_GIC(5, 2, 1, 44), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 6)
+ /*
+ * GIC Interface for Cluster 3 CPU 0
+ */
+ AMD_GIC(6, 3, 0, 45), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 7)
+ /*
+ * GIC Interface for Cluster 3 CPU 1
+ */
+ AMD_GIC(7, 3, 1, 46), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+ },
+ /*
+ * GIC Distributor
+ */
+ AMD_GICD(GICD_ID, GICD_VECTOR), // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE
+ /*
+ * GIC MSI Frame
+ */
+ AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE),
+};
+
+
+STATIC
+EFI_STATUS
+BuildGicC (
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC,
+ UINT32 CpuNum,
+ UINT32 ClusterId,
+ UINT32 CoreId,
+ EFI_PHYSICAL_ADDRESS MpParkingBase
+ )
+{
+ UINT32 MpId, PmuSpi;
+ EFI_STATUS Status;
+
+ MpId = (UINT32) GET_MPID (ClusterId, CoreId);
+ Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi);
+ if (EFI_ERROR (Status))
+ return Status;
+
+ GicC->Type = EFI_ACPI_5_1_GIC;
+ GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ GicC->Reserved = EFI_ACPI_RESERVED_WORD;
+ GicC->CPUInterfaceNumber = CpuNum;
+ GicC->AcpiProcessorUid = MpId;
+ GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED;
+ GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION;
+ GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId);
+ GicC->PhysicalBaseAddress = GIC_BASE;
+ GicC->GICV = GICV_BASE;
+ GicC->GICH = GICH_BASE;
+ GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT;
+ GicC->GICRBaseAddress = GICVR_BASE;
+ GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET;
+ GicC->MPIDR = MpId;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+BuildGicD (
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD,
+ UINT32 GicId,
+ UINT32 SystemVectorBase
+ )
+{
+ GicD->Type = EFI_ACPI_5_1_GICD;
+ GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+ GicD->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicD->GicId = GicId;
+ GicD->PhysicalBaseAddress = GICD_BASE;
+ GicD->SystemVectorBase = SystemVectorBase;
+#if 0
+ GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD;
+#else
+ GicD->GicVersion = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE;
+#endif
+}
+
+
+STATIC
+VOID
+BuildGicM (
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM,
+ UINT32 MsiFrameId,
+ UINT16 SpiCount,
+ UINT16 SpiBase
+ )
+{
+ GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME;
+ GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+ GicM->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicM->GicMsiFrameId = MsiFrameId;
+ GicM->PhysicalBaseAddress = GIC_MSI_FRAME;
+ GicM->Flags = MSI_TYPER_FLAG;
+ GicM->SPICount = SpiCount;
+ GicM->SPIBase = SpiBase;
+}
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+MadtHeader (
+ VOID
+ )
+{
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC;
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN CoreCount, CpuNum;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+
+ Status = gBS->LocateProtocol (
+ &gAmdMpCoreInfoProtocolGuid,
+ NULL,
+ (VOID **)&mAmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Get pointer to ARM core info table
+ ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+
+ // Make sure SoC's core count does not exceed what we want to build
+ ASSERT (CoreCount <= NUM_CORES);
+ ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount));
+
+ MpParkingSize = 0;
+ MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize);
+ if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) {
+ DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n"));
+ MpParkingBase = 0;
+ }
+
+ GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0];
+ AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+ for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) {
+ DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d CoreId = %d\n",
+ CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId));
+
+ Status = BuildGicC (GicC, CpuNum,
+ ArmCoreInfoTable[CpuNum].ClusterId,
+ ArmCoreInfoTable[CpuNum].CoreId,
+ MpParkingBase
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ }
+
+ GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicD (GicD, GICD_ID, GICD_VECTOR);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+
+ GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+
+ return &AcpiMadt.Header.Header;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Mcfg.c b/Silicon/AMD/Styx/AcpiTables/Mcfg.c new file mode 100644 index 0000000000..4fc18e8efc --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Mcfg.c @@ -0,0 +1,51 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#if STYX_A0
+#define END_PCI_BUS_NUMBER 15
+#else
+#define END_PCI_BUS_NUMBER 255
+#endif
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = {
+ { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD },
+ { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+McfgHeader (
+ VOID
+ )
+{
+ return &AcpiMcfg.Header.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Spcr.c b/Silicon/AMD/Styx/AcpiTables/Spcr.c new file mode 100644 index 0000000000..719c276cfb --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Spcr.c @@ -0,0 +1,124 @@ +/** @file
+
+ Serial Port Console Redirection Table
+ © 2000 - 2014 Microsoft Corporation. All rights reserved.
+ http://go.microsoft.com/fwlink/?linkid=403368
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011 3
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = {
+ //
+ // Header
+ //
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ //
+ // InterfaceType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011,
+ //
+ // Reserved[3]
+ //
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ //
+ // BaseAddress
+ //
+ AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)),
+ //
+ // InterruptType
+ //
+ 0,
+ //
+ // Irq
+ //
+ 0,
+ //
+ // GlobalSystemInterrupt
+ //
+ 0x148,
+ //
+ // BaudRate
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ //
+ // Parity
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ //
+ // StopBits
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ //
+ // FlowControl
+ //
+ 0,
+ //
+ // TerminalType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ //
+ // Language
+ //
+ EFI_ACPI_RESERVED_BYTE,
+ //
+ // PciDeviceId
+ //
+ 0xFFFF,
+ //
+ // PciVendorId
+ //
+ 0xFFFF,
+ //
+ // PciBusNumber
+ //
+ 0x00,
+ //
+ // PciDeviceNumber
+ //
+ 0x00,
+ //
+ // PciFunctionNumber
+ //
+ 0x00,
+ //
+ // PciFlags
+ //
+ 0,
+ //
+ // PciSegment
+ //
+ 0,
+ //
+ // Reserved2
+ //
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+SpcrHeader (
+ VOID
+ )
+{
+ return &AcpiSpcr.Header;
+}
+
diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec new file mode 100644 index 0000000000..ddd5bf4c36 --- /dev/null +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -0,0 +1,117 @@ +#/** @file
+# AmdStyx package.
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may be
+# found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AmdStyx
+ PACKAGE_GUID = 58353cd1-61fb-4f9e-93f7-c43961d39b01
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Common
+
+[LibraryClasses]
+
+[Ppis]
+ gAmdStyxPlatInitPpiGuid = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } }
+
+[Protocols]
+ gAmdMpBootProtocolGuid = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } }
+ gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } }
+
+[Guids]
+ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } }
+ gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
+
+ # 2a5e4deb-4445-4fb6-8b14-366b8e779b69
+ # EFI variable scope for Styx
+ gAmdStyxVariableGuid = { 0x2a5e4deb, 0x4445, 0x4fb6, { 0x8b, 0x14, 0x36, 0x6b, 0x8e, 0x77, 0x9b, 0x69 } }
+
+[PcdsDynamic]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101
+
+ gAmdStyxTokenSpaceGuid.PcdEthMacA|0|UINT64|0x000d0001
+ gAmdStyxTokenSpaceGuid.PcdEthMacB|0|UINT64|0x000d0002
+
+[PcdsFixedAtBuild]
+ # CPUID Register
+ gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200
+
+ # Synopsys SATA Controller
+ gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort|0xE0300000|UINT32|0x00020000
+ gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8|UINT8|0x00020001
+ gAmdStyxTokenSpaceGuid.PcdSataPi|0xFF|UINT32|0x00020002
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode|0|UINT16|0x00020003
+ gAmdStyxTokenSpaceGuid.PcdSataPortMpsp|TRUE|BOOLEAN|0x00020004
+ gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport|FALSE|BOOLEAN|0x00020005
+ gAmdStyxTokenSpaceGuid.PcdSataSssSupport|TRUE|BOOLEAN|0x00020006
+ gAmdStyxTokenSpaceGuid.PcdSataPortCpd|TRUE|BOOLEAN|0x00020007
+ gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort|0xE0D00000|UINT32|0x00020008
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount|8|UINT8|0x00020009
+
+ # UART
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0xE1010000|UINT64|0x00030000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200|UINT32|0x00030001
+
+ # GIC
+ gAmdStyxTokenSpaceGuid.PcdGicVersion|0x2|UINT8|0x00040000
+ gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase|0xE1140000|UINT64|0x00040001
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase|0xE116F000|UINT64|0x00040002
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt|25|UINT32|0x00040003
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase|0x00000000|UINT64|0x00040004
+ gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase|0xE1180000|UINT64|0x00040005
+
+ # Timers (GTDT)
+ gAmdStyxTokenSpaceGuid.PcdCntControlBase|0xFFFFFFFFFFFFFFFF|UINT64|0x00050000
+ gAmdStyxTokenSpaceGuid.PcdCntReadBase|0x00000000E0B90000|UINT64|0x00050001
+ gAmdStyxTokenSpaceGuid.PcdCntCTLBase|0x00000000E0BD0000|UINT64|0x00050002
+ gAmdStyxTokenSpaceGuid.PcdCntBase0|0x00000000E0BE0000|UINT64|0x00050003
+ gAmdStyxTokenSpaceGuid.PcdCntEL0Base0|0x00000000E0BF0000|UINT64|0x00050004
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase|0x00000000E0BB0000|UINT64|0x00050005
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase|0x00000000E0BC0000|UINT64|0x00050006
+ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV|371|UINT32|0x00050007
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV|369|UINT32|0x00050008
+
+ # Trusted-Firmware
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport|TRUE|BOOLEAN|0x00060000
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002
+
+ # ISCP
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000
+
+ # PSCI
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE|BOOLEAN|0x00080000
+ gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext|0|UINT64|0x00080001
+
+ # Cores Per cluster
+ gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000
+
+ # UEFI entry point
+ gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000
+
+ # Parking Protocol
+ gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000
+
+ # The original offset in memory of the NV store firmware volume, before
+ # relocating it to a dynamically allocated buffer. We need this to correlate
+ # flash accesses to the in-memory copy with LBAs in the actual SPI flash
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000
+ # block size to use when invoking the ISCP FV methods
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001
+
+[PcdsFixedAtBuild,PcdsDynamic]
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus|FALSE|BOOLEAN|0xe0000000
diff --git a/Silicon/AMD/Styx/Applications/StyxFlashUefi/Scripts/GccBase.lds b/Silicon/AMD/Styx/Applications/StyxFlashUefi/Scripts/GccBase.lds new file mode 100644 index 0000000000..7a0c87c6e3 --- /dev/null +++ b/Silicon/AMD/Styx/Applications/StyxFlashUefi/Scripts/GccBase.lds @@ -0,0 +1,86 @@ +/** @file
+
+ Unified linker script for GCC based builds
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2017, Linaro Ltd. All rights reserved.<BR>
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+SECTIONS {
+
+ /*
+ * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
+ * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
+ * between 32-bit and 64-bit builds). The actual start of the .text section
+ * will be rounded up based on its actual alignment.
+ */
+ . = PECOFF_HEADER_SIZE;
+
+ .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.text .text.* .stub .gnu.linkonce.t.*)
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.got .got.*)
+
+ /*
+ * The contents of AutoGen.c files are mostly constant from the POV of the
+ * program, but most of it ends up in .data or .bss by default since few of
+ * the variable definitions that get emitted are declared as CONST.
+ * Unfortunately, we cannot pull it into the .text section entirely, since
+ * patchable PCDs are also emitted here, but we can at least move all of the
+ * emitted GUIDs here.
+ */
+ *:AutoGen.obj(.data.g*Guid)
+ }
+
+ /*
+ * The alignment of the .data section should be less than or equal to the
+ * alignment of the .text section. This ensures that the relative offset
+ * between these sections is the same in the ELF and the PE/COFF versions of
+ * this binary.
+ */
+ .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.bss .bss.*)
+ *(.payload)
+ }
+
+ .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ KEEP (*(.eh_frame))
+ }
+
+ .rela (INFO) : {
+ *(.rela .rela.*)
+ }
+
+ .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ KEEP (*(.hii))
+ }
+
+ /*
+ * Retain the GNU build id but in a non-allocatable section so GenFw
+ * does not copy it into the PE/COFF image.
+ */
+ .build-id (INFO) : { *(.note.gnu.build-id) }
+
+ /DISCARD/ : {
+ *(.note.GNU-stack)
+ *(.gnu_debuglink)
+ *(.interp)
+ *(.dynsym)
+ *(.dynstr)
+ *(.dynamic)
+ *(.hash .gnu.hash)
+ *(.comment)
+ *(COMMON)
+ }
+}
diff --git a/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashImage.S b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashImage.S new file mode 100644 index 0000000000..041339ee9b --- /dev/null +++ b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashImage.S @@ -0,0 +1,25 @@ +/** @file
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ .section ".payload"
+ .align 12
+
+ASM_GLOBAL ASM_PFX(StyxFlashImageStart)
+ASM_PFX(StyxFlashImageStart):
+ .incbin "STYX_EFI.Fv"
+
+ .align 2
+ASM_GLOBAL ASM_PFX(StyxFlashImageSize)
+ASM_PFX(StyxFlashImageSize):
+ .long . - ASM_PFX(StyxFlashImageStart)
diff --git a/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.c b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.c new file mode 100644 index 0000000000..8f181bc2a5 --- /dev/null +++ b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.c @@ -0,0 +1,96 @@ +/** @file
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ShellCEntryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+
+#define UEFI_IMAGE_OFFSET FixedPcdGet64 (PcdFvBaseAddress) - FixedPcdGet64 (PcdFdBaseAddress)
+#define BLOCK_SIZE SIZE_64KB
+
+STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+STATIC UINT8 Buffer[BLOCK_SIZE];
+
+extern CONST UINT8 StyxFlashImageStart[];
+extern CONST UINT32 StyxFlashImageSize;
+
+/***
+ Main entrypoint
+
+ Establishes the main structure of the application.
+
+ @retval 0 The application exited normally.
+ @retval Other An error occurred.
+***/
+INTN
+EFIAPI
+ShellAppMain (
+ IN UINTN Argc,
+ IN CHAR16 **Argv
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ INTN Remaining;
+
+ Print (L"StyxFlashUefi: firmware updater for AMD Seattle based boards.\n");
+
+ Status = gBS->LocateProtocol (&gAmdIscpDxeProtocolGuid, NULL,
+ (VOID **)&mIscpDxeProtocol);
+ if (EFI_ERROR (Status)) {
+ Print (L"Failed to locate ISCP communication protocol, terminating...\n");
+ return (INTN)Status;
+ }
+
+ Index = 0;
+ Remaining = StyxFlashImageSize;
+ do {
+ Status = mIscpDxeProtocol->AmdExecuteEraseFvBlockDxe (
+ mIscpDxeProtocol,
+ UEFI_IMAGE_OFFSET + Index * BLOCK_SIZE,
+ BLOCK_SIZE);
+ if (EFI_ERROR (Status)) {
+ Print (L"Erase failed!\n");
+ return (INTN)Status;
+ }
+
+ CopyMem (Buffer, StyxFlashImageStart + Index * BLOCK_SIZE,
+ MIN (Remaining, BLOCK_SIZE));
+
+ Status = mIscpDxeProtocol->AmdExecuteUpdateFvBlockDxe (
+ mIscpDxeProtocol,
+ UEFI_IMAGE_OFFSET + Index * BLOCK_SIZE,
+ Buffer,
+ MIN (Remaining, BLOCK_SIZE));
+
+ if (EFI_ERROR (Status)) {
+ Print (L"Update failed!\n");
+ return (INTN)Status;
+ }
+
+ Remaining -= BLOCK_SIZE;
+ Index++;
+
+ Print (L"Block %d of %d updated\n", Index, StyxFlashImageSize / BLOCK_SIZE);
+
+ } while (Remaining > 0);
+
+ Print (L"\nDone!\n");
+
+ return 0;
+}
diff --git a/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf new file mode 100644 index 0000000000..582b57b2c8 --- /dev/null +++ b/Silicon/AMD/Styx/Applications/StyxFlashUefi/StyxFlashUefi.inf @@ -0,0 +1,53 @@ +#/** @file
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = StyxFlashUefi
+ FILE_GUID = 07b65d9d-b1a2-416e-bd04-0b61b775f924
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 0.1
+ ENTRY_POINT = ShellCEntryLib
+
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ StyxFlashImage.S
+ StyxFlashUefi.c
+
+[Packages]
+ AmdModulePkg/AmdModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ ShellPkg/ShellPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ ShellCEntryLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+[BuildOptions]
+ *_*_*_CC_FLAGS = -mcmodel=small
+ *_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -Wl,-T,$(MODULE_DIR)/Scripts/GccBase.lds
+ *_*_*_PLATFORM_FLAGS = -I$(BIN_DIR)/../FV
diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h new file mode 100644 index 0000000000..9438b8b0c2 --- /dev/null +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -0,0 +1,62 @@ +/** @file
+ This library provides support for various platform-specific DXE drivers.
+
+ Copyright (c) 2014 - 2015, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMDSTYX_ACPI_LIB_H_
+#define _AMDSTYX_ACPI_LIB_H_
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_DESCRIPTION_HEADER *FadtTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *FacsTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *GtdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *DsdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void);
+EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void);
+
+#define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'}
+#define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ')
+#define EFI_ACPI_AMD_OEM_REVISION 0
+#define EFI_ACPI_AMD_CREATOR_ID SIGNATURE_32('A','M','D',' ')
+#define EFI_ACPI_AMD_CREATOR_REVISION 0
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define AMD_ACPI_HEADER(sign, type, rev) { \
+ sign, /* UINT32 Signature */ \
+ sizeof (type), /* UINT32 Length */ \
+ rev, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ EFI_ACPI_AMD_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \
+ EFI_ACPI_AMD_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_AMD_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_AMD_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_AMD_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define NULL_GAS {EFI_ACPI_5_1_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_1_UNDEFINED, 0L}
+#define AMD_GAS8(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 8, 0, EFI_ACPI_5_1_BYTE, address}
+#define AMD_GAS16(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_1_WORD, address}
+#define AMD_GAS32(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_1_DWORD, address}
+#define AMD_GAS64(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 64, 0, EFI_ACPI_5_1_QWORD, address}
+#define AMD_GASN(address) AMD_GAS32(address)
+
+#endif // _AMDSTYX_ACPI_LIB_H_
+
diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h new file mode 100644 index 0000000000..2aa4c55ccb --- /dev/null +++ b/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h @@ -0,0 +1,39 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_BOOT_H_
+#define _AMD_MP_BOOT_H_
+
+extern EFI_GUID gAmdMpBootProtocolGuid;
+
+typedef
+VOID
+(EFIAPI *PARK_SECONDARY_CORE) (
+ IN ARM_CORE_INFO *ArmCoreInfo,
+ IN EFI_PHYSICAL_ADDRESS SecondaryEntry
+ );
+
+typedef struct _AMD_MP_BOOT_INFO {
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+} AMD_MP_BOOT_INFO;
+
+typedef struct _AMD_MP_BOOT_PROTOCOL {
+ PARK_SECONDARY_CORE ParkSecondaryCore;
+ AMD_MP_BOOT_INFO *MpBootInfo;
+} AMD_MP_BOOT_PROTOCOL;
+
+#endif // _AMD_MP_BOOT_H_
diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h new file mode 100644 index 0000000000..95f46e8af9 --- /dev/null +++ b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h @@ -0,0 +1,45 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_CORE_INFO_H_
+#define _AMD_MP_CORE_INFO_H_
+
+extern EFI_GUID gAmdMpCoreInfoProtocolGuid;
+
+typedef
+ARM_CORE_INFO *
+(EFIAPI *GET_ARM_CORE_INFO_TABLE) (
+ OUT UINTN *NumEntries
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_PMU_SPI_FROM_MPID) (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ );
+
+typedef
+EFI_PHYSICAL_ADDRESS
+(EFIAPI *GET_MP_PARKING_BASE) (
+ OUT UINTN *MpParkingSize
+ );
+
+typedef struct _AMD_MP_CORE_INFO_PROTOCOL {
+ GET_ARM_CORE_INFO_TABLE GetArmCoreInfoTable;
+ GET_PMU_SPI_FROM_MPID GetPmuSpiFromMpId;
+ GET_MP_PARKING_BASE GetMpParkingBase;
+} AMD_MP_CORE_INFO_PROTOCOL;
+
+#endif // _AMD_MP_CORE_INFO_H_
diff --git a/Silicon/AMD/Styx/Common/Varstore.fdf.inc b/Silicon/AMD/Styx/Common/Varstore.fdf.inc new file mode 100644 index 0000000000..83aa4334fb --- /dev/null +++ b/Silicon/AMD/Styx/Common/Varstore.fdf.inc @@ -0,0 +1,70 @@ +## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (C) 2016, Linaro, Ltd.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+0x00460000|0x0000F000
+gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x30000
+ 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0xF Blocks * 0x1000 Bytes / Block
+ 0x0F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0xF000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xefb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xEF, 0x00, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x0046F000|0x00001000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00470000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 0000000000..15b38bbf89 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,114 @@ +/** @file
+
+ Sample ACPI Platform Driver
+
+ Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AcpiTable.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_ACPI_TABLES 12
+
+EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES];
+
+
+/**
+ Entrypoint of Acpi Platform driver.
+
+ @param ImageHandle
+ @param SystemTable
+
+ @return EFI_SUCCESS
+ @return EFI_LOAD_ERROR
+ @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ UINTN TableHandle;
+ UINTN TableIndex;
+
+ ZeroMem(AcpiTableList, sizeof(AcpiTableList));
+
+ TableIndex = 0;
+ AcpiTableList[TableIndex++] = FadtTable();
+ AcpiTableList[TableIndex++] = DsdtHeader();
+ AcpiTableList[TableIndex++] = MadtHeader();
+ AcpiTableList[TableIndex++] = GtdtHeader();
+ AcpiTableList[TableIndex++] = Dbg2Header();
+ AcpiTableList[TableIndex++] = SpcrHeader();
+ AcpiTableList[TableIndex++] = McfgHeader();
+ AcpiTableList[TableIndex++] = CsrtHeader();
+ if (PcdGetBool (PcdEnableSmmus)) {
+ AcpiTableList[TableIndex++] = IortHeader();
+ }
+ AcpiTableList[TableIndex++] = NULL;
+
+ DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__));
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ TableIndex = 0;
+ while (AcpiTableList[TableIndex] != NULL) {
+ //
+ // Install ACPI table
+ //
+ DEBUG ((EFI_D_ERROR, "Installing %c%c%c%c Table (Revision %d, Length %d) ...\n",
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 1),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 2),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 3),
+ AcpiTableList[TableIndex]->Revision,
+ AcpiTableList[TableIndex]->Length));
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ AcpiTableList[TableIndex],
+ (AcpiTableList[TableIndex])->Length,
+ &TableHandle
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+ TableIndex++;
+ ASSERT( TableIndex < MAX_ACPI_TABLES );
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000000..3c484c43ac --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,53 @@ +#/** @file
+# Sample ACPI Platform Driver
+#
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiPlatform
+ FILE_GUID = f229c831-6a35-440b-9c84-dd3bc71e3865
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+[Sources]
+ AcpiPlatform.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ AmdStyxAcpiLib
+ DebugLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c new file mode 100644 index 0000000000..bd7244648a --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c @@ -0,0 +1,170 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+/* These externs are used to relocate our Pen code into pre-allocated memory */
+extern VOID *SecondariesPenStart;
+extern VOID *SecondariesPenEnd;
+extern UINTN *AsmParkingBase;
+extern UINTN *AsmMailboxBase;
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+ConfigurePen (
+ IN EFI_PHYSICAL_ADDRESS MpParkingBase,
+ IN UINTN MpParkingSize,
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN ArmCoreCount
+ )
+{
+ EFI_PHYSICAL_ADDRESS PenBase;
+ UINTN PenSize;
+ UINTN MailboxBase;
+ UINTN CoreNum;
+ UINTN CoreMailbox;
+ UINTN CoreParking;
+
+ //
+ // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#.
+ // For details, refer to the "Multi-processor Startup for ARM Platforms" document:
+ // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx
+ //
+ PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64));
+ PenSize = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart;
+
+ // Relocate the Pen code
+ CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize);
+
+ // Put spin-table mailboxes below the pen code so we know where they are relative to code.
+ // Make sure this is 8 byte aligned.
+ MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart);
+ if (MailboxBase % sizeof(UINT64) != 0) {
+ MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64);
+ }
+
+ // Update variables used in the Pen code
+ *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase;
+ *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase;
+
+ for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+ // Clear the jump address at spin-table slot
+ CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64);
+ *((UINTN*)(CoreMailbox)) = 0x0;
+
+ // Clear the jump address and set Core# at mp-parking slot
+ CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB;
+ *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0;
+ *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum;
+
+ // Update table entry to be consumed by FDT parser
+ ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox;
+ }
+
+ // flush the cache before launching secondary cores
+ WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize);
+
+ return PenBase;
+}
+
+
+EFI_STATUS
+EFIAPI
+MpBootDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ AMD_MP_BOOT_PROTOCOL *MpBootProtocol;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ UINTN CoreNum;
+ EFI_PHYSICAL_ADDRESS PenBase;
+
+ DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n"));
+
+ MpBootProtocol = NULL;
+ Status = gBS->LocateProtocol (
+ &gAmdMpBootProtocolGuid,
+ NULL,
+ (VOID **)&MpBootProtocol
+ );
+ if (EFI_ERROR (Status) || MpBootProtocol == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((VOID *)MpBootProtocol->MpBootInfo == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase;
+ if ((VOID *)MpParkingBase == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable;
+ if (ArmCoreInfoTable == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount;
+ if (ArmCoreCount < 2) {
+ DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount));
+ return EFI_UNSUPPORTED;
+ }
+
+ MpParkingSize = ArmCoreCount * SIZE_4KB;
+ if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n",
+ MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount));
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ // Move secondary cores to our new Pen
+ PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount);
+ for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+ MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf new file mode 100644 index 0000000000..ec63cd36e8 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf @@ -0,0 +1,53 @@ +#/* @file
+#
+# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MpBootDxe
+ FILE_GUID = ff3f9c9b-6d36-4787-9144-6b22acba5e9b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = MpBootDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources.common]
+ MpBootDxe.c
+
+[Sources.AARCH64]
+ MpBootHelper.S
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ CacheMaintenanceLib
+ BaseMemoryLib
+ DebugLib
+
+[Protocols]
+ gAmdMpBootProtocolGuid ## CONSUMED
+
+[Depex]
+ gAmdMpBootProtocolGuid
diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S new file mode 100644 index 0000000000..c16cc59a1e --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S @@ -0,0 +1,87 @@ +//
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//**
+// Derived from:
+// ArmPkg/Library/BdsLib/AArch64/BdsLinuxLoaderHelper.S
+//
+//**
+
+/* Secondary core pens for AArch64 Linux booting.
+
+ This code is placed in Linux kernel memory and marked reserved. UEFI ensures
+ that the secondary cores get to this pen and the kernel can then start the
+ cores from here.
+ NOTE: This code must be self-contained.
+*/
+
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(SecondariesPenStart)
+ASM_GLOBAL SecondariesPenEnd
+
+ASM_PFX(SecondariesPenStart):
+ // Registers x0-x3 are reserved for future use and should be set to zero.
+ mov x0, xzr
+ mov x1, xzr
+ mov x2, xzr
+ mov x3, xzr
+
+ mrs x4, mpidr_el1 // Get MPCore register
+ and x5, x4, #ARM_CORE_MASK // Get core number
+ and x4, x4, #ARM_CLUSTER_MASK // Get cluster number
+
+ add x4, x5, x4, LSR #7 // Add scaled cluster number to core number
+ mov x6, x4 // Save a copy to compute mp-parking offset
+
+ ldr x5, AsmMailboxBase // Get mailbox addr relative to PC
+ lsl x4, x4, 3 // Add 8-byte offset for this core
+ add x4, x4, x5 //
+
+ ldr x5, AsmParkingBase // Get mp-parking addr relative to PC
+ lsl x6, x6, 12 // Add 4K-byte offset for this core
+ add x6, x6, x5 //
+
+ mov x5, 1 // Get mp-parking id# at 2K offset
+ lsl x5, x5, 11 //
+ add x5, x5, x6 //
+ ldr x10, [x5] //
+
+1: ldr x5, [x4] // Load jump-addr from spin-table mailbox
+ cmp xzr, x5 // Has the value been set?
+ b.ne 4f // If so, break out of loop
+
+ ldr x5, [x6] // Load mp-parking id#
+ cmp w10, w5 // Is it my id?
+ b.ne 2f // If not, continue polling
+
+ ldr x5, [x6, 8] // Load jump-addr from mp-parking
+ cmp xzr, x5 // Has the value been set?
+ b.ne 3f // If so, break out of loop
+
+2: wfe // Wait a bit
+ b 1b // Wait over, check again
+
+3: str xzr, [x6, 8] // Clear to acknowledge
+ mov x0, x6 // Return mp-parking address
+4: br x5 // Jump to new addr
+
+.align 3 // Make sure the variable below is 8 byte aligned.
+ .global AsmParkingBase
+AsmParkingBase: .xword 0xdeaddeadbeefbeef
+ .global AsmMailboxBase
+AsmMailboxBase: .xword 0xdeaddeadbeefbeef
+
+SecondariesPenEnd:
diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c new file mode 100644 index 0000000000..fd5bb96f7c --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -0,0 +1,237 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Common/CoreState.h>
+#include <Library/ArmSmcLib.h>
+#include <IndustryStandard/ArmStdSmc.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Protocol/AmdMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 };
+STATIC AMD_MP_BOOT_PROTOCOL mAmdMpBootProtocol = { 0 };
+STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 };
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ );
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ );
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+ OUT UINTN *MpParkingSize
+ );
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+ ARM_CORE_INFO *ArmCoreInfo,
+ EFI_PHYSICAL_ADDRESS SecondaryEntry
+ );
+
+
+#pragma pack(push, 1)
+typedef struct _PMU_INFO {
+ UINT32 MpId;
+ UINT32 PmuSpi;
+} PMU_INFO;
+
+STATIC
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+
+EFI_STATUS
+EFIAPI
+PlatInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ EFI_HANDLE Handle = NULL;
+
+ DEBUG ((EFI_D_ERROR, "PlatInitDxe Loaded\n"));
+
+ // Get core information
+ ArmCoreCount = 0;
+ ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+ ASSERT (ArmCoreCount != 0);
+
+ // Install CoreInfo Protocol
+ mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable;
+ mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId;
+ mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gAmdMpCoreInfoProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID *)&mAmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Install MP-Boot Protocol
+ if (!FixedPcdGetBool (PcdPsciOsSupport) &&
+ FixedPcdGetBool (PcdTrustedFWSupport)) {
+ // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory
+ MpParkingBase = 0;
+ MpParkingSize = ArmCoreCount * SIZE_4KB;
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType,
+ EFI_SIZE_TO_PAGES (MpParkingSize),
+ &MpParkingBase);
+ if (EFI_ERROR (Status) || MpParkingBase == 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase."));
+ } else {
+ mAmdMpBootInfo.MpParkingBase = MpParkingBase;
+ mAmdMpBootInfo.MpParkingSize = MpParkingSize;
+ mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable;
+ mAmdMpBootInfo.ArmCoreCount = ArmCoreCount;
+
+ mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore;
+ mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo;
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gAmdMpBootProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID *)&mAmdMpBootProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol."));
+ gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize));
+ }
+ }
+ }
+
+ return Status;
+}
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ )
+{
+ EFI_HOB_GUID_TYPE *Hob;
+
+ ASSERT (NumEntries != NULL);
+
+ Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+ if (Hob == NULL) {
+ return NULL;
+ }
+
+ *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+ return GET_GUID_HOB_DATA (Hob);
+}
+
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ )
+{
+ UINT32 i;
+
+ for (i = 0; i < MAX_CPUS; ++i) {
+ if (mPmuInfo[ i ].MpId == MpId) {
+ *PmuSpi = mPmuInfo[ i ].PmuSpi;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+ OUT UINTN *MpParkingSize
+ )
+{
+ ASSERT (MpParkingSize != NULL);
+
+ *MpParkingSize = mAmdMpBootInfo.MpParkingBase;
+ return mAmdMpBootInfo.MpParkingBase;
+}
+
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+ ARM_CORE_INFO *ArmCoreInfo,
+ EFI_PHYSICAL_ADDRESS SecondaryEntry
+ )
+{
+ ARM_SMC_ARGS SmcRegs = {0};
+ UINTN MpId;
+
+ MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId);
+
+ SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64;
+ SmcRegs.Arg1 = MpId;
+ SmcRegs.Arg2 = SecondaryEntry;
+ SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext);
+ ArmCallSmc (&SmcRegs);
+
+ if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS ||
+ SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) {
+ DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId));
+ } else {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId));
+ }
+}
diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf new file mode 100644 index 0000000000..15f46be651 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -0,0 +1,62 @@ +#/* @file
+#
+# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatInitDxe
+ FILE_GUID = 6ae8bdbc-c0eb-40c5-9b3e-18119c0e2710
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatInitDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources.common]
+ PlatInitDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ ArmSmcLib
+ HobLib
+ PcdLib
+ DebugLib
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## PRODUCER
+ gAmdMpBootProtocolGuid ## PRODUCER
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+
+[Depex]
+ TRUE
diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c new file mode 100644 index 0000000000..61e373406b --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -0,0 +1,256 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Ppi/IscpPpi.h>
+#include <Iscp.h>
+
+/*----------------------------------------------------------------------------------------
+ * G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+//
+// CoreInfo table
+//
+STATIC ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+ },
+ {
+ // Cluster 1, Core 0
+ 0x1, 0x0,
+ },
+ {
+ // Cluster 1, Core 1
+ 0x1, 0x1,
+ },
+ {
+ // Cluster 2, Core 0
+ 0x2, 0x0,
+ },
+ {
+ // Cluster 2, Core 1
+ 0x2, 0x1,
+ },
+ {
+ // Cluster 3, Core 0
+ 0x3, 0x0,
+ },
+ {
+ // Cluster 3, Core 1
+ 0x3, 0x1,
+ }
+};
+
+//
+// Core count
+//
+STATIC UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+
+
+/*----------------------------------------------------------------------------------------
+ * P P I L I S T
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_ISCP_PPI *PeiIscpPpi;
+
+
+/*----------------------------------------------------------------------------------------
+ * P P I D E S C R I P T O R
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatInitPpiDescriptor =
+{
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gAmdStyxPlatInitPpiGuid,
+ NULL
+};
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ * PlatInitPeiEntryPoint
+ *
+ * Description:
+ * Entry point of the PlatInit PEI module.
+ *
+ * Control flow:
+ * Query platform parameters via ISCP.
+ *
+ * Parameters:
+ * @param[in] FfsHeader EFI_PEI_FILE_HANDLE
+ * @param[in] **PeiServices Pointer to the PEI Services Table.
+ *
+ * @return EFI_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+EFI_STATUS
+EFIAPI
+PlatInitPeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FfsHeader,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ AMD_MEMORY_RANGE_DESCRIPTOR IscpMemDescriptor = {0};
+ ISCP_FUSE_INFO IscpFuseInfo = {0};
+ ISCP_CPU_RESET_INFO CpuResetInfo = {0};
+#if DO_XGBE == 1
+ ISCP_MAC_INFO MacAddrInfo = {0};
+ UINT64 MacAddr0, MacAddr1;
+#endif
+ UINTN CpuCoreCount, CpuMap, CpuMapSize;
+ UINTN Index, CoreNum;
+ UINT32 *CpuIdReg = (UINT32 *)FixedPcdGet32 (PcdCpuIdRegister);
+
+ DEBUG ((EFI_D_ERROR, "PlatInit PEIM Loaded\n"));
+
+ // CPUID
+ PcdSet32 (PcdSocCpuId, *CpuIdReg);
+ DEBUG ((EFI_D_ERROR, "SocCpuId = 0x%X\n", PcdGet32 (PcdSocCpuId)));
+
+ // Update core count based on PCD option
+ if (mAmdCoreCount > PcdGet32 (PcdSocCoreCount)) {
+ mAmdCoreCount = PcdGet32 (PcdSocCoreCount);
+ }
+
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ // Get fuse information from ISCP
+ Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo);
+ ASSERT_EFI_ERROR (Status);
+
+ CpuMap = IscpFuseInfo.SocConfiguration.CpuMap;
+ CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount;
+ CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8;
+
+ ASSERT (CpuMap != 0);
+ ASSERT (CpuCoreCount != 0);
+ ASSERT (CpuCoreCount <= CpuMapSize);
+
+ // Update core count based on fusing
+ if (mAmdCoreCount > CpuCoreCount) {
+ mAmdCoreCount = CpuCoreCount;
+ }
+ }
+
+ //
+ // Update per-core information from ISCP
+ //
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n"));
+ } else {
+ //
+ // Walk CPU map to enumerate active cores
+ //
+ for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) {
+ if (CpuMap & 1) {
+ CpuResetInfo.CoreNum = CoreNum;
+ Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction (
+ PeiServices, &CpuResetInfo );
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED);
+ ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED);
+
+ mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
+ mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
+
+ DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n",
+ Index, mAmdMpCoreInfoTable[Index].ClusterId,
+ mAmdMpCoreInfoTable[Index].CoreId));
+
+ // Next core in Table
+ ++Index;
+ }
+ // Next core in Map
+ CpuMap >>= 1;
+ }
+
+ // Update core count based on CPU map
+ if (mAmdCoreCount > Index) {
+ mAmdCoreCount = Index;
+ }
+ }
+
+ // Update SocCoreCount on Dynamic PCD
+ if (PcdGet32 (PcdSocCoreCount) != mAmdCoreCount) {
+ PcdSet32 (PcdSocCoreCount, mAmdCoreCount);
+ }
+
+ DEBUG ((EFI_D_ERROR, "SocCoreCount = %d\n", PcdGet32 (PcdSocCoreCount)));
+
+ // Build AmdMpCoreInfo HOB
+ BuildGuidDataHob (&gAmdStyxMpCoreInfoGuid, mAmdMpCoreInfoTable, sizeof (ARM_CORE_INFO) * mAmdCoreCount);
+
+ // Get SystemMemorySize from ISCP
+ IscpMemDescriptor.Size0 = 0;
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ // Update SystemMemorySize on Dynamic PCD
+ if (IscpMemDescriptor.Size0) {
+ PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0);
+ }
+ }
+ if (IscpMemDescriptor.Size0 == 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n"));
+ }
+
+ DEBUG ((EFI_D_ERROR, "SystemMemorySize = %ld\n", PcdGet64 (PcdSystemMemorySize)));
+
+#if DO_XGBE == 1
+ // Get MAC Address from ISCP
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiIscpPpi->ExecuteGetMacAddressTransaction (
+ PeiServices, &MacAddrInfo );
+ ASSERT_EFI_ERROR (Status);
+
+ MacAddr0 = MacAddr1 = 0;
+ for (Index = 0; Index < 6; ++Index) {
+ MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8);
+ MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8);
+ }
+ PcdSet64 (PcdEthMacA, MacAddr0);
+ PcdSet64 (PcdEthMacB, MacAddr1);
+ }
+
+ DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA)));
+ DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB)));
+#endif
+
+ // Let other PEI modules know we're done!
+ Status = (*PeiServices)->InstallPpi (PeiServices, &mPlatInitPpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf new file mode 100644 index 0000000000..9f141946ae --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -0,0 +1,76 @@ +#/* @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatInitPei
+ FILE_GUID = 769694a4-2572-4f29-a5bb-33d7df7be001
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = PlatInitPeiEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources]
+ PlatInitPei.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ BaseMemoryLib
+ HobLib
+ PcdLib
+ DebugLib
+ ArmLib
+ ArmSmcLib
+
+[Ppis]
+ gPeiIscpPpiGuid ## CONSUMER
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMER
+ gAmdStyxPlatInitPpiGuid ## PRODUCER
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## PRODUCER
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdCpuIdRegister
+
+[Depex]
+ gPeiIscpPpiGuid
+
diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c new file mode 100644 index 0000000000..4bf9fc3994 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -0,0 +1,994 @@ +/** @file
+ Static SMBIOS Table for ARM platform
+ Derived from EmulatorPkg package
+
+ Note SMBIOS 2.7.1 Required structures:
+ BIOS Information (Type 0)
+ System Information (Type 1)
+ Board Information (Type 2)
+ System Enclosure (Type 3)
+ Processor Information (Type 4) - CPU Driver
+ Cache Information (Type 7) - For cache that is external to processor
+ System Slots (Type 9) - If system has slots
+ Physical Memory Array (Type 16)
+ Memory Device (Type 17) - For each socketed system-memory Device
+ Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array
+ System Boot Information (Type 32)
+
+ Copyright (c) 2012, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Guid/SmBios.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Protocol/AmdIscpDxeProtocol.h>
+
+/*----------------------------------------------------------------------------------------
+ * E X T E R N S
+ *----------------------------------------------------------------------------------------
+ */
+extern EFI_BOOT_SERVICES *gBS;
+
+
+/*----------------------------------------------------------------------------------------
+ * G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_SMBIOS_PROTOCOL *mSmbiosProtocol;
+STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+STATIC ISCP_SMBIOS_INFO mSmbiosInfo;
+
+
+/***********************************************************************
+ SMBIOS data definition TYPE0 BIOS Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {
+ { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 },
+ 1, // Vendor String
+ 2, // BiosVersion String
+ 0xE000, // BiosSegment
+ 3, // BiosReleaseDate String
+ 0x7F, // BiosSize
+ { // BiosCharacteristics
+ 0, // Reserved :2; ///< Bits 0-1.
+ 0, // Unknown :1;
+ 0, // BiosCharacteristicsNotSupported :1;
+ 0, // IsaIsSupported :1;
+ 0, // McaIsSupported :1;
+ 0, // EisaIsSupported :1;
+ 0, // PciIsSupported :1;
+ 0, // PcmciaIsSupported :1;
+ 0, // PlugAndPlayIsSupported :1;
+ 0, // ApmIsSupported :1;
+ 1, // BiosIsUpgradable :1;
+ 1, // BiosShadowingAllowed :1;
+ 0, // VlVesaIsSupported :1;
+ 0, // EscdSupportIsAvailable :1;
+ 0, // BootFromCdIsSupported :1;
+ 1, // SelectableBootIsSupported :1;
+ 0, // RomBiosIsSocketed :1;
+ 0, // BootFromPcmciaIsSupported :1;
+ 0, // EDDSpecificationIsSupported :1;
+ 0, // JapaneseNecFloppyIsSupported :1;
+ 0, // JapaneseToshibaFloppyIsSupported :1;
+ 0, // Floppy525_360IsSupported :1;
+ 0, // Floppy525_12IsSupported :1;
+ 0, // Floppy35_720IsSupported :1;
+ 0, // Floppy35_288IsSupported :1;
+ 0, // PrintScreenIsSupported :1;
+ 0, // Keyboard8042IsSupported :1;
+ 0, // SerialIsSupported :1;
+ 0, // PrinterIsSupported :1;
+ 0, // CgaMonoIsSupported :1;
+ 0, // NecPc98 :1;
+ 0 // ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+ ///< and bits 48-63 reserved for System Vendor.
+ },
+ { // BIOSCharacteristicsExtensionBytes[]
+ 0x81, // AcpiIsSupported :1;
+ // UsbLegacyIsSupported :1;
+ // AgpIsSupported :1;
+ // I2OBootIsSupported :1;
+ // Ls120BootIsSupported :1;
+ // AtapiZipDriveBootIsSupported :1;
+ // Boot1394IsSupported :1;
+ // SmartBatteryIsSupported :1;
+ // BIOSCharacteristicsExtensionBytes[1]
+ 0x0a, // BiosBootSpecIsSupported :1;
+ // FunctionKeyNetworkBootIsSupported :1;
+ // TargetContentDistributionEnabled :1;
+ // UefiSpecificationSupported :1;
+ // VirtualMachineSupported :1;
+ // ExtensionByte2Reserved :3;
+ },
+ 0x00, // SystemBiosMajorRelease
+ 0x01, // SystemBiosMinorRelease
+ 0xFF, // EmbeddedControllerFirmwareMajorRelease
+ 0xFF, // EmbeddedControllerFirmwareMinorRelease
+};
+
+STATIC CHAR8 CONST * CONST mBIOSInfoType0Strings[] = {
+ "github.com/tianocore/", // Vendor String
+ __TIME__, // BiosVersion String
+ __DATE__, // BiosReleaseDate String
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE1 System Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE1 mSysInfoType1 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } },
+ SystemWakeupTypePowerSwitch,
+ 5, // SKUNumber String
+ 6, // Family String
+};
+STATIC CHAR8 CONST * CONST mSysInfoType1Strings[] = {
+ "AMD",
+ "Seattle",
+ "1.0",
+ "System Serial#",
+ "System SKU#",
+ "edk2",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE2 Board Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE2 mBoardInfoType2 = {
+ { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ 5, // AssetTag String
+ { // FeatureFlag
+ 1, // Motherboard :1;
+ 0, // RequiresDaughterCard :1;
+ 0, // Removable :1;
+ 0, // Replaceable :1;
+ 0, // HotSwappable :1;
+ 0, // Reserved :3;
+ },
+ 6, // LocationInChassis String
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ { 0 } // ContainedObjectHandles[1];
+};
+STATIC CHAR8 CONST * CONST mBoardInfoType2Strings[] = {
+ "AMD",
+ "Seattle",
+ "1.0",
+ "Base Board Serial#",
+ "Base Board Asset Tag#",
+ "Part Component",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE3 Enclosure Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 },
+ 1, // Manufacturer String
+ MiscChassisTypeLapTop, // Type;
+ 2, // Version String
+ 3, // SerialNumber String
+ 4, // AssetTag String
+ ChassisStateSafe, // BootupState;
+ ChassisStateSafe, // PowerSupplyState;
+ ChassisStateSafe, // ThermalState;
+ ChassisSecurityStatusNone,// SecurityStatus;
+ { 0, 0, 0, 0 }, // OemDefined[4];
+ 0, // Height;
+ 0, // NumberofPowerCords;
+ 0, // ContainedElementCount;
+ 0, // ContainedElementRecordLength;
+ { { 0 } }, // ContainedElements[1];
+};
+STATIC CHAR8 CONST * CONST mEnclosureInfoType3Strings[] = {
+ "AMD",
+ "1.0",
+ "Chassis Board Serial#",
+ "Chassis Board Asset Tag#",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE4 Processor Information
+************************************************************************/
+STATIC SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = {
+ { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0},
+ 1, // Socket String
+ ProcessorOther, // ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.
+ ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY2_DATA.
+ 2, // ProcessorManufacture String;
+ { // ProcessorId;
+ { // PROCESSOR_SIGNATURE
+ 0, // ProcessorSteppingId:4;
+ 0, // ProcessorModel: 4;
+ 0, // ProcessorFamily: 4;
+ 0, // ProcessorType: 2;
+ 0, // ProcessorReserved1: 2;
+ 0, // ProcessorXModel: 4;
+ 0, // ProcessorXFamily: 8;
+ 0, // ProcessorReserved2: 4;
+ },
+
+ { // PROCESSOR_FEATURE_FLAGS
+ 0, // ProcessorFpu :1;
+ 0, // ProcessorVme :1;
+ 0, // ProcessorDe :1;
+ 0, // ProcessorPse :1;
+ 0, // ProcessorTsc :1;
+ 0, // ProcessorMsr :1;
+ 0, // ProcessorPae :1;
+ 0, // ProcessorMce :1;
+ 0, // ProcessorCx8 :1;
+ 0, // ProcessorApic :1;
+ 0, // ProcessorReserved1 :1;
+ 0, // ProcessorSep :1;
+ 0, // ProcessorMtrr :1;
+ 0, // ProcessorPge :1;
+ 0, // ProcessorMca :1;
+ 0, // ProcessorCmov :1;
+ 0, // ProcessorPat :1;
+ 0, // ProcessorPse36 :1;
+ 0, // ProcessorPsn :1;
+ 0, // ProcessorClfsh :1;
+ 0, // ProcessorReserved2 :1;
+ 0, // ProcessorDs :1;
+ 0, // ProcessorAcpi :1;
+ 0, // ProcessorMmx :1;
+ 0, // ProcessorFxsr :1;
+ 0, // ProcessorSse :1;
+ 0, // ProcessorSse2 :1;
+ 0, // ProcessorSs :1;
+ 0, // ProcessorReserved3 :1;
+ 0, // ProcessorTm :1;
+ 0, // ProcessorReserved4 :2;
+ }
+ },
+ 3, // ProcessorVersion String;
+ { // Voltage;
+ 1, // ProcessorVoltageCapability5V :1;
+ 1, // ProcessorVoltageCapability3_3V :1;
+ 1, // ProcessorVoltageCapability2_9V :1;
+ 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero.
+ 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero.
+ 0 // ProcessorVoltageIndicateLegacy :1;
+ },
+ 0, // ExternalClock;
+ 0, // MaxSpeed;
+ 0, // CurrentSpeed;
+ 0x41, // Status;
+ ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.
+ 0, // L1CacheHandle;
+ 0, // L2CacheHandle;
+ 0, // L3CacheHandle;
+ 4, // SerialNumber;
+ 5, // AssetTag;
+ 6, // PartNumber;
+ 0, // CoreCount;
+ 0, // EnabledCoreCount;
+ 0, // ThreadCount;
+ 0, // ProcessorCharacteristics;
+ ProcessorFamilyARM, // ARM Processor Family;
+};
+
+STATIC CHAR8 CONST * CONST mProcessorInfoType4Strings[] = {
+ "Socket",
+ "ARM",
+#ifdef ARM_CPU_AARCH64
+ "v8",
+#else
+ "v7",
+#endif
+ "1.0",
+ "1.0",
+ "1.0",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE7 Cache Information
+************************************************************************/
+STATIC SMBIOS_TABLE_TYPE7 mCacheInfoType7 = {
+ { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+ 1, // SocketDesignation String
+ 0x018A, // Cache Configuration
+ 0x00FF, // Maximum Size 256k
+ 0x00FF, // Install Size 256k
+ { // Supported SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ { // Current SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ 0, // Cache Speed unknown
+ CacheErrorMultiBit, // Error Correction Multi
+ CacheTypeUnknown, // System Cache Type
+ CacheAssociativity2Way // Associativity
+};
+STATIC CONST CHAR8 *mCacheInfoType7Strings[] = {
+ "Cache1",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE9 System Slot Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 },
+ 1, // SlotDesignation String
+ SlotTypeOther, // SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
+ SlotDataBusWidthOther, // SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+ SlotUsageAvailable, // CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
+ SlotLengthOther, // SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
+ 0, // SlotID;
+ { // SlotCharacteristics1;
+ 1, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0, // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2;
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0, // Reserved :5; ///< Set to 0.
+ },
+ 0, // SegmentGroupNum;
+ 0, // BusNum;
+ 0, // DevFuncNum;
+};
+STATIC CHAR8 CONST * CONST mSysSlotInfoType9Strings[] = {
+ "SD Card",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE16 Physical Memory ArrayInformation
+************************************************************************/
+STATIC SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = {
+ { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 },
+ MemoryArrayLocationSystemBoard, // Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+ MemoryArrayUseSystemMemory, // Use; ///< The enumeration value from MEMORY_ARRAY_USE.
+ MemoryErrorCorrectionUnknown, // MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+ 0x80000000, // MaximumCapacity;
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 1, // NumberOfMemoryDevices;
+ 0x3fffffffffffffffULL, // ExtendedMaximumCapacity;
+};
+STATIC CHAR8 CONST * CONST mPhyMemArrayInfoType16Strings[] = {
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE17 Memory Device Information
+************************************************************************/
+STATIC SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
+ { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
+ 0, // MemoryArrayHandle;
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 0xFFFF, // TotalWidth;
+ 0xFFFF, // DataWidth;
+ 0xFFFF, // Size;
+ MemoryFormFactorUnknown, // FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.
+ 0xff, // DeviceSet;
+ 1, // DeviceLocator String
+ 2, // BankLocator String
+ MemoryTypeDram, // MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.
+ { // TypeDetail;
+ 0, // Reserved :1;
+ 0, // Other :1;
+ 1, // Unknown :1;
+ 0, // FastPaged :1;
+ 0, // StaticColumn :1;
+ 0, // PseudoStatic :1;
+ 0, // Rambus :1;
+ 0, // Synchronous :1;
+ 0, // Cmos :1;
+ 0, // Edo :1;
+ 0, // WindowDram :1;
+ 0, // CacheDram :1;
+ 0, // Nonvolatile :1;
+ 0, // Registered :1;
+ 0, // Unbuffered :1;
+ 0, // Reserved1 :1;
+ },
+ 0, // Speed;
+ 3, // Manufacturer String
+ 0, // SerialNumber String
+ 0, // AssetTag String
+ 0, // PartNumber String
+ 0, // Attributes;
+ 0, // ExtendedSize;
+ 0, // ConfiguredMemoryClockSpeed;
+};
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+STATIC CHAR8 CONST *mMemDevInfoType17Strings[ 7 ] = {0};
+#else
+STATIC CHAR8 CONST * CONST mMemDevInfoType17Strings[] = {
+ "OS Virtual Memory",
+ "malloc",
+ "OSV",
+ NULL
+};
+#endif
+
+/***********************************************************************
+ SMBIOS data definition TYPE19 Memory Array Mapped Address Information
+************************************************************************/
+STATIC SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = {
+ { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 },
+ 0x80000000, // StartingAddress;
+ 0xbfffffff, // EndingAddress;
+ 0, // MemoryArrayHandle;
+ 1, // PartitionWidth;
+ 0, // ExtendedStartingAddress;
+ 0, // ExtendedEndingAddress;
+};
+STATIC CHAR8 CONST * CONST mMemArrMapInfoType19Strings[] = {
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE32 Boot Information
+************************************************************************/
+STATIC CONST SMBIOS_TABLE_TYPE32 mBootInfoType32 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 },
+ { 0, 0, 0, 0, 0, 0 }, // Reserved[6];
+ BootInformationStatusNoError // BootStatus
+};
+
+STATIC CHAR8 CONST * CONST mBootInfoType32Strings[] = {
+ NULL
+};
+
+
+/**
+
+ Create SMBIOS record.
+
+ Converts a fixed SMBIOS structure and an array of pointers to strings into
+ an SMBIOS record where the strings are cat'ed on the end of the fixed record
+ and terminated via a double NULL and add to SMBIOS table.
+
+ SMBIOS_TABLE_TYPE32 gSmbiosType12 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 },
+ 1 // StringCount
+ };
+
+ CHAR8 *gSmbiosType12Strings[] = {
+ "Not Found",
+ NULL
+ };
+
+ ...
+
+ LogSmbiosData (
+ (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12,
+ gSmbiosType12Strings
+ );
+
+ @param Template Fixed SMBIOS structure, required.
+ @param StringArray Array of strings to convert to an SMBIOS string pack.
+ NULL is OK.
+**/
+
+STATIC
+EFI_STATUS
+EFIAPI
+LogSmbiosData (
+ IN EFI_SMBIOS_TABLE_HEADER *Template,
+ IN CONST CHAR8* CONST *StringPack
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_TABLE_HEADER *Record;
+ UINTN Index;
+ UINTN StringSize;
+ UINTN Size;
+ CHAR8 *Str;
+
+
+ // Calculate the size of the fixed record and optional string pack
+ Size = Template->Length;
+ if (StringPack == NULL) {
+ // At least a double null is required
+ Size += 2;
+ } else {
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ Size += StringSize;
+ }
+ if (StringPack[0] == NULL) {
+ // At least a double null is required
+ Size += 1;
+ }
+
+ // Don't forget the terminating double null
+ Size += 1;
+ }
+
+ // Copy over Template
+ Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (Record == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (Record, Template, Template->Length);
+
+ // Append string pack
+ Str = ((CHAR8 *)Record) + Record->Length;
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ CopyMem (Str, StringPack[Index], StringSize);
+ Str += StringSize;
+ }
+ *Str = 0;
+
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbiosProtocol->Add (
+ mSmbiosProtocol,
+ gImageHandle,
+ &SmbiosHandle,
+ Record
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ FreePool (Record);
+ return Status;
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE0 BIOS Information
+************************************************************************/
+STATIC
+VOID
+BIOSInfoUpdateSmbiosType0 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBIOSInfoType0, mBIOSInfoType0Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE1 System Information
+************************************************************************/
+STATIC
+VOID
+SysInfoUpdateSmbiosType1 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysInfoType1, mSysInfoType1Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE2 Board Information
+************************************************************************/
+STATIC
+VOID
+BoardInfoUpdateSmbiosType2 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBoardInfoType2, mBoardInfoType2Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE3 Enclosure Information
+************************************************************************/
+STATIC
+VOID
+EnclosureInfoUpdateSmbiosType3 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mEnclosureInfoType3, mEnclosureInfoType3Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE4 Processor Information
+************************************************************************/
+STATIC
+VOID
+ProcessorInfoUpdateSmbiosType4 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE4_SMBIOS_INFO *SmbiosT4 = &mSmbiosInfo.SmbiosCpuBuffer.T4[0];
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType4 from ISCP.\n"));
+
+ mProcessorInfoType4.ProcessorType = SmbiosT4->T4ProcType;
+ mProcessorInfoType4.ProcessorFamily = SmbiosT4->T4ProcFamily;
+ mProcessorInfoType4.ProcessorFamily2 = SmbiosT4->T4ProcFamily2;
+ mProcessorInfoType4.ProcessorCharacteristics = SmbiosT4->T4ProcCharacteristics;
+ mProcessorInfoType4.MaxSpeed = SmbiosT4->T4MaxSpeed;
+ mProcessorInfoType4.CurrentSpeed = SmbiosT4->T4CurrentSpeed;
+ mProcessorInfoType4.CoreCount = SmbiosT4->T4CoreCount;
+ mProcessorInfoType4.EnabledCoreCount = SmbiosT4->T4CoreEnabled;
+ mProcessorInfoType4.ThreadCount = SmbiosT4->T4ThreadCount;
+ mProcessorInfoType4.ProcessorUpgrade = SmbiosT4->T4ProcUpgrade;
+ mProcessorInfoType4.Status= (UINT8)SmbiosT4->T4Status;
+ mProcessorInfoType4.ExternalClock = SmbiosT4->T4ExternalClock;
+ CopyMem (&mProcessorInfoType4.ProcessorId.Signature,
+ &SmbiosT4->T4ProcId.ProcIDLsd, sizeof(UINT32));
+ CopyMem (&mProcessorInfoType4.ProcessorId.FeatureFlags,
+ &SmbiosT4->T4ProcId.ProcIDMsd, sizeof(UINT32));
+ CopyMem (&mProcessorInfoType4.Voltage,
+ &SmbiosT4->T4Voltage, sizeof(UINT8));
+#else
+ mProcessorInfoType4.ProcessorType = CentralProcessor;
+ mProcessorInfoType4.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ mProcessorInfoType4.ProcessorFamily2 = ProcessorFamilyARM;
+ #ifdef ARM_CPU_AARCH64
+ mProcessorInfoType4.ProcessorCharacteristics = 0x6C;
+ #else
+ mProcessorInfoType4.ProcessorCharacteristics = 0x68;
+ #endif
+ mProcessorInfoType4.MaxSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz
+ mProcessorInfoType4.CurrentSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz
+ mProcessorInfoType4.CoreCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.EnabledCoreCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.ThreadCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.ProcessorUpgrade = ProcessorUpgradeDaughterBoard;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE7 Cache Information
+************************************************************************/
+STATIC
+VOID
+CacheInfoUpdateSmbiosType7 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE7_SMBIOS_INFO *SmbiosT7;
+ SMBIOS_TABLE_TYPE7 dstType7 = {{0}};
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType7 from ISCP.\n"));
+
+ CopyMem ((VOID *) &dstType7.Hdr, (VOID *) &mCacheInfoType7.Hdr, sizeof (SMBIOS_STRUCTURE));
+ dstType7.SocketDesignation = 1; // "L# Cache"
+
+ // L1 cache settings
+ mCacheInfoType7Strings[0] = "L1 Cache";
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+ // L2 cache settings
+ mCacheInfoType7Strings[0] = "L2 Cache";
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+ // L3 cache settings
+ mCacheInfoType7Strings[0] = "L3 Cache";
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+#else
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings);
+#endif
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE9 System Slot Information
+************************************************************************/
+STATIC
+VOID
+SysSlotInfoUpdateSmbiosType9 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysSlotInfoType9, mSysSlotInfoType9Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE16 Physical Memory Array Information
+************************************************************************/
+STATIC
+VOID
+PhyMemArrayInfoUpdateSmbiosType16 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE16_SMBIOS_INFO *SmbiosT16 = &mSmbiosInfo.SmbiosMemBuffer.T16;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType16 from ISCP.\n"));
+
+ mPhyMemArrayInfoType16.Location = SmbiosT16->Location;
+ mPhyMemArrayInfoType16.Use = SmbiosT16->Use;
+ mPhyMemArrayInfoType16.MemoryErrorCorrection = SmbiosT16->MemoryErrorCorrection;
+ mPhyMemArrayInfoType16.NumberOfMemoryDevices = SmbiosT16->NumberOfMemoryDevices;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE17 Memory Device Information
+************************************************************************/
+STATIC
+VOID
+MemDevInfoUpdatedstType17 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ SMBIOS_TABLE_TYPE17 dstType17 = {{0}};
+ ISCP_TYPE17_SMBIOS_INFO *srcType17;
+ UINTN i, j, StrIndex, LastIndex;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType17 from ISCP.\n"));
+
+ LastIndex = (sizeof(mMemDevInfoType17Strings) / sizeof (CHAR8 *)) - 1;
+ for (i = 0; i < 2; ++i) {
+ for (j = 0; j < 2; ++j) {
+ srcType17 = &mSmbiosInfo.SmbiosMemBuffer.T17[i][j];
+
+ CopyMem ((VOID *) &dstType17.Hdr, (VOID *) &mMemDevInfoType17.Hdr, sizeof (SMBIOS_STRUCTURE));
+ dstType17.MemoryArrayHandle = srcType17->Handle;
+ dstType17.TotalWidth = srcType17->TotalWidth;
+ dstType17.DataWidth = srcType17->DataWidth;
+ dstType17.Size = srcType17->MemorySize;
+ dstType17.FormFactor = srcType17->FormFactor;
+ dstType17.DeviceSet = srcType17->DeviceSet;
+ dstType17.MemoryType = srcType17->MemoryType;
+
+ CopyMem ((VOID *) &dstType17.TypeDetail, (VOID *) &mMemDevInfoType17.TypeDetail, sizeof (UINT16));
+ dstType17.Speed = srcType17->Speed;
+ dstType17.Attributes = srcType17->Attributes;
+ dstType17.ExtendedSize = srcType17->ExtSize;
+ dstType17.ConfiguredMemoryClockSpeed = srcType17->ConfigSpeed;
+
+ // Build table of TYPE17 strings
+ StrIndex = 0;
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->DeviceLocator) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->DeviceLocator;
+ dstType17.DeviceLocator = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.DeviceLocator = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->BankLocator) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->BankLocator;
+ dstType17.BankLocator = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.BankLocator = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->ManufacturerIdCode) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->ManufacturerIdCode;
+ dstType17.Manufacturer = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.Manufacturer = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->SerialNumber) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->SerialNumber;
+ dstType17.SerialNumber = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.SerialNumber = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->PartNumber) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->PartNumber;
+ dstType17.PartNumber = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.PartNumber = 0;
+ }
+
+ mMemDevInfoType17Strings[StrIndex] = NULL;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType17, mMemDevInfoType17Strings);
+ }
+ }
+#else
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings);
+#endif
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE19 Memory Array Map Information
+************************************************************************/
+STATIC
+VOID
+MemArrMapInfoUpdateSmbiosType19 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE19_SMBIOS_INFO *SmbiosT19 = &mSmbiosInfo.SmbiosMemBuffer.T19;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType19 from ISCP.\n"));
+
+ mMemArrMapInfoType19.StartingAddress = SmbiosT19->StartingAddr;
+ mMemArrMapInfoType19.EndingAddress = SmbiosT19->EndingAddr;
+ mMemArrMapInfoType19.MemoryArrayHandle = SmbiosT19->MemoryArrayHandle;
+ mMemArrMapInfoType19.PartitionWidth = SmbiosT19->PartitionWidth;
+ mMemArrMapInfoType19.ExtendedStartingAddress = SmbiosT19->ExtStartingAddr;
+ mMemArrMapInfoType19.ExtendedEndingAddress = SmbiosT19->ExtEndingAddr;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings);
+}
+
+
+/***********************************************************************
+ SMBIOS data update TYPE32 Boot Information
+************************************************************************/
+STATIC
+VOID
+BootInfoUpdateSmbiosType32 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBootInfoType32, mBootInfoType32Strings);
+}
+
+/***********************************************************************
+ Driver Entry
+************************************************************************/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_ERROR, "PlatformSmbiosDxe Loaded\n"));
+
+ //
+ // Locate Smbios protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&mSmbiosProtocol
+ );
+
+ if (EFI_ERROR (Status)) {
+ mSmbiosProtocol = NULL;
+ DEBUG ((EFI_D_ERROR, "Failed to Locate SMBIOS Protocol"));
+ return Status;
+ }
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+ Status = gBS->LocateProtocol (
+ &gAmdIscpDxeProtocolGuid,
+ NULL,
+ (VOID **)&mIscpDxeProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ mIscpDxeProtocol = NULL;
+ DEBUG ((EFI_D_ERROR, "Failed to Locate ISCP DXE Protocol"));
+ return Status;
+ }
+
+ Status = mIscpDxeProtocol-> AmdExecuteSmbiosInfoDxe (
+ mIscpDxeProtocol,
+ &mSmbiosInfo
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to get SMBIOS data via ISCP"));
+ return Status;
+ }
+#endif
+
+ BIOSInfoUpdateSmbiosType0();
+
+ SysInfoUpdateSmbiosType1();
+
+ BoardInfoUpdateSmbiosType2();
+
+ EnclosureInfoUpdateSmbiosType3();
+
+ ProcessorInfoUpdateSmbiosType4();
+
+ CacheInfoUpdateSmbiosType7();
+
+ SysSlotInfoUpdateSmbiosType9();
+
+ PhyMemArrayInfoUpdateSmbiosType16();
+
+ MemDevInfoUpdatedstType17();
+
+ MemArrMapInfoUpdateSmbiosType19();
+
+ BootInfoUpdateSmbiosType32();
+
+ return Status;
+}
diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf new file mode 100644 index 0000000000..0027d79031 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -0,0 +1,60 @@ +#/** @file
+# SMBIOS Table for ARM platform
+#
+# Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSmbiosDxe
+ FILE_GUID = 3847D23F-1D95-4772-B60C-4BBFBC4D532F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformSmbiosDriverEntryPoint
+
+[Sources]
+ PlatformSmbiosDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ BaseLib
+ UefiLib
+ UefiDriverEntryPoint
+ DebugLib
+
+
+[Protocols]
+ gEfiSmbiosProtocolGuid ## CONSUMER
+ gAmdIscpDxeProtocolGuid ## CONSUMER
+
+[Guids]
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Depex]
+ gEfiSmbiosProtocolGuid AND
+ gAmdIscpDxeProtocolGuid
+
diff --git a/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c b/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c new file mode 100644 index 0000000000..be6cf9eda5 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c @@ -0,0 +1,189 @@ +/** @file
+
+ This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+
+ Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+
+#include <Protocol/Rng.h>
+
+#define CCP_TRNG_OFFSET 0xc
+#define CCP_TNRG_RETRIES 5
+
+STATIC EFI_PHYSICAL_ADDRESS mCcpRngOutputReg;
+
+STATIC EFI_HANDLE mHandle;
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of
+ RNGAlgorithmList.
+ On output with a return code of
+ EFI_SUCCESS, the size in bytes of the
+ data returned in RNGAlgorithmList. On
+ output with a return code of
+ EFI_BUFFER_TOO_SMALL, the size of
+ RNGAlgorithmList required to obtain the
+ list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled
+ by the driver with one EFI_RNG_ALGORITHM
+ element for each supported RNG algorithm.
+ The list must not change across multiple
+ calls to the same driver. The first
+ algorithm in the list is the default
+ algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned
+ successfully.
+ @retval EFI_UNSUPPORTED The services is not supported by this
+ driver.
+ @retval EFI_DEVICE_ERROR The list of algorithms could not be
+ retrieved due to a hardware or firmware
+ error.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are
+ incorrect.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small
+ to hold the result.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetInfo (
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ if (This == NULL || RNGAlgorithmListSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ if (RNGAlgorithmList == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG
+ algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that
+ identifies the RNG algorithm to use. May
+ be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer
+ pointed to by RNGValue. The driver shall
+ return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled
+ by the driver with the resulting RNG
+ value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm
+ is not supported by this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due
+ to a hardware or firmware error.
+ @retval EFI_NOT_READY There is not enough random data available
+ to satisfy the length requested by
+ RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is
+ zero.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ UINT32 Val;
+ UINT32 Retries;
+ UINT32 Loop;
+
+ if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // We only support the raw algorithm, so reject requests for anything else
+ //
+ if (RNGAlgorithm != NULL &&
+ !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ do {
+ Retries = CCP_TNRG_RETRIES;
+ do {
+ Val = MmioRead32 (mCcpRngOutputReg);
+ } while (!Val && Retries-- > 0);
+
+ if (!Val) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ for (Loop = 0; Loop < 4 && RNGValueLength > 0; Loop++, RNGValueLength--) {
+ *RNGValue++ = (UINT8)Val;
+ Val >>= 8;
+ }
+ } while (RNGValueLength > 0);
+
+ return EFI_SUCCESS;
+}
+
+STATIC EFI_RNG_PROTOCOL mStyxRngProtocol = {
+ StyxRngGetInfo,
+ StyxRngGetRNG
+};
+
+//
+// Entry point of this driver.
+//
+EFI_STATUS
+EFIAPI
+StyxRngEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ mCcpRngOutputReg = PcdGet64 (PcdCCPBase) + CCP_TRNG_OFFSET;
+
+ return SystemTable->BootServices->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiRngProtocolGuid, &mStyxRngProtocol,
+ NULL
+ );
+}
diff --git a/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf b/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf new file mode 100644 index 0000000000..e63656037e --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf @@ -0,0 +1,47 @@ +## @file
+# This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+#
+# Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StyxRngDxe
+ FILE_GUID = 58E26F0D-CBAC-4BBA-B70F-18221415665A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = StyxRngEntryPoint
+
+[Sources]
+ StyxRngDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ IoLib
+ PcdLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gAmdModulePkgTokenSpaceGuid.PcdCCPBase
+
+[Protocols]
+ gEfiRngProtocolGuid ## PRODUCES
+
+[Guids]
+ gEfiRngAlgorithmRaw
+
+[Depex]
+ TRUE
diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c new file mode 100644 index 0000000000..1958d918d9 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c @@ -0,0 +1,201 @@ +/** @file
+ Initialize SATA Phy, Serdes, and Controller.
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "SataRegisters.h"
+
+#include <Library/AmdSataInitLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+STATIC
+VOID
+ResetSataController (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ // Make a minimal global reset for HBA regiser
+ MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
+
+ // Clear all interrupts
+ MmioWrite32 (AhciBaseAddr + EFI_AHCI_PORT_IS, EFI_AHCI_PORT_IS_CLEAR);
+
+ // Turn on interrupts and ensure that the HBA is working in AHCI mode
+ MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET,
+ EFI_AHCI_GHC_IE | EFI_AHCI_GHC_ENABLE);
+}
+
+STATIC
+VOID
+SetSataCapabilities (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ UINT32 Capability;
+
+ Capability = 0;
+ if (FixedPcdGetBool (PcdSataSssSupport)) // Staggered Spin-Up Support bit
+ Capability |= EFI_AHCI_CAP_SSS;
+ if (FixedPcdGetBool (PcdSataSmpsSupport)) // Mechanical Presence Support bit
+ Capability |= EFI_AHCI_CAP_SMPS;
+
+ MmioOr32 (AhciBaseAddr + EFI_AHCI_CAPABILITY_OFFSET, Capability);
+}
+
+STATIC
+VOID
+InitializeSataPorts (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr,
+ UINTN PortCount
+ )
+{
+ INTN PortNum;
+ BOOLEAN IsCpd;
+ BOOLEAN IsMpsp;
+ UINT32 PortRegAddr;
+ UINT32 RegVal;
+
+ // Set Ports Implemented (PI)
+ MmioWrite32 (AhciBaseAddr + EFI_AHCI_PI_OFFSET, (1 << PortCount) - 1);
+
+ IsCpd = FixedPcdGetBool (PcdSataPortCpd);
+ IsMpsp = FixedPcdGetBool (PcdSataPortMpsp);
+ if (!IsCpd && !IsMpsp) {
+ return;
+ }
+
+ for (PortNum = 0; PortNum < PortCount; PortNum++) {
+ PortRegAddr = EFI_AHCI_PORT_OFFSET (PortNum) + EFI_AHCI_PORT_CMD;
+ RegVal = MmioRead32(AhciBaseAddr + PortRegAddr);
+ if (IsCpd)
+ RegVal |= EFI_AHCI_PORT_CMD_CPD;
+ else
+ RegVal &= ~EFI_AHCI_PORT_CMD_CPD;
+ if (IsMpsp)
+ RegVal |= EFI_AHCI_PORT_CMD_MPSP;
+ else
+ RegVal &= ~EFI_AHCI_PORT_CMD_MPSP;
+ RegVal |= EFI_AHCI_PORT_CMD_HPCP;
+ MmioWrite32(AhciBaseAddr + PortRegAddr, RegVal);
+ }
+}
+
+STATIC
+EFI_STATUS
+InitializeSataController (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr,
+ UINTN SataPortCount,
+ UINTN StartPort
+ )
+{
+ UINT8 SataChPerSerdes;
+ UINT32 PortNum;
+ UINT32 EvenPort;
+ UINT32 OddPort;
+
+ SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes);
+
+ for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) {
+ EvenPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> (PortNum * 2)) & 3;
+ OddPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
+ SataPhyInit ((StartPort + PortNum) / SataChPerSerdes, EvenPort, OddPort);
+ }
+
+ //
+ // Reset SATA controller
+ //
+ ResetSataController (AhciBaseAddr);
+
+ //
+ // Set SATA capabilities
+ //
+ SetSataCapabilities (AhciBaseAddr);
+
+ //
+ // Set and intialize the Sata ports
+ //
+ InitializeSataPorts (AhciBaseAddr, SataPortCount);
+
+ return RegisterNonDiscoverableMmioDevice (
+ NonDiscoverableDeviceTypeAhci,
+ NonDiscoverableDeviceDmaTypeCoherent,
+ NULL,
+ NULL,
+ 1,
+ AhciBaseAddr, SIZE_4KB);
+}
+
+#define STYX_SOC_VERSION_MASK 0xFFF
+#define STYX_SOC_VERSION_A0 0x000
+#define STYX_SOC_VERSION_B0 0x010
+#define STYX_SOC_VERSION_B1 0x011
+
+EFI_STATUS
+EFIAPI
+StyxSataPlatformDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT32 PortNum;
+ EFI_STATUS Status;
+
+ //
+ // Perform SATA workarounds
+ //
+ for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
+ SetCwMinSata0 (PortNum);
+ }
+
+ Status = InitializeSataController (FixedPcdGet32(PcdSata0CtrlAxiSlvPort),
+ FixedPcdGet8(PcdSata0PortCount), 0);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to initialize primary SATA controller!\n",
+ __FUNCTION__));
+ return Status;
+ }
+
+ for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
+ SetPrdSingleSata0 (PortNum);
+ }
+
+ //
+ // Ignore the second SATA controller on pre-B1 silicon
+ //
+ if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
+ return EFI_SUCCESS;
+ }
+
+ if (FixedPcdGet8(PcdSata1PortCount) > 0) {
+ for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
+ SetCwMinSata1 (PortNum);
+ }
+
+ Status = InitializeSataController (FixedPcdGet32(PcdSata1CtrlAxiSlvPort),
+ FixedPcdGet8(PcdSata1PortCount),
+ FixedPcdGet8(PcdSata0PortCount));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to initialize secondary SATA controller!\n",
+ __FUNCTION__));
+ } else {
+ for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
+ SetPrdSingleSata1 (PortNum);
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h new file mode 100644 index 0000000000..ff78f4ac3c --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h @@ -0,0 +1,180 @@ +/** @file
+ Header file for AHCI mode of ATA host controller.
+
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SATA_REGISTERS_H__
+#define __SATA_REGISTERS_H__
+
+#define EFI_AHCI_BAR_INDEX 0x05
+
+#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
+#define EFI_AHCI_CAP_SSS BIT27
+#define EFI_AHCI_CAP_SMPS BIT28
+#define EFI_AHCI_CAP_S64A BIT31
+#define EFI_AHCI_GHC_OFFSET 0x0004
+#define EFI_AHCI_GHC_RESET BIT0
+#define EFI_AHCI_GHC_IE BIT1
+#define EFI_AHCI_GHC_ENABLE BIT31
+#define EFI_AHCI_IS_OFFSET 0x0008
+#define EFI_AHCI_PI_OFFSET 0x000C
+
+#define EFI_AHCI_MAX_PORTS 32
+
+//
+// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
+//
+#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
+//
+// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
+//
+#define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
+//
+// Refer SATA1.0a spec, the bus reset time should be less than 1s.
+//
+#define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
+
+#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
+#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
+#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
+#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
+
+//
+// Each PRDT entry can point to a memory block up to 4M byte
+//
+#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
+
+#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
+#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
+#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
+#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
+#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
+#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
+#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
+#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
+#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST_LENGTH 12
+#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
+#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
+#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
+#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
+
+#define EFI_AHCI_D2H_FIS_OFFSET 0x40
+#define EFI_AHCI_DMA_FIS_OFFSET 0x00
+#define EFI_AHCI_PIO_FIS_OFFSET 0x20
+#define EFI_AHCI_SDB_FIS_OFFSET 0x58
+#define EFI_AHCI_FIS_TYPE_MASK 0xFF
+#define EFI_AHCI_U_FIS_OFFSET 0x60
+
+//
+// Port register
+//
+#define EFI_AHCI_PORT_START 0x0100
+#define EFI_AHCI_PORT_REG_WIDTH 0x0080
+#define EFI_AHCI_PORT_CLB 0x0000
+#define EFI_AHCI_PORT_CLBU 0x0004
+#define EFI_AHCI_PORT_FB 0x0008
+#define EFI_AHCI_PORT_FBU 0x000C
+#define EFI_AHCI_PORT_IS 0x0010
+#define EFI_AHCI_PORT_IS_DHRS BIT0
+#define EFI_AHCI_PORT_IS_PSS BIT1
+#define EFI_AHCI_PORT_IS_SSS BIT2
+#define EFI_AHCI_PORT_IS_SDBS BIT3
+#define EFI_AHCI_PORT_IS_UFS BIT4
+#define EFI_AHCI_PORT_IS_DPS BIT5
+#define EFI_AHCI_PORT_IS_PCS BIT6
+#define EFI_AHCI_PORT_IS_DIS BIT7
+#define EFI_AHCI_PORT_IS_PRCS BIT22
+#define EFI_AHCI_PORT_IS_IPMS BIT23
+#define EFI_AHCI_PORT_IS_OFS BIT24
+#define EFI_AHCI_PORT_IS_INFS BIT26
+#define EFI_AHCI_PORT_IS_IFS BIT27
+#define EFI_AHCI_PORT_IS_HBDS BIT28
+#define EFI_AHCI_PORT_IS_HBFS BIT29
+#define EFI_AHCI_PORT_IS_TFES BIT30
+#define EFI_AHCI_PORT_IS_CPDS BIT31
+#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
+
+#define EFI_AHCI_PORT_OFFSET(PortNum) \
+ (EFI_AHCI_PORT_START + ((PortNum) * EFI_AHCI_PORT_REG_WIDTH))
+
+#define EFI_AHCI_PORT_IE 0x0014
+#define EFI_AHCI_PORT_CMD 0x0018
+#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
+#define EFI_AHCI_PORT_CMD_ST BIT0
+#define EFI_AHCI_PORT_CMD_SUD BIT1
+#define EFI_AHCI_PORT_CMD_POD BIT2
+#define EFI_AHCI_PORT_CMD_CLO BIT3
+#define EFI_AHCI_PORT_CMD_CR BIT15
+#define EFI_AHCI_PORT_CMD_FRE BIT4
+#define EFI_AHCI_PORT_CMD_FR BIT14
+#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
+#define EFI_AHCI_PORT_CMD_PMA BIT17
+#define EFI_AHCI_PORT_CMD_HPCP BIT18
+#define EFI_AHCI_PORT_CMD_MPSP BIT19
+#define EFI_AHCI_PORT_CMD_CPD BIT20
+#define EFI_AHCI_PORT_CMD_ESP BIT21
+#define EFI_AHCI_PORT_CMD_ATAPI BIT24
+#define EFI_AHCI_PORT_CMD_DLAE BIT25
+#define EFI_AHCI_PORT_CMD_ALPE BIT26
+#define EFI_AHCI_PORT_CMD_ASP BIT27
+#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
+#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
+#define EFI_AHCI_PORT_TFD 0x0020
+#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
+#define EFI_AHCI_PORT_TFD_BSY BIT7
+#define EFI_AHCI_PORT_TFD_DRQ BIT3
+#define EFI_AHCI_PORT_TFD_ERR BIT0
+#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
+#define EFI_AHCI_PORT_SIG 0x0024
+#define EFI_AHCI_PORT_SSTS 0x0028
+#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SSTS_DET 0x0001
+#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
+#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL 0x002C
+#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
+#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
+#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
+#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
+#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
+#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
+#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
+#define EFI_AHCI_PORT_SERR 0x0030
+#define EFI_AHCI_PORT_SERR_RDIE BIT0
+#define EFI_AHCI_PORT_SERR_RCE BIT1
+#define EFI_AHCI_PORT_SERR_TDIE BIT8
+#define EFI_AHCI_PORT_SERR_PCDIE BIT9
+#define EFI_AHCI_PORT_SERR_PE BIT10
+#define EFI_AHCI_PORT_SERR_IE BIT11
+#define EFI_AHCI_PORT_SERR_PRC BIT16
+#define EFI_AHCI_PORT_SERR_PIE BIT17
+#define EFI_AHCI_PORT_SERR_CW BIT18
+#define EFI_AHCI_PORT_SERR_BDE BIT19
+#define EFI_AHCI_PORT_SERR_DE BIT20
+#define EFI_AHCI_PORT_SERR_CRCE BIT21
+#define EFI_AHCI_PORT_SERR_HE BIT22
+#define EFI_AHCI_PORT_SERR_LSE BIT23
+#define EFI_AHCI_PORT_SERR_TSTE BIT24
+#define EFI_AHCI_PORT_SERR_UFT BIT25
+#define EFI_AHCI_PORT_SERR_EX BIT26
+#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_SACT 0x0034
+#define EFI_AHCI_PORT_CI 0x0038
+#define EFI_AHCI_PORT_SNTF 0x003C
+
+#endif
diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf new file mode 100644 index 0000000000..8a4deb9185 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf @@ -0,0 +1,63 @@ +## @file
+#
+# Component description file for the Styx SATA platform driver.
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = StyxSataPlatformDxe
+ FILE_GUID = 4703fac4-9de9-4010-87d1-11402894296a
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = StyxSataPlatformDxeEntryPoint
+
+[Sources]
+ InitController.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ AmdSataInit
+ BaseLib
+ DebugLib
+ IoLib
+ NonDiscoverableDeviceRegistrationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[FixedPcd]
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes
+
+ gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort
+ gAmdStyxTokenSpaceGuid.PcdSata0PortCount
+ gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode
+ gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport
+ gAmdStyxTokenSpaceGuid.PcdSataSssSupport
+ gAmdStyxTokenSpaceGuid.PcdSataPortCpd
+ gAmdStyxTokenSpaceGuid.PcdSataPortMpsp
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+[Depex]
+ TRUE
diff --git a/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c b/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c new file mode 100644 index 0000000000..f544af3eeb --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c @@ -0,0 +1,500 @@ +/** @file
+
+ FV block I/O protocol driver for Styx SPI flash exposed via ISCP
+
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#define SPI_BASE (FixedPcdGet64 (PcdFdBaseAddress))
+#define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize))
+
+STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+STATIC EFI_HANDLE mStyxSpiFvHandle;
+
+STATIC EFI_EVENT mVirtualAddressChangeEvent;
+
+STATIC UINT64 mNvStorageBase;
+STATIC UINT64 mNvStorageLbaOffset;
+
+STATIC CONST UINT64 mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+
+/**
+ Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE.
+
+ This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
+ It convers pointer to new virtual address.
+
+ @param Event Event whose notification function is being invoked.
+ @param Context Pointer to the notification function's context.
+
+**/
+STATIC
+VOID
+EFIAPI
+VariableClassAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID **)&mIscpDxeProtocol);
+ EfiConvertPointer (0x0, (VOID **)&mNvStorageBase);
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
+ attributes and current settings are
+ returned. Type EFI_FVB_ATTRIBUTES_2 is defined
+ in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were
+ returned.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ *Attributes = EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP | // Writes may be enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY; // After erasure all bits take this value (i.e. '1')
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume
+ attributes and returns the new settings of the firmware volume.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to
+ EFI_FVB_ATTRIBUTES_2 that contains the
+ desired firmware volume settings. On
+ successful return, it contains the new
+ settings of the firmware volume. Type
+ EFI_FVB_ATTRIBUTES_2 is defined in
+ EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in
+ conflict with the capabilities
+ as declared in the firmware
+ volume header.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeSetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ return EFI_SUCCESS; // ignore for now
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_UNSUPPORTED The firmware volume is not memory mapped.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ *Address = (EFI_PHYSICAL_ADDRESS)mNvStorageBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ *BlockSize = BLOCK_SIZE;
+ *NumberOfBlocks = mNvStorageSize / BLOCK_SIZE - (UINTN)Lba;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index
+ from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will
+ be used to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully,
+ and contents are in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA
+ boundary. On output, NumBytes
+ contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not
+ functioning correctly and could
+ not be read.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ VOID *Base;
+
+ if (Offset + *NumBytes > BLOCK_SIZE) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+ //
+ // Copy the data from the in-memory image
+ //
+ CopyMem (Buffer, Base, *NumBytes);
+
+ DEBUG_CODE_BEGIN ();
+ EFI_STATUS Status;
+
+ if (!EfiAtRuntime ()) {
+ Lba += mNvStorageLbaOffset;
+ Status = mIscpDxeProtocol->AmdExecuteLoadFvBlockDxe (mIscpDxeProtocol,
+ Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+ ASSERT_EFI_ERROR (Status);
+
+ ASSERT (CompareMem (Base, Buffer, *NumBytes) == 0);
+ }
+ DEBUG_CODE_END ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an
+ LBA boundary. On output, NumBytes
+ contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning
+ and could not be written.
+
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ VOID *Base;
+
+ if (Offset + *NumBytes > BLOCK_SIZE) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+ Lba += mNvStorageLbaOffset;
+ Status = mIscpDxeProtocol->AmdExecuteUpdateFvBlockDxe (mIscpDxeProtocol,
+ Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Copy the data we just wrote to the in-memory copy of the
+ // firmware volume
+ //
+ CopyMem (Base, Buffer, *NumBytes);
+ }
+ return Status;
+}
+
+/**
+ Erases and initializes a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to
+ erase.
+
+ The list is terminated with an
+ EFI_LBA_LIST_TERMINATOR. For example, the
+ following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased: EraseBlocks
+ (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully
+ completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+ @retval EFI_DEVICE_ERROR The block device is not functioning
+ correctly and could not be written.
+ The firmware device may have been
+ partially erased.
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed
+ in the variable argument list do
+ not exist in the firmware volume.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeErase (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ VA_LIST Args;
+ EFI_LBA Start;
+ UINTN Length;
+ EFI_STATUS Status;
+
+ VA_START (Args, This);
+
+ for (Start = VA_ARG (Args, EFI_LBA);
+ Start != EFI_LBA_LIST_TERMINATOR;
+ Start = VA_ARG (Args, EFI_LBA)) {
+ Length = VA_ARG (Args, UINTN);
+ Status = mIscpDxeProtocol->AmdExecuteEraseFvBlockDxe (mIscpDxeProtocol,
+ (Start + mNvStorageLbaOffset) * BLOCK_SIZE,
+ Length * BLOCK_SIZE);
+ if (!EFI_ERROR (Status)) {
+ SetMem64 ((VOID *)mNvStorageBase + Start * BLOCK_SIZE,
+ Length * BLOCK_SIZE, ~0UL);
+ }
+ }
+
+ VA_END (Args);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mStyxSpiFvProtocol = {
+ StyxSpiFvDxeGetAttributes,
+ StyxSpiFvDxeSetAttributes,
+ StyxSpiFvDxeGetPhysicalAddress,
+ StyxSpiFvDxeGetBlockSize,
+ StyxSpiFvDxeRead,
+ StyxSpiFvDxeWrite,
+ StyxSpiFvDxeErase
+};
+
+EFI_STATUS
+EFIAPI
+StyxSpiFvDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mNvStorageBase = PcdGet64 (PcdFlashNvStorageVariableBase64);
+ mNvStorageLbaOffset = (FixedPcdGet64 (PcdFlashNvStorageOriginalBase) -
+ SPI_BASE) / BLOCK_SIZE;
+
+ DEBUG ((EFI_D_INFO,
+ "%a: Using NV store FV in-memory copy at 0x%lx, LBA offset == 0x%lx\n",
+ __FUNCTION__, mNvStorageBase, mNvStorageLbaOffset));
+
+ Status = gBS->LocateProtocol (&gAmdIscpDxeProtocolGuid, NULL,
+ (VOID **)&mIscpDxeProtocol);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
+ VariableClassAddressChangeEvent, NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mVirtualAddressChangeEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return gBS->InstallMultipleProtocolInterfaces (&mStyxSpiFvHandle,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &mStyxSpiFvProtocol,
+ NULL);
+}
diff --git a/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf b/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf new file mode 100644 index 0000000000..76042ab301 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf @@ -0,0 +1,63 @@ +#/** @file
+#
+# Component description file for StyxSpiFvDxe module
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StyxSpiFvDxe
+ FILE_GUID = F549FC67-C4A6-4E92-B9BA-297E1F82A1A8
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = StyxSpiFvDxeInitialize
+
+[Sources]
+ StyxSpiFvDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ UefiLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeLib
+ DxeServicesTableLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid ## CONSUMES
+ gEfiFirmwareVolumeBlockProtocolGuid ## PRODUCES
+
+[Depex]
+ gAmdIscpDxeProtocolGuid
diff --git a/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c b/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c new file mode 100644 index 0000000000..d8b70f56fa --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c @@ -0,0 +1,77 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxHelperLib.h>
+
+#include <PiDxe.h>
+#include <Library/HobLib.h>
+
+extern EFI_SYSTEM_TABLE *gST;
+
+#pragma pack(push, 1)
+typedef struct {
+ UINT32 MpId;
+ UINT32 PmuSpi;
+} PMU_INFO;
+
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ UINT32 MpId,
+ UINT32 *PmuSpi
+ )
+{
+ UINT32 i;
+
+ for (i = 0; i < MAX_CPUS; ++i) {
+ if (mPmuInfo[ i ].MpId == MpId) {
+ *PmuSpi = mPmuInfo[ i ].PmuSpi;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ )
+{
+ EFI_HOB_GUID_TYPE *Hob;
+
+ ASSERT (NumEntries != NULL);
+
+ Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+ if (Hob == NULL) {
+ return NULL;
+ }
+
+ *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+
+ return GET_GUID_HOB_DATA (Hob);
+}
diff --git a/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf b/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf new file mode 100644 index 0000000000..17681d9ed5 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf @@ -0,0 +1,37 @@ +#/** @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxHelperLib
+ FILE_GUID = a2a9afbb-6776-4585-8a81-f82f98b4ea53
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdStyxHelperLib
+
+[Sources.common]
+ AmdStyxHelperLib.c
+
+[LibraryClasses]
+ HobLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid
diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S b/Silicon/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S new file mode 100644 index 0000000000..b7ec02f0e6 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S @@ -0,0 +1,78 @@ +#/**
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S
+#
+#**/
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+PrimaryCoreMpid: .word 0x0
+PrimaryCoreBoot: .word 0x0
+
+//VOID
+//ArmPlatformPeiBootAction (
+// VOID
+// );
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ldr w0, PrimaryCoreBoot
+ cbnz w0, 1f
+
+ // Save the primary CPU MPID
+ mrs x0, mpidr_el1
+ adr x2, PrimaryCoreMpid
+ mov w1, #1
+ stp w0, w1, [x2]
+1:
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ ldr w0, PrimaryCoreMpid
+ ret
+
+# IN None
+# OUT x0 = number of cores present in the system
+ASM_FUNC(ArmGetCpuCountPerCluster)
+ MOV32 (w0, FixedPcdGet32 (PcdCoreCount))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ ldr w1, PrimaryCoreMpid
+
+ cmp w0, w1
+ cset x0, eq
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #7
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf new file mode 100644 index 0000000000..76ea730990 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf @@ -0,0 +1,76 @@ +#/* @file
+#
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxLib
+ FILE_GUID = 256ee872-5a3e-4b6e-afd6-63c49ba3d7ba
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ DebugLib
+
+[Sources.common]
+ Styx.c
+ StyxMem.c
+
+[Sources.AARCH64]
+ AArch64/Helper.S | GCC
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## CONSUMER
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
+
+[Depex]
+ gAmdStyxPlatInitPpiGuid
diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf new file mode 100644 index 0000000000..b067f72899 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf @@ -0,0 +1,67 @@ +#/* @file
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxLibSec
+ FILE_GUID = 2228e985-60ae-406e-bdf0-410c6750c7d2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ DebugLib
+
+[Sources.common]
+ Styx.c
+
+[Sources.AARCH64]
+ AArch64/Helper.S | GCC
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## CONSUMER
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/Styx.c b/Silicon/AMD/Styx/Library/AmdStyxLib/Styx.c new file mode 100644 index 0000000000..f17a960d60 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/Styx.c @@ -0,0 +1,164 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+
+
+extern EFI_GUID gAmdStyxMpCoreInfoGuid;
+
+
+UINTN
+ArmGetCpuCountPerCluster (
+ VOID
+ );
+
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ // XXX Place holder XXX ...
+
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+
+//
+// Return list of cores in the system
+//
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *ArmCoreCount,
+ OUT ARM_CORE_INFO **ArmCoreInfoTable
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+
+ if (ArmIsMpCore()) {
+ // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
+ for (Hob.Raw = GetHobList (); !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
+ // Check for Correct HOB type
+ if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
+ // Check for correct GUID type
+ if (CompareGuid(&(Hob.Guid->Name), &gAmdStyxMpCoreInfoGuid)) {
+ *ArmCoreInfoTable = (ARM_CORE_INFO *) GET_GUID_HOB_DATA(Hob);
+ *ArmCoreCount = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
+ return EFI_SUCCESS;
+ }
+ }
+ }
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ if (ArmIsMpCore()) {
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+ } else {
+ *PpiListSize = 0;
+ *PpiList = NULL;
+ }
+}
+
+
diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c new file mode 100644 index 0000000000..3b82132d08 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c @@ -0,0 +1,118 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+
+#if !defined(MDEPKG_NDEBUG)
+
+static const char *tblAttrDesc[] =
+{
+ "UNCACHED_UNBUFFERED ",
+ "NONSECURE_UNCACHED_UNBUFFERED",
+ "WRITE_BACK ",
+ "NONSECURE_WRITE_BACK ",
+ "WRITE_THROUGH ",
+ "NONSECURE_WRITE_THROUGH ",
+ "DEVICE ",
+ "NONSECURE_DEVICE "
+};
+#endif
+
+#define LOG_MEM(desc) DEBUG ((EFI_D_ERROR, desc, VirtualMemoryTable[Index].PhysicalBase, \
+ ( VirtualMemoryTable[Index].PhysicalBase+VirtualMemoryTable[Index].Length - 1), \
+ VirtualMemoryTable[Index].Length, tblAttrDesc[VirtualMemoryTable[Index].Attributes]));
+
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT(VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+
+ DEBUG ((EFI_D_ERROR, " Memory Map\n------------------------------------------------------------------------\n"));
+ DEBUG ((EFI_D_ERROR, "Description : START - END [ SIZE ] { ATTR }\n"));
+
+ // 0xE000_0000 - 0xEFFF_FFFF: Mapped I/O space
+ VirtualMemoryTable[Index].PhysicalBase = 0xE0000000UL;
+ VirtualMemoryTable[Index].VirtualBase = 0xE0000000UL;
+ VirtualMemoryTable[Index].Length = SIZE_256MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("I/O Space [Platform MMIO] : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // 0xF000_0000 - 0xFFFF_FFFF: PCI config space
+ VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000UL;
+ VirtualMemoryTable[Index].VirtualBase = 0xF0000000UL;
+ VirtualMemoryTable[Index].Length = SIZE_256MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("I/O Space [PCI config space] : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ LOG_MEM ("DRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c new file mode 100644 index 0000000000..8d8c76a0f7 --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -0,0 +1,196 @@ +/** @file
+ PCI Host Bridge Library instance for AMD Seattle SOC
+
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08), // PCI Express
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ PCI_ROOT_BRIDGE *RootBridge;
+
+ *Count = 1;
+ RootBridge = AllocateZeroPool (*Count * sizeof *RootBridge);
+
+ RootBridge->Segment = 0;
+
+ RootBridge->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
+ RootBridge->Attributes = RootBridge->Supports;
+
+ RootBridge->DmaAbove4G = TRUE;
+
+ RootBridge->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE ;
+
+ RootBridge->Bus.Base = PcdGet32 (PcdPciBusMin);
+ RootBridge->Bus.Limit = PcdGet32 (PcdPciBusMax);
+ RootBridge->Io.Base = PcdGet64 (PcdPciIoBase);
+ RootBridge->Io.Limit = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1;
+ RootBridge->Mem.Base = PcdGet32 (PcdPciMmio32Base);
+ RootBridge->Mem.Limit = PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1;
+ RootBridge->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
+ RootBridge->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1;
+
+ //
+ // No separate ranges for prefetchable and non-prefetchable BARs
+ //
+ RootBridge->PMem.Base = MAX_UINT64;
+ RootBridge->PMem.Limit = 0;
+ RootBridge->PMemAbove4G.Base = MAX_UINT64;
+ RootBridge->PMemAbove4G.Limit = 0;
+
+ ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);
+ ASSERT (FixedPcdGet64 (PcdPciMmio64Translation) == 0);
+
+ RootBridge->NoExtendedConfigSpace = FALSE;
+
+ RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
+
+ return RootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+ FreePool (Bridges);
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf b/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf new file mode 100644 index 0000000000..3fdaf14d8c --- /dev/null +++ b/Silicon/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf @@ -0,0 +1,55 @@ +## @file
+# PCI Host Bridge Library instance for AMD Seattle SOC
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxPciHostBridgeLib
+ FILE_GUID = 05E7AB83-EF8D-482D-80F8-905B73377A15
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ AmdStyxPciHostBridgeLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+ gArmTokenSpaceGuid.PcdPciMmio64Translation
diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c new file mode 100644 index 0000000000..70821d1b12 --- /dev/null +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -0,0 +1,185 @@ +/** @file
+
+ Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016 AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmMmuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+VOID
+InitMmu (
+ VOID
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ // Note: Because we called PeiServicesInstallPeiMemory() before to call
+ // InitMmu() the MMU Page Table resides in DRAM (even at the top
+ // of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+STATIC
+VOID
+MoveNvStoreImage (
+ VOID
+ )
+{
+ VOID *OldBase, *NewBase;
+ UINTN Size;
+
+ //
+ // Move the in-memory image of the NV store firmware volume to a dynamically
+ // allocated buffer. This gets rid of the annoying static memory reservation
+ // at the base of memory where all other UEFI allocations are near the top.
+ //
+ OldBase = (VOID *)FixedPcdGet64 (PcdFlashNvStorageOriginalBase);
+
+ Size = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+ NewBase = AllocateAlignedRuntimePages (EFI_SIZE_TO_PAGES (Size), SIZE_64KB);
+ ASSERT (NewBase != NULL);
+
+ CopyMem (NewBase, OldBase, Size);
+
+ DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n",
+ __FUNCTION__, OldBase, NewBase));
+
+ PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase);
+
+ PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase +
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize));
+
+ PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase +
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize));
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ UINT64 Base, Size;
+
+ // Ensure PcdSystemMemorySize has been set
+ ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
+
+ //
+ // Now, the permanent memory has been installed, we can call AllocatePages()
+ //
+
+ Base = PcdGet64 (PcdSystemMemoryBase);
+ Size = PcdGet64 (PcdSystemMemorySize);
+ if (FixedPcdGetBool (PcdTrustedFWSupport)) {
+
+ //
+ // For now, we assume that the trusted firmware region is at the base of
+ // system memory, since that is much easier to deal with.
+ //
+ ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase));
+
+ Base += PcdGet64 (PcdTrustedFWMemorySize);
+ Size -= PcdGet64 (PcdTrustedFWMemorySize);
+
+ // Reserved Trusted Firmware region
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED ),
+ PcdGet64 (PcdTrustedFWMemoryBase),
+ PcdGet64 (PcdTrustedFWMemorySize)
+ );
+
+ BuildMemoryAllocationHob (
+ PcdGet64 (PcdTrustedFWMemoryBase),
+ PcdGet64 (PcdTrustedFWMemorySize),
+ EfiReservedMemoryType
+ );
+ }
+
+ // Declare system memory
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED ),
+ Base,
+ Size
+ );
+
+ // Build Memory Allocation Hob
+ InitMmu ();
+
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ BuildMemoryTypeInformationHob ();
+ }
+
+ MoveNvStoreImage ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf new file mode 100644 index 0000000000..724d71645d --- /dev/null +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -0,0 +1,92 @@ +#/** @file
+#
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxMemoryInitPeiLib
+ FILE_GUID = 25466f78-a75a-4aae-be09-a68a347c3228
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+ MemoryInitPeiLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ ArmMmuLib
+ ArmPlatformLib
+ PcdLib
+
+[Ppis]
+ gAmdStyxPlatInitPpiGuid ## CONSUMER
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
+
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Depex]
+ gAmdStyxPlatInitPpiGuid
diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c new file mode 100644 index 0000000000..1b926242b5 --- /dev/null +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c @@ -0,0 +1,277 @@ +/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Iscp.h>
+
+extern EFI_BOOT_SERVICES *gBS;
+
+AMD_ISCP_DXE_PROTOCOL *mRtcIscpDxeProtocol = NULL;
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ ISCP_RTC_INFO RtcInfo;
+ EFI_STATUS Status;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (mRtcIscpDxeProtocol == NULL) {
+ DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Fill in Time and Capabilities via data from you RTC
+ //
+ Status = mRtcIscpDxeProtocol->AmdExecuteGetRtc (
+ mRtcIscpDxeProtocol,
+ &RtcInfo
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "RTC: Failed GetRtc() via ISCP - Status = %r \n", Status));
+ return Status;
+ }
+
+ Time->Year = RtcInfo.Year;
+ Time->Month = RtcInfo.Month;
+ Time->Day = RtcInfo.Day;
+ Time->Hour = RtcInfo.Hour;
+ Time->Minute = RtcInfo.Minute;
+ Time->Second = RtcInfo.Second;
+
+ return Status;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status;
+ ISCP_RTC_INFO RtcInfo;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Use Time, to set the time in your RTC hardware
+ //
+ RtcInfo.Year = Time->Year;
+ RtcInfo.Month = Time->Month;
+ RtcInfo.Day = Time->Day;
+ RtcInfo.Hour = Time->Hour;
+ RtcInfo.Minute = Time->Minute;
+ RtcInfo.Second = Time->Second;
+
+ if (mRtcIscpDxeProtocol == NULL) {
+ DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = mRtcIscpDxeProtocol->AmdExecuteSetRtc (
+ mRtcIscpDxeProtocol,
+ &RtcInfo
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "RTC: Failed SetRtc() via ISCP - Status = %r \n", Status));
+ return Status;
+ }
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Do some initialization if required to turn on the RTC
+ //
+ Status = gBS->LocateProtocol (
+ &gAmdIscpDxeProtocolGuid,
+ NULL,
+ (VOID **)&mRtcIscpDxeProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "RTC: Failed to Locate ISCP DXE Protocol - Status = %r \n", Status));
+ return Status;
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ LibRtcVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mRtcVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transistions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol);
+ }
+}
+
+
+
diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf new file mode 100644 index 0000000000..cd9418c9b7 --- /dev/null +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -0,0 +1,57 @@ +#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxRealTimeClockLib
+ FILE_GUID = fd922639-f4ee-4d2f-955b-804e60df1e68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ UefiRuntimeLib
+ DxeServicesTableLib
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid ## CONSUMER
+
+[Depex]
+ gAmdIscpDxeProtocolGuid
+
+
+
diff --git a/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 0000000000..5a99fd7938 --- /dev/null +++ b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,47 @@ +#/** @file
+# Reset System lib using PSCI hypervisor or secure monitor calls
+#
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxResetSystemLib
+ FILE_GUID = 624f6cc6-c38f-4897-b3b7-8a601701291b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+[Sources.common]
+ ResetSystemLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PcdLib
+ BaseLib
+ ArmSmcLib
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c new file mode 100644 index 0000000000..7e8f918b11 --- /dev/null +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -0,0 +1,543 @@ +/** @file
+*
+* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <libfdt.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/AmdMpCoreInfo.h>
+
+#define PMU_INT_FLAG_SPI 0
+#define PMU_INT_TYPE_HIGH_LEVEL 4
+
+//
+// PMU interrupts per core
+//
+#pragma pack(push, 1)
+typedef struct {
+ UINT32 Flag; // 0 == SPI
+ UINT32 IntId; // GSIV == IntId+32
+ UINT32 Type; // 4 == Level-Sensitive, Active-High
+} PMU_INTERRUPT;
+#pragma pack(pop)
+
+STATIC
+BOOLEAN
+ClusterInRange (
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN ClusterId,
+ IN UINTN LowIndex,
+ IN UINTN HighIndex
+ )
+{
+ do {
+ if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId)
+ return TRUE;
+ } while (++LowIndex <= HighIndex);
+
+ return FALSE;
+}
+
+
+STATIC
+UINTN
+NumberOfCoresInCluster (
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN NumberOfEntries,
+ IN UINTN ClusterId
+ )
+{
+ UINTN Index, Cores;
+
+ Cores = 0;
+ for (Index = 0; Index < NumberOfEntries; ++Index) {
+ if (ClusterId == ArmCoreInfoTable[Index].ClusterId)
+ ++Cores;
+ }
+
+ return Cores;
+}
+
+
+STATIC
+UINTN
+NumberOfClustersInTable (
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN NumberOfEntries
+ )
+{
+ UINTN Index, Cores, Clusters, ClusterId;
+
+ Index = 0;
+ Clusters = 0;
+ Cores = NumberOfEntries;
+ while (Cores) {
+ ++Clusters;
+ ClusterId = ArmCoreInfoTable[Index].ClusterId;
+ Cores -= NumberOfCoresInCluster (ArmCoreInfoTable,
+ NumberOfEntries,
+ ClusterId);
+ if (Cores) {
+ do {
+ ++Index;
+ } while (ClusterInRange (ArmCoreInfoTable,
+ ArmCoreInfoTable[Index].ClusterId,
+ 0, Index-1));
+ }
+ }
+
+ return Clusters;
+}
+
+
+STATIC
+INT32
+fdt_alloc_phandle (
+ IN VOID *Fdt
+ )
+{
+ INT32 Offset;
+ INT32 Phandle;
+
+ Phandle = 0;
+
+ for (Offset = fdt_next_node (Fdt, -1, NULL); Offset >= 0;
+ Offset = fdt_next_node (Fdt, Offset, NULL)) {
+ Phandle = MAX (Phandle, fdt_get_phandle (Fdt, Offset));
+ }
+
+ return Phandle + 1;
+}
+
+STATIC
+VOID
+SetDeviceStatus (
+ IN VOID *Fdt,
+ IN CONST CHAR8 *Device,
+ IN BOOLEAN Enable
+ )
+{
+ INT32 Node;
+ INT32 SubNode;
+ INT32 Rc;
+
+ Node = fdt_subnode_offset (Fdt, 0, "smb");
+ if (Node >= 0) {
+ SubNode = fdt_subnode_offset (Fdt, Node, Device);
+ if (SubNode >= 0) {
+ Rc = fdt_setprop_string (Fdt, SubNode, "status",
+ Enable ? "okay" : "disabled");
+ if (Rc) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: Could not set 'status' property for '%a' node\n",
+ __FUNCTION__, Device));
+ }
+ }
+ }
+}
+
+#if DO_XGBE
+
+#define MAC_ADDRESS_BYTES 6
+
+STATIC
+VOID
+SetMacAddress (
+ IN VOID *Fdt,
+ IN CONST CHAR8 *Device,
+ IN UINT64 MacAddress
+ )
+{
+ INT32 Node;
+ INT32 SubNode;
+ INT32 Rc;
+
+ Node = fdt_subnode_offset (Fdt, 0, "smb");
+ if (Node >= 0) {
+ SubNode = fdt_subnode_offset (Fdt, Node, Device);
+ if (SubNode >= 0) {
+ Rc = fdt_setprop (Fdt, SubNode, "mac-address", (VOID *)&MacAddress,
+ MAC_ADDRESS_BYTES);
+ if (Rc) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: Could not set 'mac-address' property for '%a' node\n",
+ __FUNCTION__, Device));
+ }
+ }
+ }
+}
+
+#endif
+
+STATIC
+VOID
+DisableSmmu (
+ IN VOID *Fdt,
+ IN CONST CHAR8 *IommuPropName,
+ IN CONST CHAR8 *SmmuNodeName,
+ IN CONST CHAR8 *DeviceNodeName
+ )
+{
+ INT32 Node;
+ INT32 Error;
+
+ Node = fdt_path_offset (Fdt, DeviceNodeName);
+ if (Node <= 0) {
+ DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
+ __FUNCTION__, DeviceNodeName, fdt_strerror (Node)));
+ return;
+ }
+
+ Error = fdt_delprop (Fdt, Node, IommuPropName);
+ if (Error != 0) {
+ DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n",
+ __FUNCTION__, IommuPropName, fdt_strerror (Error)));
+ return;
+ }
+
+ Node = fdt_path_offset (Fdt, SmmuNodeName);
+ if (Node <= 0) {
+ DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
+ __FUNCTION__, SmmuNodeName, fdt_strerror (Node)));
+ return;
+ }
+
+ Error = fdt_del_node (Fdt, Node);
+ if (Error != 0) {
+ DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n",
+ __FUNCTION__, SmmuNodeName, fdt_strerror (Error)));
+ }
+}
+
+#define STYX_SOC_VERSION_MASK 0xFFF
+#define STYX_SOC_VERSION_A0 0x000
+#define STYX_SOC_VERSION_B0 0x010
+#define STYX_SOC_VERSION_B1 0x011
+
+STATIC
+VOID
+SetSocIdStatus (
+ IN VOID *Fdt
+ )
+{
+ UINT32 SocId;
+ BOOLEAN IsRevB1;
+ BOOLEAN DisableXgbeSmmus;
+
+ SocId = PcdGet32 (PcdSocCpuId);
+ IsRevB1 = (SocId & STYX_SOC_VERSION_MASK) >= STYX_SOC_VERSION_B1;
+
+ SetDeviceStatus (Fdt, "sata@e0d00000",
+ IsRevB1 && FixedPcdGet8 (PcdSata1PortCount) > 0);
+ SetDeviceStatus (Fdt, "gpio@e0020000", IsRevB1);
+ SetDeviceStatus (Fdt, "gpio@e0030000", IsRevB1);
+ SetDeviceStatus (Fdt, "gwdt@e0bb0000", IsRevB1);
+#if DO_KCS
+ SetDeviceStatus (Fdt, "kcs@e0010000", IsRevB1);
+#else
+ SetDeviceStatus (Fdt, "kcs@e0010000", FALSE);
+#endif
+
+ if (!PcdGetBool (PcdEnableSmmus)) {
+ DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");
+ DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");
+ }
+
+ if (!PcdGetBool (PcdEnableSmmus) || !IsRevB1 || FixedPcdGet8 (PcdSata1PortCount) == 0) {
+ DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");
+ }
+
+#if DO_XGBE
+ DisableXgbeSmmus = !PcdGetBool (PcdEnableSmmus);
+#else
+ DisableXgbeSmmus = TRUE;
+#endif
+
+ if (DisableXgbeSmmus) {
+ DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000");
+ DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000");
+ }
+}
+
+STATIC
+VOID
+SetXgbeStatus (
+ IN VOID *Fdt
+ )
+{
+#if DO_XGBE
+ SetDeviceStatus (Fdt, "xgmac@e0700000", TRUE);
+ SetDeviceStatus (Fdt, "phy@e1240800", TRUE);
+ SetDeviceStatus (Fdt, "xgmac@e0900000", TRUE);
+ SetDeviceStatus (Fdt, "phy@e1240c00", TRUE);
+
+ SetMacAddress (Fdt, "xgmac@e0700000", PcdGet64 (PcdEthMacA));
+ SetMacAddress (Fdt, "xgmac@e0900000", PcdGet64 (PcdEthMacB));
+#else
+ SetDeviceStatus (Fdt, "xgmac@e0700000", FALSE);
+ SetDeviceStatus (Fdt, "phy@e1240800", FALSE);
+ SetDeviceStatus (Fdt, "xgmac@e0900000", FALSE);
+ SetDeviceStatus (Fdt, "phy@e1240c00", FALSE);
+#endif
+}
+
+
+STATIC
+EFI_STATUS
+PrepareFdt (
+ IN OUT VOID *Fdt,
+ IN UINTN FdtSize
+ )
+{
+ EFI_STATUS Status;
+ INT32 Node;
+ INT32 CpuNode;
+ UINTN Index;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ INT32 MapNode;
+ INT32 ClusterNode;
+ INT32 PmuNode;
+ PMU_INTERRUPT PmuInt;
+ INT32 Phandle[NUM_CORES];
+ UINT32 ClusterIndex;
+ UINT32 CoreIndex;
+ UINT32 ClusterCount;
+ UINT32 CoresInCluster;
+ UINT32 ClusterId;
+ UINTN MpId;
+ CHAR8 Name[10];
+ AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
+
+ //
+ // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms.
+ //
+ // For 'cpus' and 'cpu' device tree nodes bindings, refer to this file
+ // in the kernel documentation:
+ // Documentation/devicetree/bindings/arm/cpus.txt
+ //
+ Status = gBS->LocateProtocol (
+ &gAmdMpCoreInfoProtocolGuid,
+ NULL,
+ (VOID **)&AmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Get pointer to ARM core info table
+ ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+ ASSERT (ArmCoreCount <= NUM_CORES);
+
+ // Get Id from primary CPU
+ MpId = (UINTN)ArmReadMpidr ();
+
+ // Create /pmu node
+ PmuNode = fdt_add_subnode(Fdt, 0, "pmu");
+ if (PmuNode >= 0) {
+ fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3");
+
+ // append PMU interrupts
+ for (Index = 0; Index < ArmCoreCount; Index++) {
+ MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+ ArmCoreInfoTable[Index].CoreId);
+
+ Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId));
+ return Status;
+ }
+
+ PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI);
+ PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId);
+ PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL);
+ fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt));
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Create /cpus noide
+ Node = fdt_add_subnode (Fdt, 0, "cpus");
+ if (Node >= 0) {
+ // Configure the 'cpus' node
+ fdt_setprop_string (Fdt, Node, "name", "cpus");
+ fdt_setprop_cell (Fdt, Node, "#address-cells", sizeof (UINTN) / 4);
+ fdt_setprop_cell (Fdt, Node, "#size-cells", 0);
+ } else {
+ DEBUG ((DEBUG_ERROR, "FDT: Error creating 'cpus' node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Walk the processor table in reverse order for proper listing in FDT
+ //
+ Index = ArmCoreCount;
+ while (Index--) {
+ // Create 'cpu' node
+ AsciiSPrint (Name, sizeof (Name), "CPU%d", Index);
+ CpuNode = fdt_add_subnode (Fdt, Node, Name);
+ if (CpuNode < 0) {
+ DEBUG ((DEBUG_ERROR, "FDT: Error on creating '%a' node\n", Name));
+ return EFI_INVALID_PARAMETER;
+ }
+ Phandle[Index] = fdt_alloc_phandle (Fdt);
+ fdt_setprop_cell (Fdt, CpuNode, "phandle", Phandle[Index]);
+ fdt_setprop_cell (Fdt, CpuNode, "linux,phandle", Phandle[Index]);
+
+ fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci");
+
+ MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+ ArmCoreInfoTable[Index].CoreId);
+ MpId = cpu_to_fdt64 (MpId);
+ fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId));
+ fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,armv8");
+ fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu");
+ }
+
+ // Create /cpu-map node
+ MapNode = fdt_add_subnode (Fdt, Node, "cpu-map");
+ if (MapNode >= 0) {
+ ClusterIndex = ArmCoreCount - 1;
+ ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable,
+ ArmCoreCount);
+ while (ClusterCount--) {
+ // Create 'cluster' node
+ AsciiSPrint (Name, sizeof (Name), "cluster%d", ClusterCount);
+ ClusterNode = fdt_add_subnode (Fdt, MapNode, Name);
+ if (ClusterNode < 0) {
+ DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
+ CoreIndex = ClusterIndex;
+ CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
+ ArmCoreCount,
+ ClusterId);
+ while (CoresInCluster--) {
+ // Create 'core' node
+ AsciiSPrint (Name, sizeof (Name), "core%d", CoresInCluster);
+ CpuNode = fdt_add_subnode (Fdt, ClusterNode, Name);
+ if (CpuNode < 0) {
+ DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
+ return EFI_INVALID_PARAMETER;
+ }
+ fdt_setprop_cell (Fdt, CpuNode, "cpu", Phandle[CoreIndex]);
+
+ // iterate to next core in cluster
+ if (CoresInCluster) {
+ do {
+ --CoreIndex;
+ } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
+ }
+ }
+
+ // iterate to next cluster
+ if (ClusterCount) {
+ do {
+ --ClusterIndex;
+ } while (ClusterInRange (ArmCoreInfoTable,
+ ArmCoreInfoTable[ClusterIndex].ClusterId,
+ ClusterIndex + 1,
+ ArmCoreCount - 1));
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR,"FDT: Error creating 'cpu-map' node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SetSocIdStatus (Fdt);
+ SetXgbeStatus (Fdt);
+
+ // Update the real size of the Device Tree
+ fdt_pack (Fdt);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Return a pool allocated copy of the DTB image that is appropriate for
+ booting the current platform via DT.
+
+ @param[out] Dtb Pointer to the DTB copy
+ @param[out] DtbSize Size of the DTB copy
+
+ @retval EFI_SUCCESS Operation completed successfully
+ @retval EFI_NOT_FOUND No suitable DTB image could be located
+ @retval EFI_OUT_OF_RESOURCES No pool memory available
+
+**/
+EFI_STATUS
+EFIAPI
+DtPlatformLoadDtb (
+ OUT VOID **Dtb,
+ OUT UINTN *DtbSize
+ )
+{
+ EFI_STATUS Status;
+ VOID *OrigDtb;
+ VOID *CopyDtb;
+ UINTN OrigDtbSize;
+ UINTN CopyDtbSize;
+ INT32 Error;
+
+ Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid,
+ EFI_SECTION_RAW, 0, &OrigDtb, &OrigDtbSize);
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Allocate space for the DTB: add a page of slack space to make some room
+ // for our modifications.
+ //
+ CopyDtbSize = OrigDtbSize + EFI_PAGE_SIZE;
+ CopyDtb = AllocatePool (CopyDtbSize);
+ if (CopyDtb == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Error = fdt_open_into (OrigDtb, CopyDtb, CopyDtbSize);
+ if (Error != 0) {
+ //
+ // fdt_open_into() validates the DTB header, so if it fails, the template
+ // is most likely invalid.
+ //
+ return EFI_NOT_FOUND;
+ }
+
+ Status = PrepareFdt (CopyDtb, CopyDtbSize);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Dtb = CopyDtb;
+ *DtbSize = CopyDtbSize;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf new file mode 100644 index 0000000000..fc8b25c928 --- /dev/null +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -0,0 +1,65 @@ +/** @file
+*
+* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = StyxDtbLoaderLib
+ FILE_GUID = 3874890c-2917-46a6-8711-8fcaee92260a
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DtPlatformDtbLoaderLib|DXE_DRIVER
+
+[Sources]
+ StyxDtbLoaderLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ DebugLib
+ DxeServicesLib
+ FdtLib
+ MemoryAllocationLib
+ PcdLib
+ PrintLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Guids]
+ gDtPlatformDefaultDtbFileGuid
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## CONSUMED
+
+[Depex]
+ gAmdMpCoreInfoProtocolGuid
diff --git a/Silicon/AMD/Styx/License.txt b/Silicon/AMD/Styx/License.txt new file mode 100644 index 0000000000..ff85835d63 --- /dev/null +++ b/Silicon/AMD/Styx/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
|