Sync SVN commit: 1. November 13, 2015. Vlv2TbltDevicePkg: Add Microcode for MinnowBoard Max, and Change Flash size from 3M to 4M. Contributed-under: TianoCore Contribution Agreement 1.0. Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com> 2. May 18, 2016. Change the whole flash layout to fix the Fv space is not enough when source level debug enabled. [Test] Windows Build BIOS Boot to Win8.1, yocto passed. S3,S4, shutdown passed. Windows Build BIOS Boot to Win10 passed. shutdown passed. Gcc Build BIOS Boot to Win8.1, yocto passed. S3, S4, shutdown passed. <shifeix.a.lu@intel.com>

10 files changed, 68 insertions, 64 deletions

diff --git a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
index 709cdc76ce..233aafcb16 100644
--- a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
+++ b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
@@ -1,6 +1,6 @@
 /** @file

 

-Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2007  - 2016, Intel Corporation. All rights reserved.<BR>

                                                                                    


   This program and the accompanying materials are licensed and made available under


   the terms and conditions of the BSD License that accompanies this distribution.  


@@ -25,8 +25,8 @@ EFI_HII_HANDLE  HiiHandle;
 //00000000	007FFFFF	00800000	Flash Image

 //

 //00000000	00000FFF	00001000	Descriptor Region

-//00001000	004FFFFF	004FF000	TXE Region

-//00500000	007FFFFF	00300000	BIOS Region

+//00001000	003FFFFF	003FF000	TXE Region

+//00500000	007FFFFF	00400000	BIOS Region

 //

 FV_REGION_INFO mRegionInfo[] = {

   {FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
index 48386cb2d4..36954de69f 100644
--- a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
@@ -29,7 +29,7 @@
   FILE_GUID                      = 32F89CBC-305D-4bdd-8B2C-9C65592E66AC

   MODULE_TYPE                    = BASE

   VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = PchPlatformLib

+  LIBRARY_CLASS                  = PchPlatformLib | DXE_DRIVER DXE_RUNTIME_DRIVER  UEFI_DRIVER PEIM DXE_SMM_DRIVER

 

 [sources.common]

   PchPlatformLibrary.h

diff --git a/Vlv2TbltDevicePkg/PlatformPkg.dec b/Vlv2TbltDevicePkg/PlatformPkg.dec
index 378cb530d2..642bcf92a3 100644
--- a/Vlv2TbltDevicePkg/PlatformPkg.dec
+++ b/Vlv2TbltDevicePkg/PlatformPkg.dec
@@ -2,7 +2,7 @@
 # Platform Package

 #

 # This package provides platform specific modules.

-# Copyright (c) 2009  - 2014, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2009  - 2016, Intel Corporation. All rights reserved.<BR>

 #                                                                                  


 # This program and the accompanying materials are licensed and made available under


 # the terms and conditions of the BSD License that accompanies this distribution.  


@@ -152,9 +152,9 @@
   gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003

   gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004

   gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009

-  gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x004FF000|UINT32|0x4000000A

-  gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFD00000|UINT32|0x4000000B

-  gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00300000|UINT32|0x4000000C

+  gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4000000A

+  gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x4000000B

+  gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x4000000C

 

 [PcdsFeatureFlag]

   ## This PCD specifies whether StatusCode is reported via ISA Serial port.

diff --git a/Vlv2TbltDevicePkg/PlatformPkg.fdf b/Vlv2TbltDevicePkg/PlatformPkg.fdf
index 0345b29615..3432904825 100644
--- a/Vlv2TbltDevicePkg/PlatformPkg.fdf
+++ b/Vlv2TbltDevicePkg/PlatformPkg.fdf
@@ -1,7 +1,7 @@
 #/** @file
 # FDF file of Platform.
 #
-# Copyright (c) 2008  - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008  - 2016, Intel Corporation. All rights reserved.<BR>
 #                                                                                  
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.  
@@ -15,46 +15,46 @@
 #**/
 
 [Defines]
-DEFINE FLASH_BASE       = 0xFFD00000     #The base address of the 3Mb FLASH Device.
-DEFINE FLASH_SIZE       = 0x00300000     #The flash size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_NUM_BLOCKS = 0x300           #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_BASE       = 0xFFC00000     #The base address of the 4Mb FLASH Device.
+DEFINE FLASH_SIZE       = 0x00400000     #The flash size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x400           #The number of blocks in 4Mb FLASH Device.
 DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000
 DEFINE FLASH_AREA_SIZE                                        = 0x00800000
 
 DEFINE FLASH_REGION_VLVMICROCODE_OFFSET                       = 0x00000000 
-DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00030000
-DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFD00000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00040000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFC00000
 
-DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00030000
+DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00040000
 DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0003E000
 
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000
 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000
 
 
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00070000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00080000
 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00040000
 
 !if $(MINNOW2_FSP_BUILD) == TRUE
-DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000C0000
 DEFINE FLASH_REGION_FSPBIN_SIZE                               = 0x00048000
-DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFDB0000
+DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFCC0000
 
-DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x00108000
 DEFINE FLASH_REGION_AZALIABIN_SIZE                            = 0x00008000
-DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFDF8000
+DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFD08000
 
 !endif
 
-DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00100000
-DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x001A5000
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00110000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00215000
 
-DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x002A5000
-DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0002B000
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x00325000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0006B000
  
-DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x002D0000
-DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00030000
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x00390000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00070000
 
 ################################################################################
 #
diff --git a/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
index 47ec3f01af..3326fb2925 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
+++ b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
@@ -1,7 +1,7 @@
 #/** @file
 # FDF file of Platform.
 #
-# Copyright (c) 2008  - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008  - 2016, Intel Corporation. All rights reserved.<BR>
 #                                                                                  
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.  
@@ -15,47 +15,46 @@
 #**/
 
 [Defines]
-DEFINE FLASH_BASE       = 0xFFD00000     #The base address of the 3Mb FLASH Device.
-DEFINE FLASH_SIZE       = 0x00300000     #The flash size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_NUM_BLOCKS = 0x300           #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_BASE       = 0xFFC00000     #The base address of the 4Mb FLASH Device.
+DEFINE FLASH_SIZE       = 0x00400000     #The flash size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x400           #The number of blocks in 4Mb FLASH Device.
 DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000
 DEFINE FLASH_AREA_SIZE                                        = 0x00800000
 
 DEFINE FLASH_REGION_VLVMICROCODE_OFFSET                       = 0x00000000 
-DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00030000
-DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFD00000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00040000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFC00000
 
-DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00030000
+DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00040000
 DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0003E000
 
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000
 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000
 
 
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00070000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00080000
 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00040000
 
 !if $(MINNOW2_FSP_BUILD) == TRUE
-DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000C0000
 DEFINE FLASH_REGION_FSPBIN_SIZE                               = 0x00048000
-DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFDB0000
+DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFCC0000
 
-DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x00108000
 DEFINE FLASH_REGION_AZALIABIN_SIZE                            = 0x00008000
-DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFDF8000
+DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFD08000
 
 !endif
 
-DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00100000
-DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00196000
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00110000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00215000
 
-
-DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x00296000
-DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0002C000
-
-DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x002C2000
-DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x0003E000
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x00325000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0006B000
+ 
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x00390000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00070000
 
 ################################################################################
 #
diff --git a/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc b/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
index d989a305c4..3891c7752a 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
+++ b/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
@@ -1,7 +1,7 @@
 #/** @file
 # Platform description.
 #
-# Copyright (c) 2012  - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012  - 2016, Intel Corporation. All rights reserved.<BR>
 #                                                                                  
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.  
@@ -604,16 +604,16 @@
 [PcdsFixedAtBuild.common]
 !if $(MINNOW2_FSP_BUILD) == TRUE
 # $(FLASH_REGION_VLVMICROCODE_BASE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
 # $(FLASH_REGION_VLVMICROCODE_SIZE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
   gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
 # $(FLASH_AREA_BASE_ADDRESS)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
 # $(FLASH_AREA_SIZE)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
 # $(FLASH_REGION_FSPBIN_BASE)
-  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
 !endif
 
 !if $(PERFORMANCE_ENABLE) == TRUE
@@ -1017,6 +1017,7 @@ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf
 !endif
   }
 
+
  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
 
@@ -1177,7 +1178,7 @@ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf
 !endif
    MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
     <LibraryClasses>
-   FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
   }
 
   MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
diff --git a/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc b/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
index b445009a86..684f2fe1ef 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
+++ b/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
@@ -1,7 +1,7 @@
 #/** @file
 # Platform description.
 #
-# Copyright (c) 2012  - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012  - 2016, Intel Corporation. All rights reserved.<BR>
 #                                                                                  
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.  
@@ -604,16 +604,16 @@
 [PcdsFixedAtBuild.common]
 !if $(MINNOW2_FSP_BUILD) == TRUE
 # $(FLASH_REGION_VLVMICROCODE_BASE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
 # $(FLASH_REGION_VLVMICROCODE_SIZE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
   gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
 # $(FLASH_AREA_BASE_ADDRESS)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
 # $(FLASH_AREA_SIZE)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
 # $(FLASH_REGION_FSPBIN_BASE)
-  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
 !endif
 
 !if $(PERFORMANCE_ENABLE) == TRUE
@@ -1142,7 +1142,7 @@ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf
   MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
   MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
-  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
+   MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
     <LibraryClasses>
       NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
       SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
diff --git a/Vlv2TbltDevicePkg/PlatformPkgX64.dsc b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
index 97e2f72b5b..a07df1cb7e 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
+++ b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
@@ -1,7 +1,7 @@
 #/** @file
 # Platform description.
 #
-# Copyright (c) 2012  - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012  - 2016, Intel Corporation. All rights reserved.<BR>
 #                                                                                  
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.  
@@ -604,16 +604,16 @@
 [PcdsFixedAtBuild.common]
 !if $(MINNOW2_FSP_BUILD) == TRUE
 # $(FLASH_REGION_VLVMICROCODE_BASE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
 # $(FLASH_REGION_VLVMICROCODE_SIZE)
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
   gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
 # $(FLASH_AREA_BASE_ADDRESS)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
 # $(FLASH_AREA_SIZE)
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
 # $(FLASH_REGION_FSPBIN_BASE)
-  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
 !endif
 
 !if $(PERFORMANCE_ENABLE) == TRUE
@@ -829,6 +829,9 @@
   !if $(TPM_ENABLED) == TRUE
     gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
   !endif
+  !if $(FTPM_ENABLE) == TRUE
+    gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  !endif
 
   ## This PCD defines the video horizontal resolution.
   #  This PCD could be set to 0 then video resolution could be at highest resolution.
@@ -1011,6 +1014,7 @@ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf
 !endif
   }
 
+
  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
 
diff --git a/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
index 5c26f1ed01..ca10f7af61 100644
--- a/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
+++ b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
diff --git a/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPILOCK.bin b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPILOCK.bin
new file mode 100644
index 0000000000..f2dcb0067d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPILOCK.bin