diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 13:50:39 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:55:34 +0800 |
| commit | 48f455b9a53e42468ba5069a8e6ca876b1349900 (patch) | |
| tree | 15f7c7eb87c02d59366b245aa5875e6d243dfc8f | |
| parent | e468aeccbf0401410445639ed516f3b72f8209bb (diff) | |
| download | edk2-platforms-48f455b9a53e42468ba5069a8e6ca876b1349900.tar.xz | |
ChvRefCodePkg: Add SouthCluster include files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
64 files changed, 15465 insertions, 0 deletions
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/CmosMap.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/CmosMap.h new file mode 100644 index 0000000000..1034a9fb4e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/CmosMap.h @@ -0,0 +1,178 @@ +/** @file
+ This header file provides platform specific definitions used by other modules
+ for platform specific initialization.
+
+ This is not suitable for consumption by ASL or VRF files.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CMOSMAP_H_
+#define _CMOSMAP_H_
+
+//
+//GENERAL USAGE GUIDELINES
+//
+
+//
+// CMOS 0x00 - 0x0F are used by RTC. defined in ICHx spec
+// CMOS 0x10 - 0x7F are reserved for board specific use by Intel
+// CMOS 0x80 - 0xFF are reserved for OEM use only
+//
+
+#define CmosIo_70 0x70
+#define CmosIo_71 0x71
+#define CmosIo_72 0x72
+#define CmosIo_73 0x73
+
+//
+//PLATFORM SPECIFIC USAGE
+//
+
+#define CPU_HT_POLICY 0x50
+#define CPU_HT_POLICY_ENABLED 0x01
+
+#define TPM_POLICY 0x60
+#define TPM_POLICY_ENABLED 0x01
+
+#define CMOS_LCDPANELTYPE_REG 0x61
+#define CMOS_LCDPANELSCALING_REG 0x62
+#define CMOS_IGDBOOTTYPE_REG 0x63
+#define CMOS_BACKLIGHT_REG 0x64
+#define CMOS_LFP_PANEL_COLOR_DEPTH_REG 0x65
+#define CMOS_EDP_ACTIVE_LFP_CONFIG_REG 0x66
+#define CMOS_PRIMARY_DISPLAY_REG 0x67
+#define CMOS_IGD_DISPLAY_PIPE_B_REG 0x68
+#define CMOS_LFP_INVERTER_TYPE 0x69
+#define CMOS_CPV_STATE 0x6A
+#define CMOS_PLATFORM_RESET_OS 0x80
+#define CMOS_CPU_BSP_SELECT 0x90
+#define CMOS_CPU_RATIO_OFFSET 0x92
+#define CMOS_ICH_PORT80_OFFSET 0x97
+
+#define CMOS_DATA_PORT 0x71
+#define CMOS_ADDR_PORT 0x70
+#define CMOS_BAD_REG 0xe
+
+#define CMOS_MAXRATIO_CONFIG_REG 0xEF
+
+#define CMOS_BOOT_REGISTER_REG 0x47
+#define RTC_ADDRESS_CENTURY 0x32
+#define RTC_ADDRESS_CENTURY_DEFAULT 0x20 //20th Century.BCD value
+
+//
+// Post Code value to be break at
+//
+#define CMOS_POST_CODE_BREAK_REG 0x48
+#define CMOS_POST_CODE_BREAK_1_REG 0x49
+#define CMOS_POST_CODE_BREAK_2_REG 0x4A
+#define CMOS_POST_CODE_BREAK_3_REG 0x4B
+
+//
+// Debug Mask saved in CMOS
+//
+#define CMOS_DEBUG_PRINT_LEVEL_REG 0x4C
+#define CMOS_DEBUG_PRINT_LEVEL_1_REG 0x4D
+#define CMOS_DEBUG_PRINT_LEVEL_2_REG 0x4E
+#define CMOS_DEBUG_PRINT_LEVEL_3_REG 0x4F
+//
+// CMOS usage Upper CMOS bank offsets:
+//
+//#define CMOS_CPU_BSP_SELECT 0x10
+#define CMOS_CPU_UP_MODE 0x11
+//#define CMOS_CPU_RATIO_OFFSET 0x12
+#define CMOS_CPU_CORE_HT_OFFSET 0x13
+#define CMOS_EFI_DEBUG 0x14
+#define CMOS_CPU_BIST_OFFSET 0x15
+#define CMOS_CPU_VMX_OFFSET 0x16
+#define CMOS_PORT80_OFFSET 0x17
+#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID
+#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP
+#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
+#define CMOS_DCU_MODE_OFFSET 0x1B
+#define CMOS_VR11_SET_OFFSET 0x1C
+#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!
+#define TCG_CMOS_AREA_OFFSET 0x60 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
+ // Also Change in Platform\IntelEpg\Thurley\Dxe\AcpiTables\Dsdt\Tpm.asi
+#define TCG_CMOS_MOR_AREA_OFFSET (TCG_CMOS_AREA_OFFSET + 0x05) // Also Change in Platform\IntelEpg\Thurley\Dxe\AcpiTables\Dsdt\Tpm.asi
+
+#define EFI_CMOS_START_ADDRESS 0x40
+#define EFI_CMOS_END_ADDRESS 0x7F
+
+#define EFI_CMOS_CHECKSUM_ADDRESS 0x4F
+#define EFI_CMOS_HYPERBOOT_FLAGS 0x50
+#define B_CMOS_FIRST_BOOT 0x01
+#define B_CMOS_BOOT_SUCCESS 0x02
+#define B_CMOS_HYPERBOOT_STATUS 0x04
+#define B_CMOS_HYPERBOOT_RECOVERY 0x08
+#define B_CMOS_BOOT_FAILED 0x10
+#define B_CMOS_BOOT_LOCK 0x20
+#define EFI_CMOS_BOOT_CFG_FLAGS 0x51
+#define B_CMOS_BOOT_CFG_EXIST 0x01
+#define B_CMOS_BOOT_CFG_BOOT_MENU 0x02
+#define B_CMOS_BOOT_CFG_BOOT_CD 0x04
+#define B_CMOS_BOOT_CFG_BOOT_FDD 0x08
+#define B_CMOS_BOOT_CFG_BOOT_PXE 0x10
+#define B_CMOS_BOOT_CFG_BOOT_USB 0x20
+#define B_CMOS_BOOT_CFG_USB_FIRST 0x40
+#define B_CMOS_BOOT_CFG_BOOT_UEFI 0x80
+#define EFI_CMOS_PENDING_ME_BIOS_ACTION 0x6D
+#define EFI_CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
+#define EFI_CMOS_XP_FLAG_ADDRESS 0x6F
+#define EFI_CMOS_CAPSULE_ADDRESS_1 0x70
+#define EFI_CMOS_CAPSULE_ADDRESS_2 0x71
+#define EFI_CMOS_CAPSULE_ADDRESS_3 0x72
+#define EFI_CMOS_CAPSULE_ADDRESS_4 0x73
+#define EFI_CMOS_PERFORMANCE_FLAGS 0x74
+#define B_CMOS_MEMORY_INIT 0x01
+#define B_CMOS_FORCED_REBOOT 0x02
+#define B_CMOS_ALLOW_RESET 0x04
+#define B_CMOS_WD_RUNNING_FROM_OS 0x08
+#define B_CMOS_WD_FAILURE_STATUS_TO_OS 0x10
+#define B_CMOS_BIOS_RESET_PERF_SETTINGS_TO_OS 0x20
+#define B_CMOS_TCO_WDT_RESET 0x40
+#define EFI_ACPI_TPM_REQUEST 0x75
+#define EFI_ACPI_TPM_LAST_REQUEST 0x76
+#define EFI_ACPI_TPM_MORD 0x77
+#define EFI_CMOS_UCLK_DEFAULT 0x78
+#define EFI_CMOS_CCLK_DEFAULT 0x79
+#define EFI_CMOS_QCLK_DEFAULT 0x7A
+#define EFI_CMOS_BURN_IN_MODE_FLAGS 0x7C
+#define B_CMOS_BIM_HANG 0x01
+#define EFI_CMOS_ACPI_TABLE_FLAG_ADDRESS 0x7D
+#define B_CMOS_HPET_ENABLED 0x01
+#define EFI_CMOS_BOOT_FLAG_ADDRESS 0x7E
+#define B_CMOS_THERMAL_TRIP 0x01
+#define B_CMOS_FORCE_ENTER_SETUP 0x02
+#define B_CMOS_FORCE_NETWORK_BOOT 0x04
+#define B_CMOS_TPM_ENABLED 0x08
+#define EFI_CMOS_SX_STATE_FLAG_ADDRESS 0x7F
+#define B_CMOS_S5_SHUTDOWN 0x01
+#define EFI_CMOS_RESET_TYPE_BY_OS 0x52
+
+#define EFI_CMOS_EOL 0xFFFF
+#define EFI_CMOS_CHECKSUM_EXCLUDES {EFI_CMOS_CHECKSUM_ADDRESS, \
+ EFI_CMOS_XP_FLAG_ADDRESS, \
+ EFI_ACPI_TPM_REQUEST, \
+ EFI_ACPI_TPM_LAST_REQUEST, \
+ EFI_ACPI_TPM_MORD, \
+ EFI_CMOS_BOOT_FLAG_ADDRESS, \
+ EFI_CMOS_S4_WAKEUP_FLAG_ADDRESS, \
+ EFI_CMOS_ACPI_TABLE_FLAG_ADDRESS, \
+ EFI_CMOS_SX_STATE_FLAG_ADDRESS, \
+ EFI_CMOS_PERFORMANCE_FLAGS, \
+ EFI_CMOS_BURN_IN_MODE_FLAGS, \
+ EFI_CMOS_HYPERBOOT_FLAGS, \
+ EFI_CMOS_BOOT_CFG_FLAGS, \
+ EFI_CMOS_EOL }
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/Chv2Variable.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/Chv2Variable.h new file mode 100644 index 0000000000..51e7d697d2 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/Chv2Variable.h @@ -0,0 +1,21 @@ +/** @file
+ GUID used to define ValleyView2 variable.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHV_VARIABLE_GUID_H_
+#define _CHV_VARIABLE_GUID_H_
+
+extern EFI_GUID gEfiChvVariableGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/SataControllerGuid.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/SataControllerGuid.h new file mode 100644 index 0000000000..9b58785ec9 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/SataControllerGuid.h @@ -0,0 +1,20 @@ +/** @file
+ GUID for use in describing SataController
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SERIAL_ATA_CONTROLLER_GUID_H_
+#define _SERIAL_ATA_CONTROLLER_GUID_H_
+
+extern EFI_GUID gSataControllerDriverGuid;
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/VbtExtInfo.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/VbtExtInfo.h new file mode 100644 index 0000000000..6439208663 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Guid/VbtExtInfo.h @@ -0,0 +1,40 @@ +/** @file
+ GUID used for extended VBT Info Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VBT_EXT_INFO_H_
+#define _VBT_EXT_INFO_H_
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+
+#define EFI_VBT_EXT_INFO_GUID \
+ { \
+ 0x82411907, 0xdbc9, 0x4ece, 0xbe, 0x7c, 0xd0, 0x74, 0x4f, 0x19, 0x61, 0x26 \
+ }
+
+#pragma pack(1)
+
+typedef struct _EFI_VBT_EXT_INFO_HOB {
+ EFI_PHYSICAL_ADDRESS VbtExtAddress;
+ UINT32 VbtExtSize;
+} EFI_VBT_EXT_INFO_HOB;
+
+#pragma pack()
+
+extern EFI_GUID gEfiVbtExtInfoGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/CeAta.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/CeAta.h new file mode 100644 index 0000000000..b68ecdcd2a --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/CeAta.h @@ -0,0 +1,105 @@ +/** @file
+ Header file for chipset CE-AT spec.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CE_ATA_H
+#define _CE_ATA_H
+
+#pragma pack(1)
+
+#define DATA_UNIT_SIZE 512
+
+#define CMD60 60
+#define CMD61 61
+
+#define RW_MULTIPLE_REGISTER CMD60
+#define RW_MULTIPLE_BLOCK CMD61
+
+#define CE_ATA_SIG_CE 0xCE
+#define CE_ATA_SIG_AA 0xAA
+
+#define Reg_Features_Exp 01
+#define Reg_SectorCount_Exp 02
+#define Reg_LBALow_Exp 03
+#define Reg_LBAMid_Exp 04
+#define Reg_LBAHigh_Exp 05
+#define Reg_Control 06
+#define Reg_Features_Error 09
+#define Reg_SectorCount 10
+#define Reg_LBALow 11
+#define Reg_LBAMid 12
+#define Reg_LBAHigh 13
+#define Reg_Device_Head 14
+#define Reg_Command_Status 15
+
+#define Reg_scrTempC 0x80
+#define Reg_scrTempMaxP 0x84
+#define Reg_scrTempMinP 0x88
+#define Reg_scrStatus 0x8C
+#define Reg_scrReallocsA 0x90
+#define Reg_scrERetractsA 0x94
+#define Reg_scrCapabilities 0x98
+#define Reg_scrControl 0xC0
+
+typedef struct {
+ UINT8 Reserved0;
+ UINT8 Features_Exp;
+ UINT8 SectorCount_Exp;
+ UINT8 LBALow_Exp;
+ UINT8 LBAMid_Exp;
+ UINT8 LBAHigh_Exp;
+ UINT8 Control;
+ UINT8 Reserved1[2];
+ UINT8 Features_Error;
+ UINT8 SectorCount;
+ UINT8 LBALow;
+ UINT8 LBAMid;
+ UINT8 LBAHigh;
+ UINT8 Device_Head;
+ UINT8 Command_Status;
+}TASK_FILE;
+
+//
+//Reduced ATA command set
+//
+#define IDENTIFY_DEVICE 0xEC
+#define READ_DMA_EXT 0x25
+#define WRITE_DMA_EXT 0x35
+#define STANDBY_IMMEDIATE 0xE0
+#define FLUSH_CACHE_EXT 0xEA
+
+typedef struct {
+ UINT16 Reserved0[10];
+ UINT16 SerialNumber[10];
+ UINT16 Reserved1[3];
+ UINT16 FirmwareRevision[4];
+ UINT16 ModelNumber[20];
+ UINT16 Reserved2[33];
+ UINT16 MajorVersion;
+ UINT16 Reserved3[19];
+ UINT16 MaximumLBA[4];
+ UINT16 Reserved4[2];
+ UINT16 Sectorsize;
+ UINT16 Reserved5;
+ UINT16 DeviceGUID[4];
+ UINT16 Reserved6[94];
+ UINT16 Features;
+ UINT16 MaxWritesPerAddress;
+ UINT16 Reserved7[47];
+ UINT16 IntegrityWord;
+}IDENTIFY_DEVICE_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/Mmc.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/Mmc.h new file mode 100644 index 0000000000..1b3631f2ca --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/Mmc.h @@ -0,0 +1,334 @@ +/** @file
+ Header file for Industry MMC 4.2 spec.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MMC_H
+#define _MMC_H
+
+#pragma pack(1)
+
+//
+// Command definition
+//
+#define CMD0 0
+#define CMD1 1
+#define CMD2 2
+#define CMD3 3
+#define CMD4 4
+#define CMD6 6
+#define CMD7 7
+#define CMD8 8
+#define CMD9 9
+#define CMD10 10
+#define CMD11 11
+#define CMD12 12
+#define CMD13 13
+#define CMD14 14
+#define CMD15 15
+#define CMD16 16
+#define CMD17 17
+#define CMD18 18
+#define CMD19 19
+#define CMD20 20
+#define CMD23 23
+#define CMD24 24
+#define CMD25 25
+#define CMD26 26
+#define CMD27 27
+#define CMD28 28
+#define CMD29 29
+#define CMD30 30
+#define CMD35 35
+#define CMD36 36
+#define CMD38 38
+#define CMD39 39
+#define CMD40 40
+#define CMD42 42
+#define CMD55 55
+#define CMD56 56
+
+#define GO_IDLE_STATE CMD0
+#define SEND_OP_COND CMD1
+#define ALL_SEND_CID CMD2
+#define SET_RELATIVE_ADDR CMD3
+#define SET_DSR CMD4
+#define SWITCH CMD6
+#define SELECT_DESELECT_CARD CMD7
+#define SEND_EXT_CSD CMD8
+#define SEND_CSD CMD9
+#define SEND_CID CMD10
+#define READ_DAT_UNTIL_STOP CMD11
+#define STOP_TRANSMISSION CMD12
+#define SEND_STATUS CMD13
+#define BUSTEST_R CMD14
+#define GO_INACTIVE_STATE CMD15
+#define SET_BLOCKLEN CMD16
+#define READ_SINGLE_BLOCK CMD17
+#define READ_MULTIPLE_BLOCK CMD18
+#define BUSTEST_W CMD19
+#define WRITE_DAT_UNTIL_STOP CMD20
+#define SET_BLOCK_COUNT CMD23
+#define WRITE_BLOCK CMD24
+#define WRITE_MULTIPLE_BLOCK CMD25
+#define PROGRAM_CID CMD26
+#define PROGRAM_CSD CMD27
+#define SET_WRITE_PROT CMD28
+#define CLR_WRITE_PROT CMD29
+#define SEND_WRITE_PROT CMD30
+#define ERASE_GROUP_START CMD35
+#define ERASE_GROUP_END CMD36
+#define ERASE CMD38
+#define FAST_IO CMD39
+#define GO_IRQ_STATE CMD40
+#define LOCK_UNLOCK CMD42
+#define APP_CMD CMD55
+#define GEN_CMD CMD56
+
+#define B_PERM_WP_DIS 0x10
+#define B_PWR_WP_EN 0x01
+#define US_PERM_WP_DIS 0x10
+#define US_PWR_WP_EN 0x01
+
+#define FREQUENCY_OD (400 * 1000)
+#define FREQUENCY_MMC_PP (26 * 1000 * 1000)
+#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
+#define FREQUENCY_MMC_HS (200 * 1000 * 1000)
+
+#define DEFAULT_DSR_VALUE 0x404
+
+//
+// Registers definition
+//
+typedef struct {
+ UINT32 Reserved0: 7; // 0
+ UINT32 V170_V195: 1; // 1.70V - 1.95V
+ UINT32 V200_V260: 7; // 2.00V - 2.60V
+ UINT32 V270_V360: 9; // 2.70V - 3.60V
+ UINT32 Reserved1: 5; // 0
+ UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
+ UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
+} OCR;
+
+typedef struct {
+ UINT8 NotUsed: 1; // 1
+ UINT8 CRC: 7; // CRC7 checksum
+ UINT8 MDT; // Manufacturing date
+ UINT32 PSN; // Product serial number
+ UINT8 PRV; // Product revision
+ UINT8 PNM[6]; // Product name
+ UINT16 OID; // OEM/Application ID
+ UINT8 MID; // Manufacturer ID
+} CID;
+
+typedef struct {
+ UINT8 NotUsed: 1; // 1 [0:0]
+ UINT8 CRC: 7; // CRC [7:1]
+ UINT8 ECC: 2; // ECC code [9:8]
+ UINT8 FILE_FORMAT: 2; // File format [11:10]
+ UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
+ UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
+ UINT8 COPY: 1; // Copy flag (OTP) [14:14]
+ UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
+ UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
+ UINT16 Reserved0: 4; // 0 [20:17]
+ UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
+ UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
+ UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
+ UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
+ UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
+ UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
+ UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
+ UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
+ UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
+ UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
+ UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
+ UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
+ UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
+ UINT32 C_SIZELow2: 2;// Device size [73:62]
+ UINT32 C_SIZEHigh10: 10;// Device size [73:62]
+ UINT32 Reserved1: 2; // 0 [75:74]
+ UINT32 DSR_IMP: 1; // DSR implemented [76:76]
+ UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
+ UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
+ UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
+ UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
+ UINT32 CCC: 12;// Card command classes [95:84]
+ UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
+ UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT8 TAAC ; // Data read access-time 1 [119:112]
+ UINT8 Reserved2: 2; // 0 [121:120]
+ UINT8 SPEC_VERS: 4; // System specification version [125:122]
+ UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
+} CSD;
+
+typedef struct {
+ UINT8 Reserved133_0[134]; // [133:0] 0
+ UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode
+ UINT8 Reserved135; // [135] 0
+ UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address
+ UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size
+ UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size
+ UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size
+ UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size
+ UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size
+ UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting
+ UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes
+ UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size
+ UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support
+ UINT8 HPI_MGMT; // [161] HPI management
+ UINT8 RST_n_FUNCTION; // [162] H/W reset function
+ UINT8 BKOPS_EN; // [163] Enable background operations handshake
+ UINT8 BKOPS_START; // [164] Manually start background operations
+ UINT8 Reserved165; // [165] 0
+ UINT8 WR_REL_PARAM; // [166] Write reliability parameter register
+ UINT8 WR_REL_SET; // [167] Write reliability setting register
+ UINT8 RPMB_SIZE_MULT; // [168] RPMB Size
+ UINT8 FW_CONFIG; // [169] FW configuration
+ UINT8 Reserved170; // [170] 0
+ UINT8 USER_WP; // [171] User area write protection
+ UINT8 Reserved172; // [172] 0
+ UINT8 BOOT_WP; // [173] Boot area write protection
+ UINT8 Reserved174; // [174] 0
+ UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition
+ UINT8 Reserved176; // [176] 0
+ UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width
+ UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection
+ UINT8 PARTITION_CONFIG; // [179] Partition config
+ UINT8 Reserved180; // [180] 0
+ UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content
+ UINT8 Reserved182; // [182] 0
+ UINT8 BUS_WIDTH; // [183] Bus Width Mode
+ UINT8 Reserved184; // [184] 0
+ UINT8 HS_TIMING; // [185] High Speed Interface Timing
+ UINT8 Reserved186; // [186] 0
+ UINT8 POWER_CLASS; // [187] Power Class
+ UINT8 Reserved188; // [188] 0
+ UINT8 CMD_SET_REV; // [189] Command Set Revision
+ UINT8 Reserved190; // [190] 0
+ UINT8 CMD_SET; // [191] Command Set
+ UINT8 EXT_CSD_REV; // [192] Extended CSD Revision
+ UINT8 Reserved193; // [193] 0
+ UINT8 CSD_STRUCTURE; // [194] CSD Structure Version
+ UINT8 Reserved195; // [195] 0
+ UINT8 CARD_TYPE; // [196] Card Type
+ UINT8 DRIVER_STRENGTH; // [197] Driver Strength
+ UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing
+ UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing
+ UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V
+ UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V
+ UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V
+ UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V
+ UINT8 Reserved204; // [204] 0
+ UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz
+ UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz
+ UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz
+ UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz
+ UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz
+ UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz
+ UINT8 Reserved211; // [211] 0
+ UINT8 SEC_COUNT[4]; // [215:212] Sector Count
+ UINT8 Reserved216; // [216] 0
+ UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout
+ UINT8 Reserved218; // [218] 0
+ UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)
+ UINT8 S_C_VCC; // [220] Sleep current (VCC)
+ UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size
+ UINT8 REL_WR_SEC_C; // [222] Reliable write sector count
+ UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout
+ UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size
+ UINT8 ACC_SIZE; // [225] Access size
+ UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size
+ UINT8 Reserved227; // [227] 0
+ UINT8 BOOT_INFO; // [228] Boot information
+ UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier
+ UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier
+ UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support
+ UINT8 TRIM_MULT; // [232] TRIM Multiplier
+ UINT8 Reserved233; // [233] 0
+ UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz
+ UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz
+ UINT8 Reserved237_236[2]; // [237:236] 0
+ UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V
+ UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V
+ UINT8 Reserved240; // [240] 0
+ UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning
+ UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors
+ UINT8 BKOPS_STATUS; // [246] Background operations status
+ UINT8 Reserved501_247[255]; // [501:247] 0
+ UINT8 BKOPS_SUPPORT; // [502] Background operations support
+ UINT8 HPI_FEATURES; // [503] HPI features
+ UINT8 S_CMD_SET; // [504] Sector Count
+ UINT8 Reserved511_505[7]; // [511:505] Sector Count
+} EXT_CSD;
+
+//
+//Card Status definition
+//
+typedef struct {
+ UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
+ UINT32 Reserved1: 2; //Reserved for Application Specific commands
+ UINT32 Reserved2: 1; //
+ UINT32 SAPP_CMD: 1; //
+ UINT32 Reserved3: 1; //Reserved
+ UINT32 SWITCH_ERROR: 1; //
+ UINT32 READY_FOR_DATA: 1; //
+ UINT32 CURRENT_STATE: 4; //
+ UINT32 ERASE_RESET: 1; //
+ UINT32 Reserved4: 1; //Reserved
+ UINT32 WP_ERASE_SKIP: 1; //
+ UINT32 CID_CSD_OVERWRITE: 1; //
+ UINT32 OVERRUN: 1; //
+ UINT32 UNDERRUN: 1; //
+ UINT32 ERROR: 1; //
+ UINT32 CC_ERROR: 1; //
+ UINT32 CARD_ECC_FAILED: 1; //
+ UINT32 ILLEGAL_COMMAND: 1; //
+ UINT32 COM_CRC_ERROR: 1; //
+ UINT32 LOCK_UNLOCK_FAILED: 1; //
+ UINT32 CARD_IS_LOCKED: 1; //
+ UINT32 WP_VIOLATION: 1; //
+ UINT32 ERASE_PARAM: 1; //
+ UINT32 ERASE_SEQ_ERROR: 1; //
+ UINT32 BLOCK_LEN_ERROR: 1; //
+ UINT32 ADDRESS_MISALIGN: 1; //
+ UINT32 ADDRESS_OUT_OF_RANGE:1; //
+} CARD_STATUS;
+
+typedef struct {
+ UINT32 CmdSet: 3;
+ UINT32 Reserved0: 5;
+ UINT32 Value: 8;
+ UINT32 Index: 8;
+ UINT32 Access: 2;
+ UINT32 Reserved1: 6;
+} SWITCH_ARGUMENT;
+
+#define CommandSet_Mode 0
+#define SetBits_Mode 1
+#define ClearBits_Mode 2
+#define WriteByte_Mode 3
+
+#define Idle_STATE 0
+#define Ready_STATE 1
+#define Ident_STATE 2
+#define Stby_STATE 3
+#define Tran_STATE 4
+#define Data_STATE 5
+#define Rcv_STATE 6
+#define Prg_STATE 7
+#define Dis_STATE 8
+#define Btst_STATE 9
+
+#pragma pack()
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/SdCard.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/SdCard.h new file mode 100644 index 0000000000..3d581d4fb1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IndustryStandard/SdCard.h @@ -0,0 +1,139 @@ +/** @file
+ Header file for Industry SD Card 2.0 spec.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SD_CARD_H
+#define _SD_CARD_H
+
+#include <IndustryStandard/Mmc.h>
+
+#pragma pack(1)
+
+#define CHECK_PATTERN 0xAA ///< Physical Layer Simplified Specification Version 3.01 recommended 0xAA
+
+#define ACMD6 6
+#define ACMD13 13
+#define ACMD23 23
+#define ACMD41 41
+#define ACMD42 42
+#define ACMD51 51
+
+#define SWITCH_FUNC CMD6
+#define SEND_IF_COND CMD8
+
+#define SET_BUS_WIDTH ACMD6
+#define SD_STATUS ACMD13
+#define SET_WR_BLK_ERASE_COUNT ACMD23
+#define SD_SEND_OP_COND ACMD41
+#define SET_CLR_CARD_DETECT ACMD42
+#define SEND_SCR ACMD51
+
+#define SD_BUS_WIDTH_1 0
+#define SD_BUS_WIDTH_4 2
+
+#define FREQUENCY_SD_PP (25 * 1000 * 1000)
+#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)
+
+#define SD_SPEC_10 0
+#define SD_SPEC_11 1
+#define SD_SPEC_20 2
+
+#define VOLTAGE_27_36 0x1
+
+typedef struct {
+ UINT8 NotUsed: 1; // 1 [0:0]
+ UINT8 CRC: 7; // CRC [7:1]
+ UINT8 ECC: 2; // ECC code [9:8]
+ UINT8 FILE_FORMAT: 2; // File format [11:10]
+ UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
+ UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
+ UINT8 COPY: 1; // Copy flag (OTP) [14:14]
+ UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
+ UINT16 Reserved0: 5; // 0 [20:16]
+ UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
+ UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
+ UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
+ UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
+ UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
+ UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
+ UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
+ UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
+ UINT16 Reserved1: 1; // 0 [47:47]
+
+ UINT32 C_SIZE: 22; // Device size [69:48]
+ UINT32 Reserved2: 6; // 0 [75:70]
+ UINT32 DSR_IMP: 1; // DSR implemented [76:76]
+ UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
+ UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
+ UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
+
+ UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
+ UINT16 CCC: 12; // Card command classes [95:84]
+ UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
+ UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT8 TAAC ; // Data read access-time 1 [119:112]
+ UINT8 Reserved3: 6; // 0 [125:120]
+ UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
+} CSD_SDV2;
+
+typedef struct {
+ UINT32 Reserved0;
+ UINT32 Reserved1: 16;
+ UINT32 SD_BUS_WIDTH: 4;
+ UINT32 SD_SECURITY: 3;
+ UINT32 DATA_STAT_AFTER_ERASE: 1;
+ UINT32 SD_SPEC: 4;
+ UINT32 SCR_STRUCT: 4;
+} SCR;
+
+typedef struct {
+ UINT8 Reserved0[50];
+ UINT8 ERASE_OFFSET: 2;
+ UINT8 ERASE_TIMEOUT: 6;
+ UINT16 ERASE_SIZE;
+ UINT8 Reserved1: 4;
+ UINT8 AU_SIZE: 4;
+ UINT8 PERFORMANCE_MOVE;
+ UINT8 SPEED_CLASS;
+ UINT32 SIZE_OF_PROTECTED_AREA;
+ UINT32 SD_CARD_TYPE: 16;
+ UINT32 Reserved2: 13;
+ UINT32 SECURED_MODE: 1;
+ UINT32 DAT_BUS_WIDTH: 2;
+} SD_STATUS_REG;
+
+typedef struct {
+ UINT8 Reserved0[34];
+ UINT16 Group1BusyStatus;
+ UINT16 Group2BusyStatus;
+ UINT16 Group3BusyStatus;
+ UINT16 Group4BusyStatus;
+ UINT16 Group5BusyStatus;
+ UINT16 Group6BusyStatus;
+ UINT8 DataStructureVersion;
+ UINT8 Group21Status;
+ UINT8 Group43Status;
+ UINT8 Group65Status;
+ UINT16 Group1Function;
+ UINT16 Group2Function;
+ UINT16 Group3Function;
+ UINT16 Group4Function;
+ UINT16 Group5Function;
+ UINT16 Group6Function;
+ UINT16 MaxCurrent;
+} SWITCH_STATUS;
+
+#pragma pack()
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IosfSbDefinitions.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IosfSbDefinitions.h new file mode 100644 index 0000000000..ff65411d81 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/IosfSbDefinitions.h @@ -0,0 +1,44 @@ +/** @file
+ General IOSF-SB structure and register definitions.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IOSF_SB_DEFINITIONS_H_
+#define _IOSF_SB_DEFINITIONS_H_
+
+///
+/// Message Bus Registers
+///
+#define MC_MCR 0x000000D0 // Cunit Message Control Register
+#define MC_MDR 0x000000D4 // Cunit Message Data Register
+#define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension
+#define MC_MCRXX 0x000000DC // Cunit Message Control Register Extension 2
+
+///
+/// Message Bus API
+///
+#define MSG_BUS_ENABLED 0x000000F0
+#define MSGBUS_MASKHI 0xFFFFFF00
+#define MSGBUS_MASKLO 0x000000FF
+#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
+
+typedef struct _PCH_MSG_BUS_TABLE_STRUCT {
+ UINT8 PortId;
+ UINT32 Address;
+ UINT32 AndMask;
+ UINT32 OrMask;
+ UINT8 ReadOpCode;
+ UINT8 WriteOpCode;
+} PCH_MSG_BUS_TABLE_STRUCT;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h new file mode 100644 index 0000000000..7f68a3b5af --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h @@ -0,0 +1,302 @@ +/** @file
+ Definitions for the Driver Library
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DRIVER_LIB_H
+#define _DRIVER_LIB_H
+
+//------------------------------------------------------------------------------
+// Specify the header files
+//------------------------------------------------------------------------------
+
+#include <Uefi.h>
+
+#include <IndustryStandard/Pci.h>
+
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciIo.h>
+
+//------------------------------------------------------------------------------
+// Data Types
+//------------------------------------------------------------------------------
+
+/**
+ PCI device information
+**/
+#pragma pack(1)
+typedef struct
+{
+ UINT16 VendorID; ///< PCI-SIG <a href="http://www.pcisig.com/membership/vid_search/">vendor identification</a>
+ UINT16 DeviceID; ///< Vendor specific device identification
+ UINT8 Revision; ///< Hardware revision
+ UINT8 ProgIf; ///< Programming interface
+ UINT8 SubClass; ///< Device subclass
+ UINT8 Class; ///< Class of device defined by <a href="http://www.pcisig.com/specifications/conventional/conventional_pci">PCI 2.2 Specification</a>
+} DL_PCI_INFO;
+#pragma pack()
+
+/**
+ Driver library control structure definition
+**/
+typedef struct
+{
+ //
+ // Component Name(2) Protocol support
+ //
+ CONST EFI_COMPONENT_NAME_PROTOCOL * pComponentNameProtocol; ///< Address of component name protocol
+ CONST EFI_COMPONENT_NAME2_PROTOCOL * pComponentName2Protocol; ///< Address of component name 2 protocol
+ CONST EFI_UNICODE_STRING_TABLE * pControllerNameStringTable; ///< String table for ::DlGetControllerName
+ CONST EFI_UNICODE_STRING_TABLE * pDriverNameStringTable; ///< String table for ::DlGetDriverName
+
+ //
+ // Driver Binding Protocol support
+ //
+ EFI_DRIVER_BINDING_PROTOCOL * pDriverBindingProtocol; ///< Address of driver binding protocol
+
+ //
+ // Loaded Image Protocol support
+ //
+ EFI_IMAGE_UNLOAD pfnUnload; ///< Driver unload routine
+} DL_DRIVER_LIB;
+
+//------------------------------------------------------------------------------
+// Globals
+//------------------------------------------------------------------------------
+
+extern CONST DL_DRIVER_LIB mDriverLib; ///< Driver library control structure
+extern EFI_GUID * mpDriverProtocol; ///< Driver protocol GUID attached to the controller handle
+
+//------------------------------------------------------------------------------
+// Component Name(2) Protocol API
+//------------------------------------------------------------------------------
+
+/**
+ Locate a matching ACPI device path node
+
+ This routine walks the device path attached to the ControllerHandle
+ and determines if the last (non-end) device path node is an
+ ACPI_HID_DEVICE_PATH node and if the CID or _CIDSTR values
+ match the specified values.
+
+ @param[in] CompatibleIdentification The value to match against the CID
+ value in the ACPI_HID_DEVICE_PATH
+ node. This value must be zero when
+ the CompatibleIdentification
+ value is not NULL.
+ @param[in] CompatibleIdentificationString This value is specified as NULL
+ when the CompatibleIdentification
+ value is non-zero. When the
+ CompatibleIdentification value is
+ zero (0), this value should point
+ to a zero terminated charater
+ string value.
+
+ @return When the ACPI device path node is found, this routine
+ returns the pointer to the ACPI_HID_DEVICE_PATH node.
+ Otherwise when the device path is not found this routine
+ returns NULL.
+
+**/
+CONST ACPI_HID_DEVICE_PATH *
+EFIAPI
+DlAcpiFindDeviceWithMatchingCid (
+ EFI_HANDLE ControllerHandle,
+ UINTN CompatibleIdentification,
+ CONST CHAR8 * CompatibleIdentificationString OPTIONAL
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param[in] pThis A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+ @param[in] ChildHandle The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+ @param[in] pLanguage A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 3066 or ISO 639-2 language code format.
+ @param[out] ppControllerName A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DlGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL * pThis,
+ IN EFI_HANDLE ControllerHandle,
+ IN OPTIONAL EFI_HANDLE ChildHandle,
+ IN CHAR8 * pLanguage,
+ OUT CHAR16 ** ppControllerName
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param[in] pThis A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] pLanguage A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 3066 or ISO 639-2 language code format.
+ @param[out] ppDriverName A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DlGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL * pThis,
+ IN CHAR8 * pLanguage,
+ OUT CHAR16 ** ppDriverName
+ );
+
+//------------------------------------------------------------------------------
+// Loaded Image Protocol Support
+//------------------------------------------------------------------------------
+
+/**
+Common driver entry point
+
+ @param[in] ImageHandle Handle for the image
+ @param[in] pSystemTable Address of the system table.
+
+ @retval EFI_SUCCESS Image successfully loaded.
+
+**/
+EFI_STATUS
+EFIAPI
+DlEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * pSystemTable
+ );
+
+/**
+ Driver unload routine
+
+ @param[in] ImageHandle Handle for the image.
+
+ @retval EFI_SUCCESS Image may be unloaded
+
+**/
+EFI_STATUS
+EFIAPI
+DlDriverUnload (
+ IN EFI_HANDLE ImageHandle
+ );
+
+//------------------------------------------------------------------------------
+// PCI Support
+//------------------------------------------------------------------------------
+
+/**
+ Read PCI device information
+
+ This routine fills in the ::DL_PCI_INFO structure with the data
+ from configuration space.
+
+ @param[in] Controller Handle for the controller.
+ @param[in] DriverBindingHandle Handle for binding protocols.
+ @param[in] Attributes Attributes for OpenProtocol
+ @param[in] pPciInfo Address of a ::DL_PCI_INFO structure.
+ @param[out] ppPciIo Optional address to receive the EFI_PCI_IO_PROTCOL,
+ The caller must close the PCI I/O protocol if this
+ address is not NULL.
+
+ @retval EFI_SUCCESS The structure was initialized.
+
+**/
+EFI_STATUS
+DlPciInfo (
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE DriverBindingHandle,
+ IN UINT32 Attributes,
+ IN DL_PCI_INFO * pPciInfo,
+ OUT EFI_PCI_IO_PROTOCOL ** ppPciIo
+ );
+
+//------------------------------------------------------------------------------
+
+#endif // _DRIVER_LIB_H
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h new file mode 100644 index 0000000000..0adefa37b9 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h @@ -0,0 +1,52 @@ +/** @file
+ Header file for the Dxe Runtime PCI Express library.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+#define _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+
+//
+// Function prototypes
+//
+
+/**
+ Constructor for Pci library. Register VirtualAddressNotifyEvent() notify function
+ It will ASSERT() if that operation fails
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+PciLibConstructor (
+ VOID
+ );
+
+/**
+ Register memory space
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If SmPciLibAddressMapIndex) > PCI_LIB_ADDRESS_MAP_MAX_ITEM, then ASSERT().
+
+ @param[in] Address Starting address of the memory space
+ @param[in] Length Length of the memory space
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+PciLibRegisterMemory (
+ IN UINTN Address,
+ IN UINTN Length
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h new file mode 100644 index 0000000000..2e1b60ed95 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h @@ -0,0 +1,1092 @@ +/** @file
+ Library for GPIO Pin Programming.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <PiPei.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBaseAddresses.h>
+#include "PchAccess.h"
+#include <Library/TimerLib.h>
+#include <Library/PchPlatformLib.h>
+
+#define SD_MMIO_TIMEOUT 5
+#define HOST_CONTROL_1_REGISTER 0x28
+#define SD_POWER_CONTROL_REGISTER 0x29
+
+#define INVALID_COMMUNITY 0x01
+#define CFIO_COMMUNITY_NORTH 0x01
+#define CFIO_COMMUNITY_EAST 0x02
+#define CFIO_COMMUNITY_SOUTH_EAST 0x03
+#define CFIO_COMMUNITY_SOUTH_WEST 0x04
+
+// PAD registers offsets
+#define GPIO_MMIO_OFFSET_SW 0x0000
+#define GPIO_MMIO_OFFSET_N 0x8000
+#define GPIO_MMIO_OFFSET_E 0x10000
+#define GPIO_MMIO_OFFSET_SE 0x18000
+#define GPIO_MMIO_OFFSET_VIRT 0x20000
+
+#define CHV_GPIO_PAD_CONF0_OFFSET 0x0
+#define CHV_GPIO_PAD_CONF1_OFFSET 0x4
+#define CHV_GPIO_WAKE_REG0_BITS 0x20
+
+#define LOW 0
+#define HIGH 1
+#define MASK_WAKE 0
+#define UNMASK_WAKE 1
+
+// Families registers offsets
+#define GPIO_FAMILY_CONF_REGS_OFF 0x4400
+#define GPIO_FAMILY_CONF_REGS_SIZE 0x400
+#define GPIO_REGS_SIZE 8
+
+#define RCOMP_CONTROl_REG 0x0
+#define RCOMP_OFFSET_REG 0x4
+#define RCOMP_OVERRIDE_REG 0x8
+#define RCOMP_VALUE_REG 0xC
+#define FAMILY_RCOMP_CONFIG_REG 0x10
+#define FAMILY_CONFIG_REG 0x14
+
+// GPIO Security registers offset
+#define GPIO_READ_ACCESS_POLICY_REG 0x0000
+#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100
+#define GPIO_WAKE_STATUS_REG 0x0200
+#define GPIO_WAKE_MASK_REG0 0x0280
+#define GPIO_WAKE_MASK_REG1 0x0284
+#define GPIO_INTERRUPT_STATUS 0x0300
+#define GPIO_INTERRUPT_MASK 0x0380
+#define GPE0A_STS_REG 0x20
+#define GPE0A_EN_REG 0x28
+#define ALT_GPIO_SMI_REG 0x38
+#define GPIO_ROUT_REG 0x58
+// Broad cast registers
+#define GPIO_FAMILY_BW_MASK_31_0 0x1000
+#define GPIO_FAMILY_BW_DATA_31_0 0x1004
+#define GPIO_FAMILY_BROADCAST_REG_MASK 0x1008
+#define GPIO_PAD_BW_DATA_31_0 0x4004
+#define GPIO_PAD_BROADCAST_REG_MASK_0 0x4008
+
+#define MAX_FAMILY_PAD_GPIO_NO 15
+#define FAMILY0_PAD_REGS_OFF 0x4400
+#define FAMILY_PAD_REGS_SIZE 0x400
+
+#define GPIO_PAD_MODE_MASK 0xFFF0FFFF
+#define GPIO_EN_MASK 0xFFFF7FFF
+#define PULLUP_OR_PULLDOWN_MASK 0xFF8FFFFF
+#define PULL_VALUE_MASK 0xFF8FFFFF
+#define GPIO_INV_RXTX_MASK 0xFFFFFF0F
+#define GPIO_INT_MASK 0x0FFFFFFF
+#define GPIO_INT_TYPE 0xFFFFFFF8
+
+#define GPIO_PAD_LOCK 0x80000000
+#define PULL_UP_EN 0x00800000
+#define GPIO_DIRECTION_EN 0x00008000
+#define GPIO_DIRECTION 0x00000700
+#define GPIO_TX_STATE 0x00000002
+
+#define GPIO_RETURN_FAIL 1
+#define GPIO_RETURN_PASS 0
+
+//PAD numbers
+#define PAD0 0x00
+#define PAD1 0x01
+
+//PAD Read or Write
+#define PAD_READ 0x00
+#define PAD_WRITE 0x01
+
+//PAD Lock Status
+#define LOCKED 0x01
+#define UNLOCKED 0x00
+
+//Pull Values
+#define PULL_1K 0x00100000
+#define PULL_5K 0x00200000
+#define PULL_20K 0x00400000
+
+#define NA 0xFF
+
+#pragma pack(1)
+typedef enum
+{
+ Native =0xff,
+ GPIO = 0, // Native, no need to set PAD_VALUE
+ GPO = 1, // GPI, input only in PAD_VALUE
+ GPI = 2, // GPO, output only in PAD_VALUE
+ HI_Z = 3,
+} GPIO_En;
+
+typedef enum
+{
+ LO = 0,
+ HI = 1,
+} GPO_D4;
+
+typedef enum
+{
+ F0 = 0,
+ F1 = 1,
+ F2 = 2,
+ F3 = 3
+} GPIO_FUNC_NUM;
+
+// Mapping to CONF0 bit 27:24
+// Note: Assume "Direct Irq En" is not set, unless specially notified
+typedef enum
+{
+ TRIG_ = 0,
+ TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
+ TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
+ TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
+ TRIG_Level_High= /*BIT3 |*/ BIT2 | BIT0, // Level High
+ TRIG_Level_Low = /*BIT3 |*/ BIT1 | BIT0, // Level Low
+} INT_TYPE;
+
+typedef enum
+{
+ P_NONE = 0, // Pull None
+ P_20K_L = 1, // Pull Down 20K
+ P_5K_L = 2, // Pull Down 5K
+ P_1K_L = 4, // Pull Down 1K
+ P_20K_H = 9, // Pull Up 20K
+ P_5K_H = 10, // Pull Up 5K
+ P_1K_H = 12 // Pull Up 1K
+} PULL_TYPE;
+
+typedef enum
+{
+ _DISABLE = 0, // Disable
+ _ENABLE = 1, // Enable
+} PARKMODEENB;
+
+typedef enum
+{
+ VOLT_3_3 = 0, // Working on 3.3 Volts
+ VOLT_1_8 = 1, // Working on 1.8 Volts
+} VP18MODE;
+
+typedef enum
+{
+ DISABLE_HS = 0, // Disable high speed mode
+ ENABLE_HS = 1, // Enable high speed mode
+} HSMODE;
+
+typedef enum
+{
+ PULL_UP = 0, // On Die Termination Up
+ PULL_DOWN = 1, // On Die Termination Down
+} ODTUPDN;
+
+typedef enum
+{
+ DISABLE_OD =0, // On Die Termination Disable
+ ENABLE_OD =1, // On Die Termination Enable
+} ODTEN;
+
+typedef enum
+{
+ ONE_BIT = 1,
+ TWO_BIT = 3,
+ THREE_BIT = 7,
+ FOUR_BIT = 15,
+ FIVE_BIT = 31,
+ SIX_BIT = 63,
+ SEVEN_BIT = 127,
+ EIGHT_BIT = 255
+}BITS;
+
+typedef union {
+ UINT32 famCnf;
+ struct {
+ UINT32 CurrSrcStr : 3;
+ UINT32 reserve : 14;
+ UINT32 odpullEn : 1;
+ UINT32 odpulldir : 1;
+ UINT32 hsMode : 1;
+ UINT32 Reseve3 : 1;
+ UINT32 vpMode : 1;
+ UINT32 Reseve2 : 2;
+ UINT32 HYSCTL : 2;
+ UINT32 parkMode : 1;
+ UINT32 reseve1 : 5;
+ }r;
+} CONF_FAMILY;
+
+typedef enum
+{
+ M0 =0,
+ M1,
+ M2,
+ M3,
+ M4,
+ M5,
+ M6,
+ M7,
+ M8,
+ M9,
+ M10,
+ M11,
+ M12,
+ M13,
+ M14,
+ M15,
+} ModeList;
+
+typedef enum
+{
+ Line0 =0,
+ Line1 =1,
+ Line2 =2,
+ Line3 =3,
+ Line4 =4,
+ Line5 =5,
+ Line6 =6,
+ Line7 =7,
+ Line8 =8,
+ Line9 =9,
+ Line10 =10,
+ Line11 =11,
+ Line12 =12,
+ Line13 =13,
+ Line14 =14,
+ Line15 =15,
+} Int_Select;
+
+typedef enum
+{
+ INT_DIS =0,
+ Trig_Edge_Low =1,
+ Trig_Edge_High =2,
+ Trig_Edge_Both =3,
+ Trig_Level =4,
+} INT_Type;
+
+typedef enum
+{
+ glitch_Disable = 0,
+ En_EdgeDetect,
+ En_RX_Data,
+ En_Edge_RX_Data,
+} Glitch_Cfg;
+
+typedef enum
+{
+ Maskable,
+ NonMaskable,
+}mask;
+
+typedef enum
+{
+ NORTH = GPIO_MMIO_OFFSET_N,
+ EAST = GPIO_MMIO_OFFSET_E,
+ SOUTHWEST = GPIO_MMIO_OFFSET_SW,
+ SOUTHEAST = GPIO_MMIO_OFFSET_SE,
+ VIRTUAL = GPIO_MMIO_OFFSET_VIRT,
+} coms;
+
+typedef enum
+{
+ SMI = 1,
+ SCI = 2,
+} GPE_config;
+
+//
+// InvertRxTx 7:4
+// 0 - No Inversion
+// 1 - Inversion
+// [0] RX Enable
+// [1] TX Enable
+// [2] RX Data
+// [3] TX Data
+//
+typedef enum
+{
+ No_Inversion = 0,
+ Inv_RX_Enable = 0x1,
+ Inv_TX_Enable = 0x2,
+ Inv_RX_TX_Enable = 0x3,
+ Inv_RX_Data = 0x4,
+ Inv_RX_Data_TX_Enable = 0x6,
+ Inv_TX_Data = 0x8,
+} InvertRX_TX;
+
+typedef union {
+ UINT32 padCnf0;
+ struct {
+ UINT32 GPIORXState : 1; // 0 GPIO RX State (GPIORXState).
+ UINT32 GPIOTXState : 1; // 1 GPIO TX State (GPIOTXState).
+ UINT32 Reserved1 : 5; // 2-6 Reserved
+ UINT32 Gpio_Light_Mode : 1; // 7 GPIO Light Mode
+ UINT32 GPIOCfg : 3; // 8-10 GPIO Config (GPIOCfg).
+ UINT32 Reserved2 : 4; // 11-14 Reserved
+ UINT32 GPIOEn : 1; // 15 GPIO Enable (GPIOEn)
+ UINT32 Pmode : 4; // 16-19 Pad Mode (Pmode)
+ UINT32 Term : 4; // 20-23 Termination (Term)
+ UINT32 RXTXEnCfg : 2; // 24-25 RX/TX Enable Config (RXTXEnCfg)
+ UINT32 GFCfg : 2; // 26-27 Glitch Filter Config (GFCfg)
+ UINT32 IntSel : 4; // 28-31 Interrupt Select (IntSel)
+ }r;
+} CHV_CONF_PAD0;
+
+typedef union {
+ UINT32 padCnf1;
+ struct {
+ UINT32 IntWakeCfg : 3; // 0-2 Interrupt and Wake Configuration (IntWakeCfg).
+ UINT32 ODEn : 1; // 3 Open Drain Enable (ODEn).
+ UINT32 InvRXTX : 4; // 4-7 Invert RX TX (InvRXTX)
+ UINT32 Reserved : 2; // 8-9 Reserved.
+ UINT32 IOSTerm : 2; // 10-11 I/O Standby Termination (IOSTerm)
+ UINT32 IOSState : 4; // 12-15 I/O Standby State (IOSState)
+ UINT32 analogmuxen : 1; // 16 Analog Mux Enable (analogmuxen)
+ UINT32 ODTEN : 1; // 17 Reserved for On Die Termination Enable (ODTEN)
+ UINT32 ODTUPDN : 1; // 18 Reserved for On Die Termination Up/Down (ODTUPDN)
+ UINT32 HSMODE : 1; // 19 Reserved for High Speed mode (HSMODE)
+ UINT32 VP18Mode : 1; // 20 Reserved for 1.8 V Mode (VP18Mode)
+ UINT32 VP15MODE : 1; // 21 Reserved for 1.5V Mode (VP15MODE)
+ UINT32 CLKNENB : 1; // 22 Reserved for CLKNENB
+ UINT32 AZAMODE : 1; // 23 Reserved for AZAMODE
+ UINT32 HYSCTL : 2; // 24-25 Reserved for Hysteresis Control (HYSCTL)
+ UINT32 PARKMODEENB : 1; // 26 Reserved for Parkmode Enable Bar (PARKMODEENB)
+ UINT32 csen : 1; // 27 Current Source Enable (csen)
+ UINT32 svid_od_en : 1; // 28 SVID 1V Open Drain Mode (svid_1v_od_en)
+ UINT32 Reserved1 : 1; // 29 Reserved for Pad Configuration.
+ UINT32 PadRstCfg : 1; // 30 Pad Reset Config (PadRstCfg)
+ UINT32 CfgLock : 1; // 31 Configuration Lock (CfgLock).
+ }r;
+} CHV_CONF_PAD1;
+
+ #ifdef EFI_DEBUG
+ #define CHV_GPIO_PAD_CONF(pad_name, Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_Type, INT_S, Term_H_L, Open_Drain, Current_Source, Int_Mask, Glitch_Cfg, InvertRX_TX, WAKE_Mask,Wake_Mask_Bit, GPE, MMIO_Offset, Community ) { \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) | (((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0)), \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0)), \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0)), \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0)), Community, (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0, pad_name, ((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0))| (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))}
+ #else
+ #define CHV_GPIO_PAD_CONF(pad_name, Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_Type, INT_S, Term_H_L, Open_Drain, Current_Source, Int_Mask, Glitch_Cfg, InvertRX_TX, WAKE_Mask,Wake_Mask_Bit, GPE, MMIO_Offset, Community ) { \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) |(((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0)), \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0)), \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0)), \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0)), Community, (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0,((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0)) | (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))}
+ #endif
+
+#define CHV_GPIO_PAD_CONFG0(Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg) \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) |(((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0))
+
+#define CHV_GPIO_PAD_CONFG0_CHANGE(GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg) \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0))
+
+#define CHV_GPIO_PAD_CONFG1(INT_Type, Open_Drain, Current_Source, InvertRX_TX) \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0))
+#define CHV_GPIO_PAD_CONFG1_CHANGE(INT_Type, Open_Drain, Current_Source, InvertRX_TX) \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0))
+#define CHV_GPIO_PAD_MMIO(MMIO_Offset, Community) (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0
+#define CHV_GPIO_PAD_MISC(Int_Mask, WAKE_Mask,Wake_Mask_Bit, GPE) ((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0)) | (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))
+
+typedef union {
+ UINT32 micsData;
+ struct {
+ UINT32 GPE_ENABLE : 2; // 0 set if GPIO GPE is enable.
+ UINT32 wake_able : 1; // 2 set if GPIO Wake capable
+ UINT32 intr_mask : 1; // 3 set if GPIO interrupt masked
+ UINT32 Wake_Mask_Position : 8; // 4 set the GPIO wake mask bit position
+ }r;
+} CHV_PAD_MISC;
+
+typedef struct {
+ CHV_CONF_PAD0 padConfg0;
+ CHV_CONF_PAD0 padConfg0_changes;
+ CHV_CONF_PAD1 padConfg1;
+ CHV_CONF_PAD1 padConfg1_changes;
+ UINT32 Community;
+ UINT32 MMIO_ADDRESS;
+#ifdef EFI_DEBUG
+ CHAR16 *pad_name; // GPIO Pin Name for debug purpose
+#endif
+ CHV_PAD_MISC PAD_MISC;
+} CHV_GPIO_PAD_INIT;
+
+typedef union {
+ UINT32 mics1;
+ struct {
+ UINT32 RCOMP_ENABLE : 1; // 0 set if rcomp is enable.
+ }r;
+} CHV_FAMILY_MISC;
+
+typedef struct {
+ CONF_FAMILY confg;
+ CONF_FAMILY confg_change;
+ CHV_FAMILY_MISC family_misc;
+ UINT32 mmioAddr;
+#ifdef EFI_DEBUG
+ CHAR16 *family_name; // GPIO Family Name for debug purpose
+#endif
+} GPIO_CONF_FAMILY_INIT;
+
+typedef union {
+ UINT32 wake_;
+ struct {
+ UINT32 GPIO_ : 32; // 1 set if GPIO 1 wake enable.
+ }r;
+} GPIO_WAKE;
+
+typedef union {
+ UINT32 intr_;
+ struct {
+ UINT32 GPIO_ : 32; // 1 set if GPIO 1 wake enable.
+ }r;
+} GPIO_INTERRUPT;
+
+typedef union {
+ UINT32 rout_;
+ struct {
+ UINT32 GPIO_ROUT : 32;
+ }r;
+} GPIO_ROUT;
+
+typedef union {
+ UINT32 gpe0a_;
+ struct {
+ UINT32 GPIO_EN : 32; //Expand the structure if required.
+ }r;
+} GPE0a_EN;
+
+typedef union {
+ UINT32 smi_;
+ struct {
+ UINT32 GPIO_SMI : 32; //Expand the structure if required.
+ }r;
+} ALT_GPIO_SMI;
+
+//PAD_CONF0_MMIO_ADDR = IOBASE + COMMUNITY_BASE + 0x4400+0x400*Family# + 0x8*Pad#
+ #ifdef EFI_DEBUG
+ #define CHV_GPIO_FAMILY_INIT(family_name, PARKMODEENB, HYSCTL, VP18MODE, HSMODE, ODTUPDN, ODTEN, CurrSrcStr, rComp, familyNo, Community) { ((((PARKMODEENB) != NA) ? (UINT32)PARKMODEENB << 26 : 0) | (((HYSCTL) != NA) ? HYSCTL << 24 : 0) | (((VP18MODE) != NA) ? VP18MODE << 21 : 0) | (((HSMODE) != NA) ? HSMODE << 19 : 0) | (((ODTUPDN) != NA) ? ODTUPDN << 18 : 0) | (((ODTEN) != NA) ? ODTEN << 17 : 0) | (CurrSrcStr)), \
+ ((((PARKMODEENB) != NA) ? (UINT32)ONE_BIT << 26 : 0) | (((HYSCTL) != NA) ? TWO_BIT << 24 : 0) | (((VP18MODE) != NA) ? ONE_BIT << 21 : 0) | (((HSMODE) != NA) ? ONE_BIT << 19 : 0) | (((ODTUPDN) != NA) ? ONE_BIT << 18 : 0) | (((ODTEN) != NA) ? ONE_BIT << 17 : 0) | (THREE_BIT)), \
+ ((rComp == ENABLE) ? 1 : 0), (familyNo != NA) ? (IO_BASE_ADDRESS+Community +(0x80*familyNo)+0x1080) : 0, family_name }
+ #else
+ #define CHV_GPIO_FAMILY_INIT(family_name, PARKMODEENB, HYSCTL, VP18MODE, HSMODE, ODTUPDN, ODTEN, CurrSrcStr, rComp, familyNo, Community) { ((((PARKMODEENB) != NA) ? (UINT32)PARKMODEENB << 26 : 0) | (((HYSCTL) != NA) ? HYSCTL << 24 : 0) | (((VP18MODE) != NA) ? VP18MODE << 21 : 0) | (((HSMODE) != NA) ? HSMODE << 19 : 0) | (((ODTUPDN) != NA) ? ODTUPDN << 18 : 0) | (((ODTEN) != NA) ? ODTEN << 17 : 0) | (CurrSrcStr)), \
+ ((((PARKMODEENB) != NA) ? (UINT32)ONE_BIT << 26 : 0) | (((HYSCTL) != NA) ? TWO_BIT << 24 : 0) | (((VP18MODE) != NA) ? ONE_BIT << 21 : 0) | (((HSMODE) != NA) ? ONE_BIT << 19 : 0) | (((ODTUPDN) != NA) ? ONE_BIT << 18 : 0) | (((ODTEN) != NA) ? ONE_BIT << 17 : 0) | (THREE_BIT)), \
+ ((rComp == ENABLE) ? 1 : 0), (familyNo != NA) ? (IO_BASE_ADDRESS+Community +(0x80*familyNo)+0x1080) : 0 }
+ #endif
+
+//family_rcomp = IOBASE + COMMUNITY_BASE + 0x1080 + 0x20*family + rcompOffset
+
+/*
+ * RCOMP REGISTERS
+ */
+
+typedef union {
+ UINT32 rcomCtrl;
+ struct {
+ UINT32 InitCalValN : 8; // 0-7 Initial Pull Down Value (InitCalValN)
+ UINT32 InitCalValP : 8; // 8-15 Initial Pull Up Value (InitCalValP)
+ UINT32 RFSMStopCyc : 4; // 16-19 RCOMP FSM Stop Cycles (RFSMStopCyc)
+ UINT32 RFSMStop : 2; // 20-21 RCOMP FSM Stop Condition (RFSMStop)
+ UINT32 ircintclkperiod : 2; // 22-23 IRC Internal Clock Period (ircintclkperiod)
+ UINT32 ircfreq_select : 2; // 24-25 IRCCLK Frequency Select (ircfreq_select)
+ UINT32 reserved : 3; // 26-28 reserved (reserved)
+ UINT32 chicken_bit : 1; // 29 RCOMP FSM Binary Chicken Bit (chicken_bit)
+ UINT32 RcalStart : 1; // 30 RCOMP Calibration Start (RcalStart)
+ UINT32 RFSMEn : 1; // 31 RCOMP FSM Enable (RFSMEn)
+ }r;
+} CHV_RCOMP_CTRL;
+
+typedef union {
+ UINT32 rcompOffset;
+ struct {
+ UINT32 OffNStrVal : 5; // 0-4 Pull Down Offset Strength Value (OffNStrVal).
+ UINT32 OffNStrSign : 1; // 5 Pull Down Offset Strength Sign (OffNStrSign).
+ UINT32 Reserved : 2; // 6-7 Reserved
+ UINT32 OffPStrVal : 5; // 8-12 Pull Up Offset Strength Value (OffPStrVal).
+ UINT32 OffPStrSign : 1; // 13 Pull Up Offset Strength Sign (OffPStrSign)
+ UINT32 Reserved1 : 2; // 14-15 Reserved
+ UINT32 OffNSlewVal : 4; // 16-19 Pull Down Slew Offset (OffNSlewVal)
+ UINT32 OffNSlewSign : 1; // 20 Pull Down Offset Slew Sign (OffNSlewSign)
+ UINT32 Reserved3 : 3; // 21-23 Reserved
+ UINT32 OffPSlewVal : 4; // 24-27 Pull Up Slew Offset (OffPSlewVal)
+ UINT32 OffPSlewSign : 1; // 28 Pull Up Offset Slew Sign (OffPSlewSign)
+ UINT32 Reserved4 : 3; // 29-31 Reserved
+ }r;
+} CHV_RCOMP_OFFSET;
+
+typedef union {
+ UINT32 rcomOver;
+ struct {
+ UINT32 OvrNStrVal : 8; // 0-7 Override Pull Down Strength Value (OvrNStrVal).
+ UINT32 OvrPStrVal : 8; // 8-15 Override Pull Up Strength Value (OvrPStrVal).
+ UINT32 OvrNSlewVal : 4; // 16-19 Override N Slew Value (OvrNSlewVal).
+ UINT32 OvrPSlewVal : 2; // 20-23 Override P Slew Value (OvrPSlewVal).
+ UINT32 Reserved : 6; // 24-29 Reserved.
+ UINT32 OvrLoad : 1; // 30 Override Load (OvrLoad)
+ UINT32 OvrREn : 1; // 31 Override RCOMP Enable (OvrREn)
+ }r;
+} CHV_RCOMP_OVERRIDE;
+
+typedef union {
+ UINT32 rcompValue;
+ struct {
+ UINT32 NStrVal : 8; // 0-7 Pull Down Strength Value (NStrVal).
+ UINT32 PStrVal : 8; // 8-15 Pull Up Strength Value (PStrVal).
+ UINT32 NSlewVal : 4; // 16-19 N Slew Value (NSlewVal)
+ UINT32 PSlewVal : 4; // 20-23 P Slew Value (PSlewVal)
+ UINT32 Reserved : 8; // 24-31 Reserved
+ }r;
+} CHV_RCOMP_VALUE;
+
+typedef union {
+ UINT32 secSAI;
+ struct {
+ UINT32 IA_Untrusted : 1;
+ UINT32 IA_Ucode : 1;
+ UINT32 IA_Smm : 1;
+ UINT32 ucode_NPP : 1;
+ UINT32 IA_Boot : 1;
+ UINT32 IA_Untrusted_5 : 1;
+ UINT32 IA_Untrusted_6 : 1;
+ UINT32 IA_XUcode : 1;
+ UINT32 Punit_Trusted : 1;
+ UINT32 SEC_Trusted : 1;
+ UINT32 Drm : 1;
+ UINT32 FuseStrap_Puller : 1;
+ UINT32 Fuse_Provider : 1;
+ UINT32 Strap_Provider : 1;
+ UINT32 DFX_Untrusted : 1;
+ UINT32 DFX_Trusted : 1;
+ UINT32 PMC_Trusted : 1;
+ UINT32 DRNG : 1;
+ UINT32 ISH_t : 1;
+ UINT32 Device_Untrusted_19 : 1;
+ UINT32 Device_Untrusted_20 : 1;
+ UINT32 Device_Untrusted_21 : 1;
+ UINT32 Device_Untrusted_22 : 1;
+ UINT32 Device_Untrusted_23 : 1;
+ UINT32 Device_Untrusted_24 : 1;
+ UINT32 Device_Untrusted_25 : 1;
+ UINT32 Device_Untrusted_26 : 1;
+ UINT32 Device_Untrusted_27 : 1;
+ UINT32 Device_Untrusted_28 : 1;
+ UINT32 Device_Untrusted_29 : 1;
+ UINT32 Device_Untrusted_30 : 1;
+ UINT32 Device_Untrusted : 1;
+ }r;
+} policy_access_reg;
+
+typedef union {
+ UINT32 familyRcompCnfg;
+ struct {
+ UINT32 NSlewVal : 4; // 0-3 N Slew Value (NSlewVal).
+ UINT32 PSlewVal : 4; // 4-7 P Slew Value (PSlewVal).
+ UINT32 NStaticLegEn : 1; // 8 N Static Leg Enable (NStaticLegEn)
+ UINT32 PStaticLegEn : 1; // 9 P Static Leg Enable (PStaticLegEn)
+ UINT32 reserved : 6; // 10-15 reserved (reserved)
+ UINT32 NStrVal : 8; // 16-23 Pull Down Strength Value (NStrVal)
+ UINT32 PStrVal : 8; // 24-31 Pull Up Strength Value (PStrVal)
+ }r;
+} CHV_FAMILY_RCOMP_CNFG;
+
+typedef struct {
+ UINT32 Offset;
+ policy_access_reg val_;
+ UINT32 Community;
+#ifdef EFI_DEBUG
+ CHAR16 *family_name; // GPIO Family Name for debug purpose
+#endif
+} GPIO_SAI_INIT;
+
+#ifdef EFI_DEBUG
+ #define CHV_GPIO_SAI_INIT(family_name, Offset, value, Community) { Offset, value, Community, family_name}
+#else
+ #define CHV_GPIO_SAI_INIT(family_name, Offset, value, Community) { Offset, value, Community}
+#endif
+
+typedef struct {
+
+#ifdef EFI_DEBUG
+ CHAR16 *pad_name; // GPIO Pin Name for debug purpose
+#endif
+
+ GPIO_En usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
+ GPO_D4 gpod4; // GPO default value
+ GPIO_FUNC_NUM func; // Function Number (F0~F7)
+ INT_TYPE int_type; // Edge or Level trigger, low or high active
+ PULL_TYPE pull; // Pull Up or Down
+ UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
+} GPIO_CONF_PAD_INIT;
+
+#ifdef EFI_DEBUG
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_ ## int_type, P_ ## pull, offset}
+#else
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_ ## int_type, P_ ## pull, offset}
+#endif
+
+typedef union {
+ UINT32 dw;
+ struct {
+ UINT32 Func_Pin_Mux : 3; // 0:2 Function of CFIO selection
+ UINT32 ipslew : 2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
+ UINT32 inslew : 2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
+ UINT32 Pull_assign : 2; // 7:8 Pull assignment
+ UINT32 Pull_strength : 2; // 9:10 Pull strength
+ UINT32 Bypass_flop : 1; // 11 Bypass flop
+ UINT32 Filter_en : 1; // 12 Filter Enable
+ UINT32 Hist_ctrl : 2; // 13:14 hysteresis control
+ UINT32 Hist_enb : 1; // 15 Hysteresis enable, active low
+ UINT32 Delay_line : 6; // 16:21 Delay line values - Delay values for input or output
+ UINT32 Reserved : 3; // 22:24 Reserved
+ UINT32 TPE : 1; // 25 Trigger Positive Edge Enable
+ UINT32 TNE : 1; // 26 Trigger Negative Edge Enable
+ UINT32 Reserved2 : 3; // 27:29 Reserved
+ UINT32 i1p5sel : 1; // 30
+ UINT32 IODEN : 1; // 31 : Open Drain enable. Active high
+ } r;
+} PAD_CONF0;
+
+typedef union {
+ UINT32 dw;
+ struct {
+ UINT32 pad_val : 1; // 0 These registers are implemented as dual read/write with dedicated storage each.
+ UINT32 ioutenb : 1; // 1 output enable
+ UINT32 iinenb : 1; // 2 input enable
+ UINT32 Reserved : 29; // 3:31 Reserved
+ }r;
+} PAD_VAL;
+
+#pragma pack()
+
+#define CONF_MMIO_ADDRESS(CommunityOffset, GpioNumber, PadXOffset) (IO_BASE_ADDRESS + CommunityOffset + FAMILY0_PAD_REGS_OFF + \
+ (FAMILY_PAD_REGS_SIZE * (GpioNumber / MAX_FAMILY_PAD_GPIO_NO)) + \
+ (GPIO_REGS_SIZE * (GpioNumber % MAX_FAMILY_PAD_GPIO_NO)) + PadXOffset)
+
+/**
+ Set GPIO PAD control 0 and 1 registers for N/E/SW/SE GPIO communities
+
+ @param[in] GPIOTable_Index Begin Pin Number to start configuring in GPIO_Conf_Data table
+ @param[in] GPIOTable_NumberofPins Number of Pins to configure in GPIO_Conf_Data table
+ @param[in] Gpio_Conf_Data GPIO_CONF_PAD_INIT data array
+
+**/
+VOID
+InternalGpioPADConfig (
+ IN UINT32 Gpio_Pin_Begin_Num,
+ IN UINT32 Gpio_Pin_Size,
+ CHV_GPIO_PAD_INIT *Gpio_Conf_Data
+ );
+
+/**
+ Set GPIO families register configuration for N/E/SW/SE GPIO communities
+
+ @param[in] Gpio_Families_Mmio_Offset GPIO_MMIO_OFFSET_SW / GPIO_MMIO_OFFSET_N / GPIO_MMIO_OFFSET_E / GPIO_MMIO_OFFSET_SE.
+ @param[in] Gpio_Communities_Num Families numbers to config for GPIO communities.
+ @param[in] Gpio_Families_Data GPIO_CONF_FAMILY_INIT data array for each GPIO family.
+
+**/
+VOID
+InternalGpioFamiliesConfig (
+ IN UINT32 Gpio_Families_Mmio_Offset,
+ IN UINT32 Gpio_Communities_Num,
+ GPIO_CONF_FAMILY_INIT *Gpio_Families_Data
+ );
+
+/**
+ Set GPIO PAD SAI registers for N/E/SW/SE GPIO communities
+
+ @param[in] SAI_Conf_Data GPIO_SAI_INIT data array for each GPIO communities.
+ @param[in] UINT32 Size of the table
+**/
+VOID
+SaiSettingOfGpioFamilies (
+ GPIO_SAI_INIT *SAI_Conf_Data,
+ UINT32 familySize
+ );
+
+/**
+ Function to get the Pin Pad0 MMIO offset
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number.
+
+ @retval UINT32 Pin Mmio Offset
+**/
+UINT32
+EFIAPI
+GetPinMmioOffset (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to Read/Write Pad0 or Pad1 control register of given Pin from commnity
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Padx This can be either Pad0 or Pad1, 0 - PAD0
+ @param[in] ReadOrWrite 0 - Read and 1 - Write of Padx
+ @param[in] PadxValue Pinter to hold the Read/Write value.
+
+**/
+VOID
+ReadWritePadXConf (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Padx,
+ IN BOOLEAN ReadOrWrite,
+ IN OUT UINT32 *PadxValue
+ );
+
+/**
+ Function to configure pin to any one of GPIO fucntionalities for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Direction Gpio direction
+ GPIO - 0
+ GPO - 1
+ GPI - 2
+ HI-Z - 3
+ @param[in] Value Configure HIGH or LOW for GPO (Tx)
+ 1-HIGH,0-Low
+**/
+VOID
+SetGPIOMode (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT8 Direction,
+ IN BOOLEAN Value
+ );
+
+/**
+ Function to get the GPIO direction configuration for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval UINT8 The value for GPIO directin
+ GPIO-0
+ GPO-1
+ GPI-2
+ HI-Z-3
+**/
+UINT8
+EFIAPI
+GetGPIOMode (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure the specified pin to any one of native mode
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Mode Native Mode - M0, M1, .., M15
+
+ @retval Boolean 0 - successful native mode configuration,1 - unsuccessful, Pad Could be locked
+**/
+BOOLEAN
+EFIAPI
+SetNativeMode (
+ IN UINT32 Community,
+ IN UINT32 PinOffset,
+ IN UINT8 Mode
+ );
+
+/**
+ Function to get the native mode number
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Mode Native Mode M0-0, M1-11, .., M15-15
+ Failure - Value 0xFF.
+**/
+UINT8
+EFIAPI
+GetNativeMode (
+ IN UINT32 Community,
+ IN UINT32 PinOffset
+ );
+
+/**
+ Function to configure GPO Tx State for specified pin in the community.
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Value 1-HIGH, 0-LOW
+
+**/
+VOID
+GPIOSetTXValue (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Value
+ );
+
+/**
+ Function to get the GPO Tx state of specified pin in the community.
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Boolean 1-HIGH,0-LOW
+**/
+BOOLEAN
+EFIAPI
+GPIOGetTXValue (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure pin to any one of GPIO fucntionalities for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Pullup Enable pullup or pulldown
+ 1-Pull Up
+ 0-Pull Down
+ @param[in] Value Pull value
+ 1-1K
+ 2-5K
+ 4-20K
+ @retval Boolean 0-Successful termination configured, 1-Unsuccessful could be due to unsupported value.
+**/
+BOOLEAN
+EFIAPI
+GPIOSetPadTerm (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN PullUp,
+ IN UINT8 Value
+ );
+
+/**
+ Function to current pin termantaion value of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] *PullValue Pull value
+ 1 - 1K
+ 2 - 5K
+ 4 - 20K
+
+ @retval Boolean 1-Pull Up,0-Pull Down
+**/
+BOOLEAN
+GPIOGetPadTerm (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN OUT UINT8 *PullValue
+ );
+
+/**
+ Function to Configure the Invert Rx/Tx Data and Rx/Tx Enable of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] InvRxTxValue 0=No Inversion, 1=Inversion Enabled
+ [0] RX Enable
+ [1] TX Enable
+ [2] RX Data
+ [3] TX Data
+
+**/
+VOID
+GPIOSetInvRxTx (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT8 InvRxTxValue
+ );
+
+/**
+ Function to get current the Invert Rx/Tx Data and Rx/Tx Enable configuration of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval InvRxTxValue 0-No Inversion, 1-Inversion Enabled
+ [0] RX Enable
+ [1] TX Enable
+ [2] RX Data
+ [3] TX Data
+**/
+UINT8
+EFIAPI
+GPIOGetInvRxTx (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure the interrupt line and type for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] LineNum 0 - Interrupt Line 0
+ 1 - Interrupt Line 1
+
+ 15 = Interrupt Line 15
+ @param[in] Type Type of interrrupt
+ 0 = Interrupt/Wake Disable (Disabled and no Pad State toggles trigger the Wake/Interrupt logic)
+ 1 = Falling Edge Detect Interrupt/Wake
+ 2 = Rising Edge Detect Interrupt/Wake
+ 3 = Falling or Rising Edge Detect Interrupt/Wake
+ 4 = Level Interrupt/Wake (Bypass edge detect logic and Pad state is directly toggling the Wake/Interrupt logic)
+**/
+VOID
+ConfigureGpioInt (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT32 LineNum,
+ IN UINT8 Type
+ );
+
+/**
+ Function to lock the pad of specified Pin
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Enable 1-Lock,0-UnLock
+
+**/
+VOID
+LockUnlockGPIOPin (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Enable
+ );
+
+/**
+ Function to Read the Pad Write Lock status
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Boolean 1-Locked,0-Unlocked
+**/
+BOOLEAN
+EFIAPI
+GetPinPadLockStatus (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to Get the current interrupt configure for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] LineNum Interrupt line number refer Int_Select from PlatfromInfo.h
+ 0 = Interrupt Line 0
+ 1 = Interrupt Line 1
+
+ 15 = Interrupt Line 15
+ @param[out] Type Type of interrrupt
+ 0 = Interrupt/Wake Disable (Disabled and no Pad State toggles trigger the Wake/Interrupt logic)
+ 1 = Falling Edge Detect Interrupt/Wake
+ 2 = Rising Edge Detect Interrupt/Wake
+ 3 = Falling or Rising Edge Detect Interrupt/Wake
+ 4 = Level Interrupt/Wake (Bypass edge detect logic and Pad state is directly toggling the Wake/Interrupt logic)
+ 4> Unsupported value
+**/
+VOID
+GetGpioIntConfig (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN OUT UINT8 *LineNum,
+ IN OUT UINT8 *IntType
+ );
+
+/**
+ Set particular GPIO pin as SMI / SCI
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] IntSel Selected interrupt number to rout
+ @param[in] Type Configure SMI / SCI ?
+
+**/
+VOID
+GpioGPEConfig (
+ IN UINT32 Community,
+ IN UINT32 IntSel,
+ IN UINT8 Type
+ );
+
+/**
+ Set particular GPIO Wake Cable
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] CHV_PAD_MISC Wake capable mask details
+**/
+VOID
+ConfigureGPIOWake (
+ IN UINT32 community,
+ IN CHV_PAD_MISC Pad_misc
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h new file mode 100644 index 0000000000..c0937c8cf1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h @@ -0,0 +1,272 @@ +/** @file
+ Header file for PCH PCI Express helpers library
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PCI_EXPRESS_HELPERS_LIB_H_
+#define _PCH_PCI_EXPRESS_HELPERS_LIB_H_
+
+//
+// Function prototypes
+//
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 = PCI Power Management Interface
+ 0x04 = Slot Identification
+ 0x05 = MSI Capability
+ 0x10 = PCI Express Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieFindCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 = Advanced Error Rreporting Capability
+ 0x0002 = Virtual Channel Capability
+ 0x0003 = Device Serial Number Capability
+ 0x0004 = Power Budgeting Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieFindExtendedCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ );
+
+/**
+ Map a TC to VC0 for port and endpoint
+
+ @param[in] Bus1 The bus number of the port
+ @param[in] Device1 The device number of the port
+ @param[in] Function1 The function number of the port
+ @param[in] Bus2 The bus number of the endpoint
+ @param[in] Device2 The device number of the endpoint
+ @param[in] TCx The TC number
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieMapTcxVc0 (
+ IN UINT8 Bus1,
+ IN UINT8 Device1,
+ IN UINT8 Function1,
+ IN UINT8 Bus2,
+ IN UINT8 Device2,
+ IN UINT8 TCx
+ );
+
+/**
+ Set Common clock to Root port and Endpoint PCI device
+
+ @param[in] Bus1 Root port Pci Bus Number
+ @param[in] Device1 Root port Pci Device Number
+ @param[in] Function1 Root port Pci Function Number
+ @param[in] Bus2 Endpoint Pci Bus Number
+ @param[in] Device2 Endpoint Pci Device Number
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS VC mapping correctly initialized
+**/
+EFI_STATUS
+PcieSetCommonClock (
+ IN UINT8 Bus1,
+ IN UINT8 Device1,
+ IN UINT8 Function1,
+ IN UINT8 Bus2,
+ IN UINT8 Device2
+ );
+
+/**
+ This function enables the CLKREQ# PM on all the end point functions
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] RootFunction Rootport Function Number
+
+**/
+VOID
+PcieSetClkreq (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 RootFunction
+ );
+
+/**
+ This function get or set the Max Payload Size on all the end point functions
+
+ @param[in] EndPointBus The Bus Number of the Endpoint
+ @param[in] EndPointDevice The Device Number of the Endpoint
+ @param[in] MaxPayload The Max Payolad Size of the root port
+ @param[in] Operation True: Set the Max Payload Size on all the end point functions
+ False: Get the Max Payload Size on all the end point functions
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieMaxPayloadSize (
+ IN UINT8 EndPointBus,
+ IN UINT8 EndPointDevice,
+ IN OUT UINT16 *MaxPayload,
+ IN BOOLEAN Operation
+ );
+
+/**
+ This function disable the forwarding of EOI messages unless it discovers
+ an IOAPIC behind this root port.
+
+ @param[in] RootBus The Bus Number of the root port
+ @param[in] RootDevice The Device Number of the root port
+ @param[in] RootFunction The Function Number of the root port
+ @param[in] EndPointBus The Bus Number of the Endpoint
+ @param[in] EndPointDevice The Device Number of the Endpoint
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieSetEoiFwdDisable (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN UINT8 EndPointBus,
+ IN UINT8 EndPointDevice
+ );
+
+/**
+ This function performs the Power Management settings for root port and downstream device
+
+ @param[in] RootBus Pci Bus Number of the root port
+ @param[in] RootDevice Pci Device Number of the root port
+ @param[in] RootFunction Pci Function Number of the root port
+ @param[in] RootPortAspm Root port Aspm configuration
+ @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items
+ @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+ @param[in] NumOfDevltrOverride Number of Device specific LTR override items
+ @param[in] DevLtrOverride Pointer to array of Device specific LTR policy override items
+ @param[in] PchPwrOptPcie Pcie Power Optimizer Configuration
+ @param[in,out] L1SubstatesSupported L1 substates supported on the root port
+ @param[in] L1SubstatesConfig L1 substates configurations on the root port
+**/
+EFI_STATUS
+PcieSetPm (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm,
+ IN UINT8 NumOfDevAspmOverride,
+ IN PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax,
+ IN UINT8 NumOfDevltrOverride,
+ IN PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride,
+ IN PCH_PCIE_PWR_OPT *PchPwrOptPcie,
+ IN OUT BOOLEAN *L1SubstatesSupported,
+ IN PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubstatesConfig
+ );
+
+/**
+ This function checks if the root port and downstream device support Clkreq per port, ASPM L1 and L1 substates
+
+ @param[in] RootBus Pci Bus Number of the root port
+ @param[in] RootDevice Pci Device Number of the root port
+ @param[in] RootFunction Pci Function Number of the root port
+ @param[in] RootPortAspm Root port Aspm configuration
+ @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items
+ @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+ @param[in] NumOfDevLtrOverride Number of Device specific LTR override items
+ @param[in] DevLtrOverride Pointer to array of Device specific LTR policy override items
+ @param[in] PchPwrOptPcie Pcie Power Optimizer Configuration
+ @param[in,out] L1SubstatesSupported Flag to indicate if L1 Substates are supported
+ @param[in] L1SubstatesConfig L1 Substates configuration
+ @param[in] PolicyRevision Revision of the policy
+ @param[in,out] AspmVal Aspm value for both rootport and end point devices
+ @param[in,out] ClkreqPerPortSupported Clkreq support for both rootport and endpoint devices
+ @retval EFI_SUCCESS The function completed successfully
+ @exception EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found
+**/
+EFI_STATUS
+PcieCheckPmConfig (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm,
+ IN UINT8 NumOfDevAspmOverride,
+ IN PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax,
+ IN UINT8 NumOfDevLtrOverride,
+ IN PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride,
+ IN PCH_PCIE_PWR_OPT *PchPwrOptPcie,
+ IN OUT BOOLEAN *L1SubstatesSupported,
+ IN PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubstatesConfig,
+ IN OUT UINT16 *AspmVal,
+ IN OUT BOOLEAN *ClkreqPerPortSupported
+ );
+
+/**
+ Initializes the root port and its down stream devices
+
+ @param[in] RootPortBus Pci Bus Number of the root port
+ @param[in] RootPortDevice Pci Device Number of the root port
+ @param[in] RootPortFunc Pci Function Number of the root port
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+
+ @retval EFI_SUCCESS Successfully completed
+ @retval EFI_NOT_FOUND Can not find device.
+**/
+EFI_STATUS
+PchPcieInitRootPortDownstreamDevices (
+ IN UINT8 RootPortBus,
+ IN UINT8 RootPortDevice,
+ IN UINT8 RootPortFunc,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h new file mode 100644 index 0000000000..229cdcfd84 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h @@ -0,0 +1,251 @@ +/** @file
+ Header file for PchPlatform Lib.
+
+ Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PLATFORM_LIB_H_
+#define _PCH_PLATFORM_LIB_H_
+
+//
+// Timeout value used when Sending / Receiving messages.
+// NOTE: this must cover the longest possible wait time
+// between message being sent and response being available.
+// e.g. Virtual function readiness might take some time.
+//
+
+/**
+ Delay for at least the request number of microseconds.
+ This function would be called by runtime driver, please do not use any MMIO marco here.
+
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStall (
+ IN UINTN Microseconds
+ );
+
+/**
+ Check whether SPI is in descriptor mode
+
+ @param[in] SpiBase The PCH Spi Base Address
+
+ @retval TRUE SPI is in descriptor mode
+ @retval FALSE SPI is not in descriptor mode
+**/
+BOOLEAN
+EFIAPI
+PchIsSpiDescriptorMode (
+ IN UINTN SpiBase
+ );
+
+/**
+ Return SoC stepping type
+
+ @retval SOC_STEPPING SoC stepping type
+**/
+SOC_STEPPING
+EFIAPI
+SocStepping (
+ VOID
+ );
+
+/**
+Return SoC package type
+
+@retval SOC_PACKAGE SoC package type
+**/
+SOC_PACKAGE
+EFIAPI
+GetSocPackageType (
+ VOID
+ );
+
+/**
+ Determine if PCH is supported
+
+ @retval TRUE PCH is supported
+ @retval FALSE PCH is not supported
+**/
+BOOLEAN
+IsPchSupported (
+ VOID
+ );
+
+/**
+ This function can be called to enable/disable Alternate Access Mode
+
+ @param[in] IlbBase The PCH ILB Base Address
+ @param[in] AmeCtrl If TRUE, enable Alternate Access Mode.
+ If FALSE, disable Alternate Access Mode.
+
+**/
+VOID
+EFIAPI
+PchAlternateAccessMode (
+ IN UINTN IlbBase,
+ IN BOOLEAN AmeCtrl
+ );
+
+/**
+ Write DWord data to extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] Value Value to be written
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+**/
+VOID
+PchMsgBusWriteEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 Value,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Write DWord data to IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] Value Value to be written
+ @param[in] WriteOpCode Write Op Code
+
+**/
+VOID
+PchMsgBusWrite32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 Value,
+ IN UINT8 WriteOpCode
+ );
+
+/**
+ Read DWord data from extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] ReadOpCode Read Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval Data32 Value to be read.
+**/
+UINT32
+PchMsgBusReadEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT8 ReadOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Read DWord data from IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] ReadOpCode Read Op Code
+
+ @retval Data32 Value to be read.
+**/
+UINT32
+PchMsgBusRead32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT8 ReadOpCode
+ );
+
+/**
+ Read-modify-write DWord data from extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchMsgBusAndThenOrEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Read-modify-write DWord data from IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchMsgBusAndThenOr32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ );
+
+/**
+ This function can be called to poll for certain value within a time given.
+
+ @param[in] MmioAddress The Mmio Address.
+ @param[in] BitMask Bits to be masked.
+ @param[in] BitValue Value to be polled.
+ #param[in] DelayTime Delay time in terms of 100 micro seconds.
+
+ @retval EFI_SUCCESS Successfully polled the value.
+ @retval EFI_TIMEOUT Timeout while polling the value.
+**/
+EFI_STATUS
+EFIAPI
+PchMmioPoll32 (
+ IN UINTN MmioAddress,
+ IN UINT32 BitMask,
+ IN UINT32 BitValue,
+ IN UINT16 DelayTime
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h new file mode 100644 index 0000000000..c4db4fe0fb --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h @@ -0,0 +1,41 @@ +/** @file
+ Header file for Pch Smbus Lib.
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SMBUS_LIBRARY_H_
+#define _PCH_SMBUS_LIBRARY_H_
+
+/**
+ This function provides a standard way to execute Smbus sequential
+ I2C Read. This function allows the PCH to perform block reads to
+ certain I2C devices, such as serial E2PROMs. Typically these data
+ bytes correspond to an offset (address) within the serial memory
+ chips.
+
+ @param[in] SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Buffer Pointer to the buffer to store the bytes read
+ from the SMBUS
+ @param[out] Status eturn status for the executed command.
+
+ @retval UINTN The number of bytes read
+**/
+UINTN
+EFIAPI
+SmBusSeqI2CRead (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS * Status OPTIONAL
+ );
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h new file mode 100644 index 0000000000..4631f5d4d2 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h @@ -0,0 +1,178 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_WC_H_
+#define _PMIC_REG_WC_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/PmicLib.h>
+#include <Library/PcdLib.h>
+
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+
+UINT8
+EFIAPI
+MtvPlusPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+MtvPlusPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetBATID (void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetFABID(void);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetResetCause (void);
+
+VOID
+EFIAPI
+MtvPlusPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+MtvPlusPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGpioToggleForLpcConfig(void);
+
+VOID
+MtvPlusPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicSetVIDDecayWA (void);
+
+VOID
+MtvPlusPmicProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h new file mode 100644 index 0000000000..5737a89ecb --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h @@ -0,0 +1,193 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PMICNVMPROVISION_H_
+#define PMICNVMPROVISION_H_
+
+#define PMIC_PROVISIONING_ASK_USER 0
+#define PMIC_PROVISIONING_PUTS_DEBUG 1
+#define PMIC_PROVISIONING_NEUTERED_FOR_DEBUG 0
+#define PMIC_PROVISIONING_ASK_USER_TIMEOUT 60
+
+// setting below to '1' will print the current nvm content and exit.
+#define NVM_READBACK_ONLY 0
+
+#define NVM_OTP_MAX 2048
+#define NVM_WR_ERR 1
+#define MAGIC_NVM 0xDEADBEEF
+
+// Flags
+#define OTP_WR_ONGOING 0x1 //NVMSTAT0_REG[0]
+#define OTP_PD_ACT 0x2 //NVMSTAT0_REG[1]
+#define OTP_WR_MODE_EN 0x1 //NVMCTRL1_REG[0]
+#define OTP_WR_TRIGGER 0x2 //NVMCTRL1_REG[1]
+#define WRITE_FINISHED_INFO 0x1
+#define WRITE_ONE_CLEAR 0x1
+#define IA_IRQ_ASSERTED 1
+#define NVM_CONTROLLER 0x1
+
+// Register definitions
+#define PMIC_NVMDBUF0 0x1C6
+#define PMIC_NVMDBUF1 0x1C7
+#define PMIC_NVMDBUF2 0x1C8
+#define PMIC_NVMDBUF3 0x1C9
+#define PMIC_NVMDBUF4 0x1CA
+#define PMIC_NVMDBUF5 0x1CB
+#define PMIC_NVMDBUF6 0x1CC
+#define PMIC_NVMDBUF7 0x1CD
+#define PMIC_NVMDBUF8 0x1CE
+#define PMIC_NVMDBUF9 0x1CF
+#define PMIC_NVMDBUF10 0x1D0
+#define PMIC_NVMDBUF11 0x1D1
+#define PMIC_NVMDBUF12 0x1D2
+#define PMIC_NVMDBUF13 0x1D3
+#define PMIC_NVMDBUF14 0x1D4
+#define PMIC_NVMDBUF15 0x1D5
+#define PMIC_NVMDBUF16 0x1D6
+#define PMIC_NVMDBUF17 0x1D7
+#define PMIC_NVMDBUF18 0x1D8
+#define PMIC_NVMDBUF19 0x1D9
+#define PMIC_NVMDBUF20 0x1DA
+#define PMIC_NVMDBUF21 0x1DB
+#define PMIC_NVMDBUF22 0x1DC
+#define PMIC_NVMDBUF23 0x1DD
+#define PMIC_NVMDBUF24 0x1DE
+#define PMIC_NVMDBUF25 0x1DF
+#define PMIC_NVMDBUF26 0x1E0
+#define PMIC_NVMDBUF27 0x1E1
+#define PMIC_NVMDBUF28 0x1E2
+#define PMIC_NVMDBUF29 0x1E3
+#define PMIC_NVMDBUF30 0x1E4
+#define PMIC_NVMDBUF31 0x1E5
+#define PMIC_NVMDBUF32 0x1E6
+#define PMIC_NVMDBUF33 0x1E7
+#define PMIC_NVMCTL0 0x1E8
+#define PMIC_NVMCTL1 0x1E9
+#define PMIC_OTPMRB1 0x1EA
+#define PMIC_OTPMRB0_RD1 0x1ED
+#define PMIC_OTPMRB0_RD2 0x1EE
+#define PMIC_NVMSTAT0 0x1F0
+#define PMIC_NVMUSAGESTATH 0x1F3
+#define PMIC_NVMUSAGESTATL 0x1F4
+
+#define PMIC_ID_REG 0x000 // PMIC_ID_REG: 5E offset 0x00
+#define PMICSPARE00_REG 0x108 // OTP_VERSION: 6E offset 0x08
+#define PMICSPARE01_REG 0x109
+
+#define PMIC_VENDIRQLVL1 0x200
+#define PMIC_NVMVIRQ_REG 0x202 //4E
+
+#define PMIC_NVM_MB_ADDRH_REG 0x1C3 // for read-back
+#define PMIC_NVM_MB_ADDRL_REG 0x1C4 // for read-back
+#define PMIC_NVM_MB_DATA_REG 0x1C5 // for read-back
+
+#define MAX_SECTION_SIZE 34
+#define SECTION_HEADER_SIZE 2
+#define PMIC_PROVISIONING_PUTS_DEBUG 1
+#define PMIC_NVM_FILE_NAME L"PMIC_NVM_payload.bin"
+
+typedef struct
+{
+ UINT16 rstid_msb:2;
+ UINT16 owner:5;
+ UINT16 valid:1;
+ UINT16 sectionLength:5;
+ UINT16 type:1;
+ UINT16 rstid_lsb:2;
+} NVM_SectionHeader_t;
+
+typedef struct
+{
+ UINT32 Magic;
+ UINT16 xlsVersion;
+ UINT16 glueVersion;
+ UINT16 lengthOfPayloadStructure;
+ UINT8 checksum;
+ char nvmDate;
+} NVM_PayLoadHeader_t;
+
+#define MAX_OWNER_TYPE 20
+#define NUM_VALID_RESET_IDS 7
+#define RAW_DATA (1 << 2)
+#define ADDRESS_AUTO_INCREMENT (1 << 1)
+#define ARBITRARY_ADDRESS (1 << 0)
+
+
+// WHC:
+typedef enum
+{
+ Production = 1,
+ TLP1 = 0x2,
+ TLP2 = 0x3,
+ CSSM_Transl_Table = 0x4,
+ SoC_Device_ID2 = 0x6,
+ SoC_Device_ID3 = 0x7,
+ Soc_Device_ID4 = 0x8,
+ SCRATCH = 0x9, //also called "SoC_Device_ID_6"
+ VNN_SVID = 0xA,
+ VNN_DCDC = 0xF,
+ //NVM.sectionOwner.
+ VCC_PHS1_DCDC = 0x18,
+ //NVM.sectionOwner.
+ VCC_PHS2_DCDC = 0x19,
+ //NVM.sectionOwner.
+ VCC_PHS3_DCDC = 0x1A,
+ //NVM.sectionOwner.
+ VCC_PHS4_DCDC = 0x1B,
+ //NVM.sectionOwner.
+ VCC_PHS5_DCDC = 0x1C,
+ //NVM.sectionOwner.
+ VMEM_PHS1_DCDC = 0x1D,
+ //NVM.sectionOwner.
+ VDD2_PHS1_DCDC = 0x1E,
+ //-----
+ SoC_Device_ID_5 = 0x5,
+ VCC0_SVID = 0xB,
+ VCC1_SVID = 0xC,
+ VGG_SVID = 0xD,
+ V_PLT_SVID = 0xE,
+ VCC0_DCDC = 0x10,
+ VCC1_DCDC = 0x11,
+ VGG_DCDC = 0x12,
+ V1P8A_DCDC = 0xB,
+ V1P05A_DCDC = 0x14,
+ V1P15_DCDC = 0x15,
+ VDDQ_DCDC = 0x16,
+ V3P3A_DCDC = 0x17,
+} owner_type_e;
+
+typedef enum
+{
+ Production_ResetID = 0,
+ PMIC_OFF = 0x1,
+ PMIC_OFF_or_COLD_RESET = 0x3,
+ PMIC_OFF_or_COLD_WARM_RESET = 0x7,
+ VRTC_RESET = 0x8,
+ PMIC_OFF_or_TLP1_RESET = 0xC,
+ PMIC_OFF_or_TLP2_RESET = 0xA,
+} rstid_e;
+
+extern UINT32 sendToHostRT(char *, UINT32);
+
+UINT8 Calculate8BitChecksum_16(UINT8 *, UINT16);
+int validatePayload(UINT8, UINT16);
+void disable_OTP_WR_MODE_EN(void);
+UINT8 NVMRead(UINT8, UINT8, UINT16, UINT8 *);
+UINT8 Write_Section(NVM_SectionHeader_t *, UINT8 *);
+UINT32 NVM_ReadBack_and_exit(UINT16);
+UINT32 PmicNVMProvision(UINT8* , UINTN);
+void write_OTP_trigger_flag(void);
+
+#endif /* PMICNVMPROVISION_H_ */
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h new file mode 100644 index 0000000000..ba8c6da76c --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h @@ -0,0 +1,138 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_TIDC_H_
+#define _PMIC_REG_TIDC_H_
+
+#define BIT00 0x01
+#define BIT01 0x02
+#define BIT02 0x04
+#define BIT03 0x08
+#define BIT04 0x10
+#define BIT05 0x20
+#define BIT06 0x40
+#define BIT07 0x80
+
+#define TIDC_ID 0x00
+#define TIDC_MASK_VENDID (BIT07|BIT06)
+#define TIDC_MASK_MAJREV (BIT05|BIT04|BIT03)
+#define TIDC_MASK_MINREV (BIT02|BIT01|BIT00)
+
+#define TIDC_IRQ_R 0x01
+#define TIDC_MASK_CCEOCAL BIT07 //CC calibration completes IRQ asserted
+#define TIDC_MASK_CCEOCONV BIT06 //CC conversion completes IRQ asserted
+#define TIDC_MASK_VBUSDET BIT05 //VBUS crosses detection threshold (rising or falling) IRQ asserted
+#define TIDC_MASK_VBATLOW BIT04 //VBAT crosses low voltage detection threshold (rising or falling); VBATLOW IRQ asserted
+#define TIDC_MASK_ADCCOMPL BIT02 //ADC conversion complete; ADCCOMPL IRQ asserted
+#define TIDC_MASK_DIETMPWARN BIT01 //Die temp comparator threshold crossed (rising and falling); DIETMPWARN IRQ asserted
+#define TIDC_MASK_PWRBTN BIT00 //Power Button assertion debounce time met (press and release); PWRBTN IRQ asserted
+
+#define TIDC_MIRQ 0x02
+#define TIDC_MASK_MCCEOCAL BIT07 //CC calibration completes IRQ asserted
+#define TIDC_MASK_MCCEOCONV BIT06 //CC conversion completes IRQ asserted
+#define TIDC_MASK_MVBUSDET BIT05 //VBUS crosses detection threshold (rising or falling) IRQ asserted
+#define TIDC_MASK_MVBATLOW BIT04 //VBAT crosses low voltage detection threshold (rising or falling); VBATLOW IRQ asserted
+#define TIDC_MASK_MADCCOMPL BIT02 //ADC conversion complete; ADCCOMPL IRQ asserted
+#define TIDC_MASK_MDIETMPWARN BIT01 //Die temp comparator threshold crossed (rising and falling); DIETMPWARN IRQ asserted
+#define TIDC_MASK_MPWRBTN BIT00 //Power Button assertion debounce time met (press and release); PWRBTN IRQ asserted
+
+#define TIDC_SIRQ 0x03
+#define TIDC_MASK_SCCEOCAL BIT07 //One clock cycle pulse end of Calibration
+#define TIDC_MASK_SCCEOCONV BIT06 //One clock cycle pulse end of Conversion
+#define TIDC_MASK_SVBUSDET BIT05 //VBUS > VBUS_DET
+#define TIDC_MASK_SVBATLOW BIT04 //VBAT < VBAT_LOW
+#define TIDC_MASK_SADCCOMPL BIT02 //ADC is completing a conversion
+#define TIDC_MASK_SDIETMPWARN BIT01 //PMIC die temp monitoring threshold is triggered
+#define TIDC_MASK_SPWRBTN BIT00 //power button release value after 30 ms debounce (non-pressed)
+
+#define TIDC_PBUTTON 0x10
+#define TIDC_MASK_PBDWNTMR (BIT03|BIT02)
+#define TIDC_MASK_PBUPTMR (BIT01|BIT00)
+
+#define TIDC_CHIPCTRL 0x11
+#define TIDC_RSTSRC_R 0x12
+#define TIDC_MASK_PBOFF BIT07 //Power Button override was the shutdown reason
+#define TIDC_MASK_CLDOFF BIT06 //SoC initiated cold off was the shutdown reason
+#define TIDC_MASK_UVLO BIT05 //PMIC UVLO threshold was the shutdown reason
+#define TIDC_MASK_CLDRST BIT04 //Cold reset was the start up reason
+#define TIDC_MASK_GLBRST BIT03 //SoC initiated Global Reset was the start up reason
+#define TIDC_MASK_BATTIN BIT02 //Battery insertion was the start up reason
+#define TIDC_MASK_CHGIN BIT01 //Charger insertion was the start up reason
+#define TIDC_MASK_PBTN BIT00 //Power button was the start up reason
+
+#define TIDC_LOWBATTDET_W 0x17
+#define TIDC_VBATTHR 0x18
+#define TIDC_TMPSNSCFG 0x19
+
+#define TIDC_BUCK1CTRL 0x20
+#define TIDC_BUCK2CTRL 0x21
+#define TIDC_BUCK2SLPEXIT 0x22
+#define TIDC_BUCK2SLEEP 0x23
+#define TIDC_BUCK3CTRL 0x24
+#define TIDC_BUCK3SLPEXIT 0x25
+#define TIDC_BUCK3SLEEP 0x26
+#define TIDC_BUCK4CTRL 0x27
+#define TIDC_BUCK5CTRL 0x28
+#define TIDC_BUCK5VSEL 0x29
+#define TIDC_BUCK5SLPEXIT 0x2A
+#define TIDC_BUCK5SLEEP 0x2B
+#define TIDC_BUCK6CTRL 0x2C
+
+#define TIDC_LDO1CTRL 0x41
+#define TIDC_LDO2CTRL 0x42
+#define TIDC_LDO3CTRL 0x43
+#define TIDC_LDO5CTRL 0x45
+#define TIDC_LDO6CTRL 0x46
+#define TIDC_LDO7CTRL 0x47
+#define TIDC_LDO8CTRL 0x48
+#define TIDC_LDO9CTRL 0x49
+#define TIDC_LDO10CTRL 0x4A
+#define TIDC_LDO11CTRL 0x4B
+#define TIDC_LDO12CTRL 0x4C
+#define TIDC_LDO13CTRL 0x4D
+#define TIDC_LDO14CTRL 0x4E
+
+#define TIDC_ADCCTRL_W 0x50
+#define TIDC_ADCDIETEMPZSE 0x51
+#define TIDC_ADCGPINTHERMGE 0x52
+#define TIDC_ADCVBATZSEGE 0x53
+#define TIDC_VBATHI 0x54
+#define TIDC_VBATLO 0x55
+#define TIDC_MASK_DIETEMPH (BIT01|BIT00)
+
+#define TIDC_DIETEMPHI 0x56
+#define TIDC_DIETEMPLO 0x57
+#define TIDC_BPTHERMHI 0x58
+#define TIDC_MASK_BPTHERMH (BIT01|BIT00)
+#define TIDC_BPTHERMLO 0x59
+
+#define TIDC_GPADCHI 0x5A
+#define TIDC_GPADCLO 0x5B
+
+#define TIDC_CC_CTRL 0x60
+#define TIDC_CC_OFFSETHI 0x61
+#define TIDC_CC_OFFSETLO 0x62
+#define TIDC_CC_ACC_BYTE3 0x63
+#define TIDC_CC_ACC_BYTE2 0x64
+#define TIDC_CC_ACC_BYTE1 0x65
+#define TIDC_CC_ACC_BYTE0 0x66
+#define TIDC_CC_SMPL_BYTE2 0x67
+#define TIDC_CC_SMPL_BYTE1 0x68
+#define TIDC_CC_SMPL_BYTE0 0x69
+#define TIDC_CC_INTG_BYTE1 0x6A
+#define TIDC_CC_INTG_BYTE0 0x6B
+#define TIDC_CC_SWOFFSETH 0x6C
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h new file mode 100644 index 0000000000..f23a842235 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h @@ -0,0 +1,398 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DC_X_PMIC_REG_CC_H_
+#define _DC_X_PMIC_REG_CC_H_
+
+#define BIT00 0x01
+#define BIT01 0x02
+#define BIT02 0x04
+#define BIT03 0x08
+#define BIT04 0x10
+#define BIT05 0x20
+#define BIT06 0x40
+#define BIT07 0x80
+
+#define DC_X_PMIC_REG_PWR_SRC_STS 0x00
+#define DC_X_MAST_BAT_CURR_DIR BIT2 //Indication Battery current direction
+#define DC_X_MAST_VBUS_PRESENCE BIT5 //VBUS presence indication
+
+#define DC_X_PMIC_REG_CHARGER_STS 0x01
+#define DC_X_MAST_BAT_PRESENCE BIT5 //Battery presence indication
+
+#define DC_X_PMIC_REG_PUPD_REASON 0x02
+#define DC_X_MAST_PWRBTN_START BIT0 //Power on key was the start up reason
+#define DC_X_MAST_CHR_INERT_START BIT1 //Charger insertion was the start up reason
+#define DC_X_MAST_BAT_INERT_START BIT2 //Battery insertion was the start up reason
+#define DC_X_MAST_SOC_GLOBRST BIT3 //SOC initiated Global Reset was the start up reason
+#define DC_X_MAST_COLDRST BIT4 //Cold reset was the start up reaso
+#define DC_X_MAST_UVLO_SHDN BIT5 //PMIC UVLO threshold was the shutdown reason
+#define DC_X_MAST_SOC_SHDW BIT6 //SOC initiated cold off was the shutdown reason
+#define DC_X_MAST_PWRBTN_SHDW BIT7 //Power on key override was the shutdown reason
+
+#define DC_X_PMIC_REG_IC_TYPC 0x03
+#define PMIC_DEV_MASK_VERSION (BIT05|BIT04)
+#define PMIC_DEV_MASK_VENDER (BIT07|BIT06|BIT03|BIT02|BIT01|BIT00)
+
+#define DC_X_PMIC_REG_DATA_BUFFER_04 0x04
+#define DC_X_PMIC_REG_DATA_BUFFER_05 0x05
+#define DC_X_PMIC_REG_DATA_BUFFER_06 0x06
+#define DC_X_PMIC_REG_DATA_BUFFER_07 0x07
+#define DC_X_PMIC_REG_DATA_BUFFER_08 0x08
+#define DC_X_PMIC_REG_DATA_BUFFER_09 0x09
+#define DC_X_PMIC_REG_DATA_BUFFER_0A 0x0A
+#define DC_X_PMIC_REG_DATA_BUFFER_0B 0x0B
+#define DC_X_PMIC_REG_DATA_BUFFER_0C 0x0C
+#define DC_X_PMIC_REG_DATA_BUFFER_0D 0x0D
+#define DC_X_PMIC_REG_DATA_BUFFER_0E 0x0E
+#define DC_X_PMIC_REG_DATA_BUFFER_0F 0x0F
+#define DC_X_PMIC_REG_DATA_BUFFER_F2 0xF2
+#define DC_X_PMIC_REG_DATA_BUFFER_F4 0xF4
+#define DC_X_PMIC_REG_DATA_BUFFER_FF 0xFF
+
+#define DC_X_PMIC_REG_VR_CTRL_1 0x10
+#define DC_X_PMIC_REG_VR_CTRL_2 0x12
+#define DC_X_MASK_DLDO4_CTRL BIT06 //DLDO4 on©\off control 0©\off; 1©\on
+#define DC_X_MASK_DLDO3_CTRL BIT05 //DLDO3 on©\off control
+#define DC_X_MASK_DLDO2_CTRL BIT04 //DLDO2 on©\off control
+#define DC_X_MASK_DLDO1_CTRL BIT03 //DLDO1 on©\off control
+#define DC_X_MASK_ELDO3_CTRL BIT02 //ELDO3 on©\off control
+#define DC_X_MASK_ELDO2_CTRL BIT01 //ELDO2 on©\off control
+#define DC_X_MASK_ELDO1_CTRL BIT00 //ELDO1 on©\off control
+
+#define DC_X_PMIC_REG_VR_CTRL_3 0x13
+#define DC_X_MASK_ALDO3_CTRL BIT07 //ALDO3 on©\off control 0©\off; 1©\on
+#define DC_X_MASK_ALDO2_CTRL BIT06 //ALDO2 on©\off control
+#define DC_X_MASK_ALDO1_CTRL BIT05 //ALDO1 on©\off control
+#define DC_X_MASK_FLDO3_CTRL BIT04 //FLDO2 on©\off control
+#define DC_X_MASK_FLDO2_CTRL BIT03 //FLDO1 on©\off control
+#define DC_X_MASK_FLDO1_CTRL BIT02 //FLDO3 on©\off control
+
+#define DC_X_PMIC_REG_VR_CTRL_SYNC 0x14
+#define DC_X_MASK_BUCK5_POLY_PHASE BIT06 //BUCK5 poly©\phase control
+#define DC_X_MASK_BUCK3_$_POLY_PHASE BIT05 //BUCK 3 & 4 change to poly©\phase Buck
+#define DC_X_MASK_BUCK235_VRUN_VSLP BIT04 //Select the BUCK2/ 3 /5 Vrun register or Vsleep register
+#define DC_X_MASK_COLD_RESET_CONDITION BIT03 //If SLP_S0IX_B go high and PLTRST_B status is low for 512ms, PMIC will do a cold reset or not (Reset: power on reset)
+#define DC_X_MASK_COLD_RESET_ENABLE BIT02 //Cold reset Enable . All power rails power down and then power up,64ms delay
+#define DC_X_MASK_POWER_CONTROL_SEL BIT01 //1©\select buffer register, output value of control register to buffer
+#define DC_X_MASK_OUTPUT_BUFFER BIT00 //1©\outport to control register from buffer Bit[1:0], self clear to 0 after output
+
+#define DC_X_PMIC_REG_VR_CTRL_DLDO1 0x15
+#define DC_X_PMIC_REG_VR_CTRL_DLDO2 0x16
+#define DC_X_PMIC_REG_VR_CTRL_DLDO3 0x17
+#define DC_X_PMIC_REG_VR_CTRL_DLDO4 0x18
+#define DC_X_PMIC_REG_VR_CTRL_ELDO1 0x19
+#define DC_X_PMIC_REG_VR_CTRL_ELDO2 0x1A
+#define DC_X_PMIC_REG_VR_CTRL_ELDO3 0x1B
+#define DC_X_MASK_ELDO_VOL_18 (BIT04|BIT02|BIT01)
+
+#define DC_X_PMIC_REG_VR_CTRL_FLDO1 0x1C
+#define DC_X_PMIC_REG_VR_CTRL_FLDO2_3 0x1D
+
+#define DC_X_PMIC_REG_VR_CTRL_BUCK6 0x20
+#define DC_X_PMIC_REG_VR_CTRL_BUCK5 0x21
+#define DC_X_PMIC_REG_VR_CTRL_BUCK1 0x23
+#define DC_X_PMIC_REG_VR_CTRL_BUCK4 0x24
+#define DC_X_MASK_DVM_STATUS BIT07 //DVM finished or not status bit 1: finished
+#define DC_X_MASK_VOL_8BIT_6_0 (BIT00|BIT01|BIT02|BIT03|BIT04|BIT05|BIT06) //voltage setting Bit 6©\0 0.80©\1.12V£º10mV/step 1.14©\1.84V£º20mV/step
+
+#define DC_X_PMIC_REG_VR_CTRL_BUCK3 0x25
+#define DC_X_PMIC_REG_VR_CTRL_BUCK2 0x26
+#define DC_X_PMIC_REG_VR_BUCK_RAMP_CTRL 0x27
+#define DC_X_MASK_BUCK2_DVM_CTRL BIT07 //BUCK2 DVM on©\off control
+#define DC_X_MASK_BUCK3_DVM_CTRL BIT06 //BUCK3 DVM on©\off control
+#define DC_X_MASK_BUCK4_DVM_CTRL BIT05 //BUCK4 DVM on©\off control
+#define DC_X_MASK_BUCK1_DVM_CTRL BIT04 //BUCK1 DVM on©\off control
+#define DC_X_MASK_BUCK5_DVM_CTRL BIT02 //BUCK5 DVM on©\off control
+#define DC_X_MASK_RSMRST_B_LOW BIT01 //RSMRST_B drive low when ALDO3 less than 85% or not control
+#define DC_X_MASK_DRAMPWROK BIT00 //DRAMPWROK drive low when FLDO3 less than 85% or not control
+
+#define DC_X_PMIC_REG_ALDO1_VOL_CTRL 0x28
+#define DC_X_MASK_ALDO_VOL_30 (BIT04|BIT02|BIT01|BIT00)
+#define DC_X_MASK_ALDO_VOL_29 (BIT04|BIT02|BIT01)
+#define DC_X_MASK_ALDO_VOL_28 (BIT04|BIT02|BIT00)
+
+#define DC_X_PMIC_REG_ALDO2_VOL_CTRL 0x29
+#define DC_X_PMIC_REG_ALDO3_VOL_CTRL 0x2A
+#define DC_X_PMIC_REG_BC_GBL_DETECT 0x2C
+#define DC_X_PMIC_REG_BC_VBUS_CTRL_STS 0x2D
+#define DC_X_PMIC_REG_BC_USB_STATUS 0x2E
+#define DC_X_PMIC_REG_BC_DETECT_STS 0x2F
+
+#define DC_X_PMIC_REG_VBUS_PATH_CTRL 0x30
+#define DC_X_PMIC_REG_WAKE_UP_CTRL 0x31
+#define DC_X_PMIC_REG_PD_BAT_CHGLED 0x32
+#define DC_X_MASK_BAT_DETECT BIT06 //Battery detection function control: 0©\disable; 1©\enable
+#define DC_X_MASK_CHGLED_PIN (BIT05|BIT04) //CHGLED pin control
+#define DC_X_MASK_CHGLED_PIN_HIZ 0x0 //00: Hi-Z
+#define DC_X_MASK_CHGLED_PIN_05HZ 0x10 //01: 25% 0.5Hz toggle
+#define DC_X_MASK_CHGLED_PIN_2HZ 0x20 //10: 25% 2Hz toggle
+#define DC_X_MASK_CHGLED_PIN_LOW 0x30 //11: drive low
+#define DC_X_MASK_CHGLED_PIN_CTRL BIT03 //0: controlled by REG 32H[5:4]
+#define DC_X_MASK_DELAY_TIME (BIT01|BIT00) //control bit for Delay time between PWROK signal and power good time
+#define DC_X_MASK_DELAY_TIME_8MS 0x0
+#define DC_X_MASK_DELAY_TIME_16MS 0x1
+#define DC_X_MASK_DELAY_TIME_32MS 0x2
+#define DC_X_MASK_DELAY_TIME_64MS 0x3
+
+#define DC_X_PMIC_REG_CHARGER_CTRL_1 0x33
+#define DC_X_PMIC_REG_CHARGER_CTRL_2 0x34
+#define DC_X_MASK_PRE_CHARGE_TIME (BIT07|BIT06) //Pre©\charge Timer length setting 1:0
+#define DC_X_MASK_PRE_CHARGE_TIME_40MIN 0x0 //40 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_50MIN BIT06 //50 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_60MIN BIT07 //60 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_70MIN (BIT07|BIT06) //70 minutes
+#define DC_X_MASK_CRG_ON_OFF BIT05 //Charger output turn off or not when charging is end & the PMIC is on state 1: do not turn off
+#define DC_X_MASK_CHGLED_SEL BIT04 //CHGLED Type select when REG 32_[3] is 0 1: Type B
+#define DC_X_MASK_FAST_CHARGE_TIME (BIT01|BIT00) //Fast charge maximum time setting1:0
+#define DC_X_MASK_FAST_CHARGE_TIME_6HRS 0x0 //6 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_8HRS 0x1 //8 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_10HRS 0x2 //10 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_12HRS 0x3 //12 hours
+
+#define DC_X_PMIC_REG_CHARGER_CTRL_3 0x35
+#define DC_X_PMIC_REG_POK_SETTING 0x36
+#define DC_X_MASK_ONLEVEL (BIT06|BIT07) //ONLEVEL setting
+#define DC_X_MASK_ONLEVEL_128MS 0 // 128ms
+#define DC_X_MASK_ONLEVEL_1S BIT06 // 1s
+#define DC_X_MASK_ONLEVEL_2S BIT07 // 2s
+#define DC_X_MASK_ONLEVEL_3S (BIT06|BIT07) // 3s
+#define DC_X_MASK_IRQLEVEL (BIT04|BIT05) //IRQLEVEL setting
+#define DC_X_MASK_IRQLEVEL_1S 0 //1s
+#define DC_X_MASK_IRQLEVEL_1_5S BIT04 //1.5s
+#define DC_X_MASK_IRQLEVEL_2S BIT05 //2s
+#define DC_X_MASK_IRQLEVEL_2_5S (BIT04|BIT05) //2.5s
+#define DC_X_MASK_OFFEVEL (BIT00|BIT01) //OFFLEVEL setting
+#define DC_X_MASK_OFFEVEL_4S 0
+#define DC_X_MASK_OFFEVEL_6S 1
+#define DC_X_MASK_OFFEVEL_8S 2
+#define DC_X_MASK_OFFEVEL_10S 3
+#define DC_X_MASK_AUTO_ON_OFFEVEL BIT02
+#define DC_X_MASK_SHDW_OFFEVEL BIT03 //Enable bit of the function which will shut down the PMIC when POK is larger than OFFLEVEL
+
+#define DC_X_PMIC_REG_POK_POFF_SETTING 0x37
+#define DC_X_MASK_POK_POFF (BIT00|BIT01|BIT02) //Power off activity time setting
+#define DC_X_MASK_POK_POFF_0S 0
+#define DC_X_MASK_POK_POFF_10S 1
+#define DC_X_PMIC_REG_VLTF_CHARGE_SETTING 0x38
+#define DC_X_PMIC_REG_VHTF_CHARGE_SETTING 0x39
+#define DC_X_PMIC_REG_BUCK_FREQ_SETTING 0x3B
+#define DC_X_PMIC_REG_VLTF_WORK_SETTING 0x3C
+#define DC_X_PMIC_REG_VHTF_WORK_SETTING 0x3D
+
+#define DC_X_PMIC_REG_IRQ_CTRL_1 0x40
+#define DC_X_MASK_VBUS_HI_TO_LOW_EN BIT02 //VBUS from high go low IRQ enable
+#define DC_X_MASK_VBUS_LOW_TO_HI_EN BIT03 //VBUS from low go high IRQ enable
+#define DC_X_MASK_VBUS_OV_VOL_EN BIT04 //VBUS over voltage IRQ enable
+#define DC_X_MASK_VBUS_HI_TO_LOW_EN_1 BIT05 //VBUS from high go low IRQ enable
+#define DC_X_MASK_VBUS_LOW_TO_HI_EN_1 BIT06 //VBUS from low go high IRQ enable
+#define DC_X_MASK_VBUS_OV_VOL_EN_1 BIT07 //VBUS over voltage IRQ enable
+
+#define DC_X_PMIC_REG_IRQ_CTRL_2 0x41
+#define DC_X_PMIC_REG_IRQ_CTRL_3 0x42
+#define DC_X_PMIC_REG_IRQ_CTRL_4 0x43
+#define DC_X_MASK_PMIC_TEMP BIT07 //The PMIC temperature over the warning level 2 IRQ (OTIRQ) enable
+#define DC_X_MASK_GPADC BIT02 //GPADC(GPIO0) ADC convert finished IRQ enable
+#define DC_X_MASK_WARN_LEVEL1 BIT01 //Enable bit for IRQ which indicate battery capacity ratio being lower than warning level1
+#define DC_X_MASK_WARN_LEVEL2 BIT00 //Enable bit for IRQ which indicate battery capacity ratio being lower than warning level2
+
+#define DC_X_PMIC_REG_IRQ_CTRL_5 0x44
+#define DC_X_PMIC_REG_IRQ_CTRL_6 0x45
+#define DC_X_PMIC_REG_IRQ_STS_1 0x48
+#define DC_X_MASK_VBUS_HI_TO_LOW BIT02 //VBUS from high go low IRQ
+#define DC_X_MASK_VBUS_LOW_TO_HI BIT03 //VBUS from low go high IRQ
+#define DC_X_MASK_VBUS_OV_VOL BIT04 //VBUS over voltage IRQ
+
+#define DC_X_PMIC_REG_IRQ_STS_2 0x49
+#define DC_X_MASK_BAT_APPEND BIT07 //Battery append IRQ
+#define DC_X_MASK_BAT_CHARGE_DONE BIT02 //Battery charge done IRQ
+
+#define DC_X_PMIC_REG_IRQ_STS_3 0x4A
+#define DC_X_PMIC_REG_IRQ_STS_4 0x4B
+#define DC_X_PMIC_REG_IRQ_STS_5 0x4C
+#define DC_X_MASK_PMIC_EVENT_IRQ_STS BIT07
+#define DC_X_MASK_PMIC_POKPIRQ_STS BIT06
+#define DC_X_MASK_PMIC_POKNIRQ_STS BIT05
+#define DC_X_MASK_PMIC_POKSIRQ_STS BIT04
+#define DC_X_MASK_PMIC_POKLIRQ_STS BIT03
+#define DC_X_MASK_PMIC_POKOIRQ_STS BIT02
+#define DC_X_MASK_PMIC_GPIO1_IRQ_STS BIT01
+#define DC_X_MASK_PMIC_GPIO0_IRQ_STS BIT00
+
+#define DC_X_PMIC_REG_IRQ_STS_6 0x4D
+
+#define DC_X_PMIC_REG_TS_PIN_INPUT_HI 0x58
+#define DC_X_PMIC_REG_TS_PIN_INPUT_LO 0x59
+#define DC_X_PMIC_REG_GPADC_INPUT_HI 0x5A
+#define DC_X_PMIC_REG_GPADC_INPUT_LO 0x5B
+
+#define DC_X_PMIC_REG_BAT_VOL_HI 0x78
+#define DC_X_PMIC_REG_BAT_VOL_LO 0x79
+#define DC_X_PMIC_REG_BAT_CHG_CURRENT_HI 0x7A
+#define DC_X_PMIC_REG_BAT_CHG_CURRENT_LO 0x7B
+#define DC_X_PMIC_REG_BAT_DISCHG_CURRENT_HI 0x7C
+#define DC_X_PMIC_REG_BAT_DISCHG_CURRENT_LO 0x7D
+
+#define DC_X_PMIC_REG_BUCK_MODE_SEL 0x80
+#define DC_X_MASK_BUCK2_PFM_PWM_CTRL BIT06 //BUCK2 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK3_PFM_PWM_CTRL BIT05 //BUCK3 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK4_PFM_PWM_CTRL BIT04 //BUCK4 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK1_PFM_PWM_CTRL BIT03 //BUCK1 PFM/PWM control: 0: auto switch 1: PSM/PWM
+#define DC_X_MASK_BUCK5_PFM_PWM_CTRL BIT01 //BUCK5 PFM/PWM control: 0: auto switch 1: PSM/PWM
+#define DC_X_MASK_BUCK6_PFM_PWM_CTRL BIT00 //BUCK6 PFM/PWM control: 0: auto switch 1: always PWM
+
+#define DC_X_PMIC_REG_OUTPUT_MON_CTRL 0x81
+#define DC_X_PMIC_REG_ADC_ENABLE 0x82
+#define DC_X_MASK_GPIO0_ADC_ENABLE BIT04 //GPIO0 ADC enable
+
+#define DC_X_PMIC_REG_ADC_CTRL 0x84
+#define DC_X_MASK_GPIO0_PIN_CTRL (BIT07|BIT06) //Current source from GPIO0 pin control
+#define DC_X_MASK_GPIO0_PIN_CTRL_20UA (0x0) //20uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_40UA (BIT06) //40uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_60UA (BIT07) //60uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_80UA (BIT07|BIT06) //80uA
+
+#define DC_X_PMIC_REG_ADC_SPEED_SETTING 0x85
+#define DC_X_MASK_GPIO0_ADC_WORK_MODE (BIT02) //GPIO0 ADC work mode 1-outout current
+
+#define DC_X_PMIC_REG_TIMER_CTRL 0x8A
+#define DC_X_PMIC_REG_BUCK_OUTPUT_MON 0x8E
+#define DC_X_PMIC_REG_IRQ_HOT_OVSHDN 0x8F
+#define DC_X_MASK_POK16S_RESET_EN BIT03
+#define DC_X_MASK_OVTEMP_SHWD_EN BIT02
+#define DC_X_MASK_VOL_RECOVERY_EN BIT01
+
+#define DC_X_PMIC_REG_GPIO0_CTRL 0x90
+#define DC_X_MASK_GPIO0_PIN_FUNC_CTRL (BIT02|BIT01|BIT00) //ADC input mode
+
+#define DC_X_PMIC_REG_GPIO0_VOLTAGE 0x91
+#define DC_X_PMIC_REG_GPIO1_CTRL 0x92
+#define DC_X_PMIC_REG_GPIO1_VOLTAGE 0x93
+#define DC_X_PMIC_REG_GPIO_STATUS 0x94
+#define DC_X_PMIC_REG_GPIO_CTRL 0x97
+#define DC_X_PMIC_REG_WAKEUP_SEQUENCE1 0x9A
+
+#define DC_X_PMIC_REG_WAKEUP_SEQUENCE2 0x9B
+#define DC_X_PMIC_REG_SLEEP_SEQUENCE1 0x9C
+#define DC_X_PMIC_REG_SLEEP_SEQUENCE2 0x9D
+#define DC_X_PMIC_REG_VR_SLEEP_STATE 0x9E
+#define DC_X_MASK_BUCK2_SLP_S0IX_B BIT04 //When BUCK2 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK3_SLP_S0IX_B BIT03 //When BUCK3 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK1_SLP_S0IX_B BIT02 //When BUCK1 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK5_SLP_S0IX_B BIT01 //When BUCK5 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_FLDO1_SLP_S0IX_B BIT00 //When FLDO1 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+
+#define DC_X_PMIC_REG_RT_BAT_VOL_HI 0xA0
+#define DC_X_PMIC_REG_RT_BAT_VOL_LO 0xA1
+
+#define DC_X_PMIC_REG_FUEL_GARGE_CTRL 0xB8
+#define DC_X_PMIC_REG_BAT_CAP_PERCENT 0xB9
+#define DC_X_PMIC_REG_RDC1 0xBA
+#define DC_X_PMIC_REG_RDC0 0xBB
+#define DC_X_PMIC_REG_OCV1 0xBC
+#define DC_X_PMIC_REG_OCV0 0xBD
+#define DC_X_PMIC_REG_BAT_MAX_CAP_HI 0xE0
+#define DC_X_PMIC_REG_BAT_MAX_CAP_LO 0xE1
+#define DC_X_PMIC_REG_CLB_M_COUNTER_HI 0xE2
+#define DC_X_PMIC_REG_CLB_M_COUNTER_LO 0xE3
+#define DC_X_PMIC_REG_OCV_PERCENT_BAT_CAP 0xE4
+#define DC_X_PMIC_REG_CLB_M_PERCENT_BAT_CAP 0xE5
+#define DC_X_PMIC_REG_BAT_CAP_PERCENT_W 0xE6
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_0 0xE8
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_1 0xE9
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_2 0xEA
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_3 0xEB
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_4 0xEC
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_5 0xED
+
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C0 0xC0
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C1 0xC1
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C2 0xC2
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C3 0xC3
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C4 0xC4
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C5 0xC5
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C6 0xC6
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C7 0xC7
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C8 0xC8
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C9 0xC9
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CA 0xCA
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CB 0xCB
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CC 0xCC
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CD 0xCD
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CE 0xCE
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CF 0xCF
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D0 0xD0
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D1 0xD1
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D2 0xD2
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D3 0xD3
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D4 0xD4
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D5 0xD5
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D6 0xD6
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D7 0xD7
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D8 0xD8
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D9 0xD9
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DA 0xDA
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DB 0xDB
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DC 0xDC
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DD 0XDD
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DE 0xDE
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DF 0xDF
+
+#if 0
+//DollarCove XPOWER FG Characterization data Provided by FG Mfg
+//This Registers 0xC0-0xDF is OCV Percentage Table ( Refer AXP288 Datasheet for more detail )
+//Charcterizaiton Start ----->
+#define XPOWER_FG_OCV_C0 0x00
+#define XPOWER_FG_OCV_C1 0x00
+#define XPOWER_FG_OCV_C2 0x00
+#define XPOWER_FG_OCV_C3 0x00
+#define XPOWER_FG_OCV_C4 0x01
+#define XPOWER_FG_OCV_C5 0x01
+#define XPOWER_FG_OCV_C6 0x02
+#define XPOWER_FG_OCV_C7 0x02
+#define XPOWER_FG_OCV_C8 0x02
+#define XPOWER_FG_OCV_C9 0x03
+#define XPOWER_FG_OCV_CA 0x03
+#define XPOWER_FG_OCV_CB 0x04
+#define XPOWER_FG_OCV_CC 0x0C
+#define XPOWER_FG_OCV_CD 0x10
+#define XPOWER_FG_OCV_CE 0x16
+#define XPOWER_FG_OCV_CF 0x1C
+#define XPOWER_FG_OCV_D0 0x27
+#define XPOWER_FG_OCV_D1 0x2C
+#define XPOWER_FG_OCV_D2 0x30
+#define XPOWER_FG_OCV_D3 0x35
+#define XPOWER_FG_OCV_D4 0x3A
+#define XPOWER_FG_OCV_D5 0x3F
+#define XPOWER_FG_OCV_D6 0x43
+#define XPOWER_FG_OCV_D7 0x47
+#define XPOWER_FG_OCV_D8 0x4B
+#define XPOWER_FG_OCV_D9 0x4E
+#define XPOWER_FG_OCV_DA 0x50
+#define XPOWER_FG_OCV_DB 0x51
+#define XPOWER_FG_OCV_DC 0x54
+#define XPOWER_FG_OCV_DD 0x57
+#define XPOWER_FG_OCV_DE 0x5B
+#define XPOWER_FG_OCV_DF 0x5E
+
+#define BATTERY_MAX_CAP_HI 0x8D
+#define BATTERY_MAX_CAP_LO 0xA3
+#define BATTERY_RDC1 0xC0
+#define BATTERY_RDC0 0x97
+
+//Charcterizaiton Table End <-----------
+#endif
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h new file mode 100644 index 0000000000..39c7760ef1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h @@ -0,0 +1,939 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_WC_H_
+#define _PMIC_REG_WC_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/I2CLib.h>
+#include <Library/PmicLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+#include "PmicNVMProvision.h"
+
+#define DELAY_BETWEEN_INSTRUCTION_500 500
+#define DELAY_BETWEEN_INSTRUCTION_100 100
+#define DELAY_BETWEEN_INSTRUCTION_50 50
+#define DELAY_BETWEEN_INSTRUCTION_10 10
+#define DELAY_BETWEEN_INSTRUCTION_5 5
+
+#define WC_PMIC_I2C_CHANNEL_NUMBER 0x6
+#define WC_PMIC_I2C_DEV_1_SLAVE_ADDRESS 0x4E // For BXT
+#define WC_PMIC_I2C_DEV_2_SLAVE_ADDRESS 0x4F // Common
+#define WC_PMIC_I2C_DEV_3_SLAVE_ADDRESS 0x5E // Common
+#define WC_PMIC_I2C_DEV_4_SLAVE_ADDRESS 0x5F // Common
+#define WC_PMIC_I2C_DEV_5_SLAVE_ADDRESS 0x6E // For CHT
+#define WC_PMIC_I2C_SCRATCH_SLAVE_ADDRESS 0x6F
+#define WC_PMIC_I2C_VCC0_DEVICE_ADDRESS 0x10
+#define WC_PMIC_I2C_VCC1_DEVICE_ADDRESS 0x18
+#define WC_PMIC_I2C_VNN_DEVICE_ADDRESS 0x12
+#define WC_PMIC_I2C_VGG_DEVICE_ADDRESS 0x1A
+
+//VCC0 VCC1 VNN VGG definitions
+
+#define VOUT_MAX_REG 0x30
+#define VID_MAX_REG 0x33
+
+//DEV 2 definitions
+
+#define DEV2_ID_TRMPGM_REG 0x00
+#define DEV2_ID_OTPVERSION_REG 0x01
+#define DEV2_ADC_GPADCREQ_REG 0x02
+#define DEV2_ADC_VBATRSLTH_REG 0x03
+#define DEV2_ADC_VBATRSLTL_REG 0x04
+#define DEV2_ADC_GPADCCNTL_REG 0x05
+#define DEV2_ADC_BATTIDRSLTH_REG 0x06
+#define DEV2_ADC_BATTIDRSLTL_REG 0x07
+#define DEV2_ADC_USBIDRSLTH_REG 0x08
+#define DEV2_ADC_USBIDRSLTL_REG 0x09
+#define DEV2_ADC_GPMEASRSLTH_REG 0x0A
+#define DEV2_ADC_GPMEASRSLTL_REG 0x0B
+#define DEV2_ADC_Y0DATAH_REG 0x0C
+#define DEV2_ADC_Y0DATAL_REG 0x0D
+#define DEV2_ADC_Y1DATAH_REG 0x0E
+#define DEV2_ADC_Y1DATAL_REG 0x0F
+#define DEV2_SVID_DEV2_STATUS_1_REG 0x10
+#define DEV2_SVID_DEV2_STATUS_2_REG 0x11
+#define DEV2_ADC_PEAKREQ_REG 0x12
+#define DEV2_ADC_PEAKRSLTH_REG 0x13
+#define DEV2_ADC_PEAKRSLTL_REG 0x14
+#define DEV2_THERM_BATTEMP0H_REG 0x15
+#define DEV2_THERM_BATTEMP0L_REG 0x16
+#define DEV2_THERM_BATTEMP1H_REG 0x17
+#define DEV2_THERM_BATTEMP1L_REG 0x18
+#define DEV2_THERM_STHRMIRQ0_REG 0x19
+#define DEV2_THERM_STHRMIRQ1_REG 0x1A
+#define DEV2_THERM_STHRMIRQ2_REG 0x1B
+#define DEV2_SVID_DEV2_STATUS2_LASTREAD_REG 0x1C
+#define DEV2_THERM_THRMMONCFG_REG 0x1D
+#define DEV2_THERM_THRMMONCTL_REG 0x1E
+#define DEV2_THERM_BATTHERMMONCTL_REG 0x1F
+#define DEV2_THERM_VBATMONCTL_REG 0x20
+#define DEV2_THERM_GPMONCTL_REG 0x21
+#define DEV2_THERM_THRMBATZONE_REG 0x22
+#define DEV2_THERM_SYS0ALERT0H_REG 0x23
+#define DEV2_THERM_SYS0ALERT0L_REG 0x24
+#define DEV2_THERM_SYS0ALERT1H_REG 0x25
+#define DEV2_THERM_SYS0ALERT1L_REG 0x26
+#define DEV2_THERM_SYS1ALERT0H_REG 0x27
+#define DEV2_THERM_SYS1ALERT0L_REG 0x28
+#define DEV2_THERM_SYS1ALERT1H_REG 0x29
+#define DEV2_THERM_SYS1ALERT1L_REG 0x2A
+#define DEV2_THERM_SYS2ALERT0H_REG 0x2B
+#define DEV2_THERM_SYS2ALERT0L_REG 0x2C
+#define DEV2_THERM_SYS2ALERT1H_REG 0x2D
+#define DEV2_THERM_SYS2ALERT1L_REG 0x2E
+#define DEV2_THERM_BAT0ALERT0H_REG 0x2F
+#define DEV2_THERM_BAT0ALERT0L_REG 0x30
+#define DEV2_THERM_BAT1ALERT0H_REG 0x31
+#define DEV2_THERM_BAT1ALERT0L_REG 0x32
+#define DEV2_THERM_PMICALERT0H_REG 0x33
+#define DEV2_THERM_PMICALERT0L_REG 0x34
+#define DEV2_SVID_DEV2_SETREGADR_REG 0x35
+#define DEV2_THERM_GPMEASALERTH_REG 0x36
+#define DEV2_THERM_GPMEASALERTL_REG 0x37
+#define DEV2_THERM_THRMRSLT0H_REG 0x38
+#define DEV2_THERM_THRMRSLT0L_REG 0x39
+#define DEV2_THERM_THRMRSLT1H_REG 0x3A
+#define DEV2_THERM_THRMRSLT1L_REG 0x3B
+#define DEV2_THERM_THRMRSLT2H_REG 0x3C
+#define DEV2_THERM_THRMRSLT2L_REG 0x3D
+#define DEV2_THERM_THRMRSLT3H_REG 0x3E
+#define DEV2_THERM_THRMRSLT3L_REG 0x3F
+#define DEV2_THERM_THRMRSLT4H_REG 0x40
+#define DEV2_THERM_THRMRSLT4L_REG 0x41
+#define DEV2_THERM_THRMRSLT5H_REG 0x42
+#define DEV2_THERM_THRMRSLT5L_REG 0x43
+#define DEV2_THERM_THRMZN0H_REG 0x44
+#define DEV2_THERM_THRMZN0L_REG 0x45
+#define DEV2_THERM_THRMZN1H_REG 0x46
+#define DEV2_THERM_THRMZN1L_REG 0x47
+#define DEV2_THERM_THRMZN2H_REG 0x48
+#define DEV2_THERM_THRMZN2L_REG 0x49
+#define DEV2_THERM_THRMZN3H_REG 0x4A
+#define DEV2_THERM_THRMZN3L_REG 0x4B
+#define DEV2_THERM_THRMZN4H_REG 0x4C
+#define DEV2_THERM_THRMZN4L_REG 0x4D
+#define DEV2_THERM_BATCRITCOLDH_REG 0x4E
+#define DEV2_THERM_BATCRITCOLDL_REG 0x4F
+#define DEV2_THERM_BATCRITHOTH_REG 0x50
+#define DEV2_THERM_BATCRITHOTL_REG 0x51
+#define DEV2_THERM_BATCRITH_REG 0x52
+#define DEV2_THERM_BATCRITL_REG 0x53
+#define DEV2_THERM_PMICCRITH_REG 0x54
+#define DEV2_THERM_PMICCRITL_REG 0x55
+#define DEV2_THERM_SYS0CRITH_REG 0x56
+#define DEV2_THERM_SYS0CRITL_REG 0x57
+#define DEV2_THERM_SYS1CRITH_REG 0x58
+#define DEV2_THERM_SYS1CRITL_REG 0x59
+#define DEV2_THERM_SYS2CRITH_REG 0x5A
+#define DEV2_THERM_SYS2CRITL_REG 0x5B
+#define DEV2_THERM_SYS0ALERT3H_REG 0x5C
+#define DEV2_THERM_SYS0ALERT3L_REG 0x5D
+#define DEV2_THERM_SYS1ALERT3H_REG 0x5E
+#define DEV2_THERM_SYS1ALERT3L_REG 0x5F
+#define DEV2_THERM_SYS2ALERT3H_REG 0x60
+#define DEV2_THERM_SYS2ALERT3L_REG 0x61
+#define DEV2_THERM_PMICALERT3H_REG 0x62
+#define DEV2_THERM_PMICALERT3L_REG 0x63
+#define DEV2_THERM_BAT0ALERT3H_REG 0x64
+#define DEV2_THERM_BAT0ALERT3L_REG 0x65
+#define DEV2_THERM_BAT1ALERT3H_REG 0x66
+#define DEV2_THERM_BAT1ALERT3L_REG 0x67
+#define DEV2_THERM_THRMCRITEN_REG 0x68
+#define DEV2_THERM_THRMALERT3EN_REG 0x69
+#define DEV2_THERM_THRMALERT3PAEN_REG 0x6A
+#define DEV2_IMON_CM_VCC0_MODE_CTRL_REG 0x6B
+#define DEV2_IMON_CM_VCC1_MODE_CTRL_REG 0x6C
+#define DEV2_IMON_CM_VCC_MODE_CTRL_REG 0x6D
+#define DEV2_IMON_CM_VNN_MODE_CTRL_REG 0x6E
+#define DEV2_IMON_CM_VNNAON_MODE_CTRL_REG 0x6F
+#define DEV2_IMON_CM_VDD1_MODE_CTRL_REG 0x70
+#define DEV2_IMON_CM_VDD2_MODE_CTRL_REG 0x71
+#define DEV2_IMON_CM_VCCRAM_MODE_CTRL_REG 0x72
+#define DEV2_IMON_CM_VMEM_MODE_CTRL_REG 0x73
+#define DEV2_IMON_CM_VFLEX_MODE_CTRL_REG 0x74
+#define DEV2_IMON_CM_VPROG1A_MODE_CTRL_REG 0x75
+#define DEV2_IMON_CM_VPROG1B_MODE_CTRL_REG 0x76
+#define DEV2_IMON_CM_VPROG1C_MODE_CTRL_REG 0x77
+#define DEV2_IMON_CM_VPROG1D_MODE_CTRL_REG 0x78
+#define DEV2_IMON_CM_VPROG2A_MODE_CTRL_REG 0x79
+#define DEV2_IMON_CM_VPROG2B_MODE_CTRL_REG 0x7A
+#define DEV2_IMON_CM_VPROG2C_MODE_CTRL_REG 0x7B
+#define DEV2_IMON_CM_VPROG3A_MODE_CTRL_REG 0x7C
+#define DEV2_IMON_CM_VPROG3B_MODE_CTRL_REG 0x7D
+#define DEV2_IMON_CM_TSPAN_CTRL_REG 0x7E
+#define DEV2_IMON_CM_LDO1_THRSHLD_REG 0x7F
+#define DEV2_IMON_CM_LDO2_THRSHLD_REG 0x80
+#define DEV2_IMON_CM_LDO3_THRSHLD_REG 0x81
+#define DEV2_IMON_CM_SMPS0_THRSHLD_REG 0x82
+#define DEV2_IMON_CM_SMPS1_THRSHLD_REG 0x83
+#define DEV2_IMON_CM_SMPS2_THRSHLD_REG 0x84
+#define DEV2_IMON_CM_SMPS3_THRSHLD_REG 0x85
+#define DEV2_IMON_CM_SMPS4_THRSHLD_REG 0x86
+#define DEV2_IMON_CM_SMPS5_THRSHLD_REG 0x87
+#define DEV2_IMON_CM_VCC0_DATA_REG 0x88
+#define DEV2_IMON_CM_VCC1_DATA_REG 0x89
+#define DEV2_IMON_CM_VCC_DATA_REG 0x8A
+#define DEV2_IMON_CM_VNN_DATA_REG 0x8B
+#define DEV2_IMON_CM_VNNAON_DATA_REG 0x8C
+#define DEV2_IMON_CM_VDD1_DATA_REG 0x8D
+#define DEV2_IMON_CM_VDD2_DATA_REG 0x8E
+#define DEV2_IMON_CM_VCCRAM_DATA_REG 0x8F
+#define DEV2_IMON_CM_VMEM_DATA_REG 0x90
+#define DEV2_IMON_CM_VFLEX_DATA_REG 0x91
+#define DEV2_IMON_CM_PROG1A_DATA_REG 0x92
+#define DEV2_IMON_CM_PROG1B_DATA_REG 0x93
+#define DEV2_IMON_CM_PROG1C_DATA_REG 0x94
+#define DEV2_IMON_CM_PROG1D_DATA_REG 0x95
+#define DEV2_IMON_CM_PROG2A_DATA_REG 0x96
+#define DEV2_IMON_CM_PROG2B_DATA_REG 0x97
+#define DEV2_IMON_CM_PROG2C_DATA_REG 0x98
+#define DEV2_IMON_CM_PROG3A_DATA_REG 0x99
+#define DEV2_IMON_CM_PROG3B_DATA_REG 0x9A
+#define DEV2_IMON_CM_VCC0_INT_LVL_REG 0x9B
+#define DEV2_IMON_CM_VCC1_INT_LVL_REG 0x9C
+#define DEV2_IMON_CM_VCC_INT_LVL_REG 0x9D
+#define DEV2_IMON_CM_VNN_INT_LVL_REG 0x9E
+#define DEV2_IMON_CM_VNNAON_INT_LVL_REG 0x9F
+#define DEV2_IMON_CM_VDD1_INT_LVL_REG 0xA0
+#define DEV2_IMON_CM_VDD2_INT_LVL_REG 0xA1
+#define DEV2_IMON_CM_VCCRAM_INT_LVL_REG 0xA2
+#define DEV2_IMON_CM_VMEM_INT_LVL_REG 0xA3
+#define DEV2_IMON_CM_VFLEX_INT_LVL_REG 0xA4
+#define DEV2_IMON_CM_VPROG1A_INT_LVL_REG 0xA5
+#define DEV2_IMON_CM_VPROG1B_INT_LVL_REG 0xA6
+#define DEV2_IMON_CM_VPROG1C_INT_LVL_REG 0xA7
+#define DEV2_IMON_CM_VPROG1D_INT_LVL_REG 0xA8
+#define DEV2_IMON_CM_VPROG2A_INT_LVL_REG 0xA9
+#define DEV2_IMON_CM_VPROG2B_INT_LVL_REG 0xAA
+#define DEV2_IMON_CM_VPROG2C_INT_LVL_REG 0xAB
+#define DEV2_IMON_CM_VPROG3A_INT_LVL_REG 0xAC
+#define DEV2_IMON_CM_VPROG3B_INT_LVL_REG 0xAD
+#define DEV2_IMON_CM_VROCIRQSTAT0_REG 0xAE
+#define DEV2_IMON_CM_VROCIRQSTAT1_REG 0xAF
+#define DEV2_IMON_CM_VROCIRQSTAT2_REG 0xB0
+#define DEV2_IMON_CM_VROCIRQSTAT3_REG 0xB1
+#define DEV2_RTC_VRTCCTRL_REG 0xB5
+#define DEV2_TMU_TMUIRQ_REG 0xB6
+#define DEV2_TMU_MTMUIRQ_REG 0xB7
+#define DEV2_TMU_TMUSTATUS_REG 0xB8
+#define DEV2_TMU_TMUCONFIG_REG 0xB9
+#define DEV2_TMU_SECONDS_REG 0xBA
+#define DEV2_TMU_SECONDSW_REG 0xBA
+#define DEV2_TMU_SECONDSSA_REG 0xBB
+#define DEV2_TMU_SECONDSWA_REG 0xBC
+#define DEV2_TMU_MINUTES_REG 0xBD
+#define DEV2_TMU_MINUTESW_REG 0xBD
+#define DEV2_TMU_MINUTESSA_REG 0xBE
+#define DEV2_TMU_MINUTESWA_REG 0xBF
+#define DEV2_TMU_HOURS_REG 0xC0
+#define DEV2_TMU_HOURSW_REG 0xC0
+#define DEV2_TMU_HOURSSA_REG 0xC1
+#define DEV2_TMU_HOURSWA_REG 0xC2
+#define DEV2_TMU_DWEEK_REG 0xC3
+#define DEV2_TMU_DWEEKW_REG 0xC3
+#define DEV2_TMU_DMONTH_REG 0xC4
+#define DEV2_TMU_DMONTHW_REG 0xC4
+#define DEV2_TMU_MONTH_REG 0xC5
+#define DEV2_TMU_MONTHW_REG 0xC5
+#define DEV2_TMU_YEAR_REG 0xC6
+#define DEV2_TMU_YEARW_REG 0xC6
+#define DEV2_TMU_STCB1_REG 0xC7
+#define DEV2_TMU_STCB2_REG 0xC8
+#define DEV2_TMU_STCB3_REG 0xC9
+#define DEV2_TMU_STCB4_REG 0xCA
+#define DEV2_TMU_DMONTHWA_REG 0xCB
+#define DEV2_CLK_CLKCONFIG_REG 0xCC
+#define DEV2_CLKGEN_FLLCTRL_REG 0xCD
+#define DEV2_CLKGEN_FLLDACSH_REG 0xCE
+#define DEV2_CLKGEN_FLLDACSL_REG 0xCF
+#define DEV2_CLKGEN_FLLDAC_STATUSH_REG 0xD0
+#define DEV2_CLKGEN_FLLDAC_STATUSL_REG 0xD1
+#define DEV2_CLKGEN_FLLFRQDIV_REG 0xD2
+#define DEV2_CLKGEN_CLK32CTRL_REG 0xD3
+#define DEV2_GPLED_GPLEDCTRL_REG 0xDF
+#define DEV2_GPLED_GPLEDFSM_REG 0xE0
+#define DEV2_GPLED_GPLEDPWM_REG 0xE1
+#define DEV2_INTVREF_INTVREFCTRL_REG 0xE2
+#define DEV2_INTVREF_IREFTRIM_REG 0xE3
+#define DEV2_INTVREF_VREFTRIM0_REG 0xE4
+#define DEV2_INTVREF_VREFTRIM1_REG 0xE5
+#define DEV2_COULCNT_CC_THRH_REG 0xE6
+#define DEV2_COULCNT_CC_THRL_REG 0xE7
+#define DEV2_COULCNT_CC_CURR_SHRTH_REG 0xE8
+#define DEV2_COULCNT_CC_CURR_SHRTL_REG 0xE9
+#define DEV2_COULCNT_CC_CURR_LNGH_REG 0xEA
+#define DEV2_COULCNT_CC_CURR_LNGL_REG 0xEB
+#define DEV2_COULCNT_CC_CTRL0_REG 0xEC
+#define DEV2_COULCNT_CC_CTRL1_REG 0xED
+#define DEV2_COULCNT_CC_DOWN_B3_REG 0xEE
+#define DEV2_COULCNT_CC_DOWN_B2_REG 0xEF
+#define DEV2_COULCNT_CC_DOWN_B1_REG 0xF0
+#define DEV2_COULCNT_CC_DOWN_B0_REG 0xF1
+#define DEV2_COULCNT_CC_UP_B3_REG 0xF2
+#define DEV2_COULCNT_CC_UP_B2_REG 0xF3
+#define DEV2_COULCNT_CC_UP_B1_REG 0xF4
+#define DEV2_COULCNT_CC_UP_B0_REG 0xF5
+#define DEV2_COULCNT_VBATMAXH_REG 0xF5
+#define DEV2_COULCNT_VBATMAXHW_REG 0xF6
+#define DEV2_COULCNT_VBATMAXL_REG 0xF6
+#define DEV2_COULCNT_VBATMAXLW_REG 0xF7
+#define DEV2_COULCNT_MAX_CURR_SHRTH_REG 0xF8
+#define DEV2_COULCNT_MAX_CURR_SHRTL_REG 0xF9
+#define DEV2_COULCNT_MAX_CURR_LNGH_REG 0xFA
+#define DEV2_COULCNT_MAX_CURR_LNGL_REG 0xFB
+#define DEV2_ID_PROVERSION_REG 0xFF
+
+// DEV 3 definitions
+
+#define DEV3_CRIT_PMICWDTCNT_REG 0x00
+#define DEV3_CRIT_PMICWDTTC_REG 0x01
+#define DEV3_CRIT_SCRITIRQ_REG 0x02
+#define DEV3_USB_USBIDCTRL_REG 0x05
+#define DEV3_USB_USBIDDETTYPE_REG 0x06
+#define DEV3_USB_USBPHYCTRL_REG 0x07
+#define DEV3_USB_USBRSTGPO_REG 0x08
+#define DEV3_USB_USBRSTGPI_REG 0x09
+#define DEV3_VCTRL_VSYSCTRL_REG 0x0C
+#define DEV3_VCTRL_VOTPCTRL_REG 0x0D
+#define DEV3_VCTRL_VXOCNT_REG 0x0E
+#define DEV3_SVID_DEV3_STATUS_1_REG 0x10
+#define DEV3_SVID_DEV3_STATUS_2_REG 0x11
+#define DEV3_CHARGER_CHGDETGPO_REG 0x12
+#define DEV3_CHARGER_CHGDETGPI_REG 0x13
+#define DEV3_CHARGER_DBPTIMEOUT_REG 0x14
+#define DEV3_CHARGER_DBPTIMER_REG 0x15
+#define DEV3_CHARGER_CHGRCTRL0_REG 0x16
+#define DEV3_CHARGER_CHGRCTRL1_REG 0x17
+#define DEV3_CHARGER_CHGRCTRL2_REG 0x18
+#define DEV3_CHARGER_CHGRSTATUS_REG 0x19
+#define DEV3_CHARGER_SCHGRIRQ_REG 0x1A
+#define DEV3_SVID_DEV3_STATUS2_LASTREAD_REG 0x1C
+#define DEV3_CHARGER_VBUSDETCTRL_REG 0x1D
+#define DEV3_CHARGER_VDCINDETCTRL_REG 0x1E
+#define DEV3_CHARGER_CHRLEDCTRL_REG 0x1F
+#define DEV3_CHARGER_CHRLEDFSM_REG 0x20
+#define DEV3_CHARGER_CHRLEDPWM_REG 0x21
+#define DEV3_CHARGER_CHRTTADDR_REG 0x22
+#define DEV3_CHARGER_CHRTTDATA_REG 0x23
+#define DEV3_CHARGER_I2COVRCTRL_REG 0x24
+#define DEV3_CHARGER_I2COVRDADDR_REG 0x25
+#define DEV3_CHARGER_I2COVROFFSET_REG 0x26
+#define DEV3_CHARGER_I2COVRWRDATA_REG 0x27
+#define DEV3_CHARGER_I2COVRRDDATA_REG 0x28
+#define DEV3_CHARGER_USBSRCDETSTATUS0_REG 0x29
+#define DEV3_CHARGER_USBSRCDETSTATUS1_REG 0x2A
+#define DEV3_CHARGER_CCSMCMDSKIP_REG 0x2B
+#define DEV3_CHARGER_CCSMSFTTIMER_REG 0x2C
+#define DEV3_CHARGER_SCCSMSFTTIMER_REG 0x2D
+#define DEV3_CHARGER_CHGRCTRL3_REG 0x2E
+#define DEV3_CHARGER_CHGDISCTRL_REG 0x2F
+#define DEV3_TLP_TLP1CTRL_REG 0x30
+#define DEV3_TLP_TLP1EVSTATUS0_REG 0x31
+#define DEV3_TLP_TLP1EVSTATUS1_REG 0x32
+#define DEV3_TLP_TLP1EVSTATUS2_REG 0x33
+#define DEV3_TLP_TLP1EVSTATUS3_REG 0x34
+#define DEV3_SVID_DEV3_SETREGADR_REG 0x35
+#define DEV3_TLP_TLP1TRACEINSTH_REG 0x36
+#define DEV3_TLP_TLP1TRACEINSTL_REG 0x37
+#define DEV3_TLP_TLP1INSTMEMADDRH_REG 0x38
+#define DEV3_TLP_TLP1INSTMEMADDRL_REG 0x39
+#define DEV3_TLP_TLP1INSTMEMDATAH_REG 0x3A
+#define DEV3_TLP_TLP1INSTMEMDATAHW_REG 0x3A
+#define DEV3_TLP_TLP1INSTMEMDATAL_REG 0x3B
+#define DEV3_TLP_TLP1COLDBOOTH_REG 0x3C
+#define DEV3_TLP_TLP1COLDBOOTL_REG 0x3D
+#define DEV3_TLP_TLP1COLDOFFH_REG 0x3E
+#define DEV3_TLP_TLP1COLDOFFL_REG 0x3F
+#define DEV3_TLP_TLP1COLDRSTH_REG 0x40
+#define DEV3_TLP_TLP1COLDRSTL_REG 0x41
+#define DEV3_TLP_TLP1WARMRSTH_REG 0x42
+#define DEV3_TLP_TLP1WARMRSTL_REG 0x43
+#define DEV3_TLP_TLP1ESBS0I1H_REG 0x44
+#define DEV3_TLP_TLP1ESBS0I1L_REG 0x45
+#define DEV3_TLP_TLP1ESBS0I1VNNH_REG 0x46
+#define DEV3_TLP_TLP1ESBS0I1VNNL_REG 0x47
+#define DEV3_TLP_TLP1ESBS0I1VNNLPH_REG 0x48
+#define DEV3_TLP_TLP1ESBS0I1VNNLPL_REG 0x49
+#define DEV3_TLP_TLP1ESBS0I2H_REG 0x4A
+#define DEV3_TLP_TLP1ESBS0I2L_REG 0x4B
+#define DEV3_TLP_TLP1ESBS0I3H_REG 0x4C
+#define DEV3_TLP_TLP1ESBS0I3L_REG 0x4D
+#define DEV3_TLP_TLP1ESBS0I3LPH_REG 0x4E
+#define DEV3_TLP_TLP1ESBS0I3LPL_REG 0x4F
+#define DEV3_TLP_TLP1EXSBH_REG 0x50
+#define DEV3_TLP_TLP1EXSBL_REG 0x51
+#define DEV3_TLP_TLP1ESBS0IXH_REG 0x52
+#define DEV3_TLP_TLP1ESBS0IXL_REG 0x53
+#define DEV3_TLP_TLP1ESBS3H_REG 0x54
+#define DEV3_TLP_TLP1ESBS3L_REG 0x55
+#define DEV3_TLP_TLP1EXSBS0IXH_REG 0x56
+#define DEV3_TLP_TLP1EXSBS0IXL_REG 0x57
+#define DEV3_TLP_TLP1EXSBS3H_REG 0x58
+#define DEV3_TLP_TLP1EXSBS3L_REG 0x59
+#define DEV3_TLP_TLP1MODEMRSTH_REG 0x5A
+#define DEV3_TLP_TLP1MODEMRSTL_REG 0x5B
+#define DEV3_TLP_TLP1VRSETTLED_REG 0x5C
+#define DEV3_TLP_TLP2CTRL_REG 0x61
+#define DEV3_TLP_TLP2EVSTATUS_REG 0x62
+#define DEV3_TLP_TLP2TRACEINST_REG 0x63
+#define DEV3_TLP_TLP2INSTMEMADDR_REG 0x64
+#define DEV3_TLP_TLP2INSTMEMDATA_REG 0x65
+#define DEV3_TLP_TLP2SYSTEMP_REG 0x66
+#define DEV3_TLP_TLP2BATTID_REG 0x67
+#define DEV3_TLP_TLP2BATTV_REG 0x68
+#define DEV3_TLP_TLP2USBID_REG 0x69
+#define DEV3_TLP_TLP2PEAK_REG 0x6A
+#define DEV3_TLP_TLP2GPMEAS_REG 0x6B
+#define DEV3_IMON_CM_VPROG1E_MODE_CTRL_REG 0x70
+#define DEV3_IMON_CM_VPROG1F_MODE_CTRL_REG 0x71
+#define DEV3_IMON_CM_VPROG2D_MODE_CTRL_REG 0x72
+#define DEV3_IMON_CM_VPROG4A_MODE_CTRL_REG 0x73
+#define DEV3_IMON_CM_VPROG4B_MODE_CTRL_REG 0x74
+#define DEV3_IMON_CM_VPROG4C_MODE_CTRL_REG 0x75
+#define DEV3_IMON_CM_VPROG4D_MODE_CTRL_REG 0x76
+#define DEV3_IMON_CM_VPROG5A_MODE_CTRL_REG 0x77
+#define DEV3_IMON_CM_VPROG5B_MODE_CTRL_REG 0x78
+#define DEV3_IMON_CM_VPROG6A_MODE_CTRL_REG 0x79
+#define DEV3_IMON_CM_VPROG6B_MODE_CTRL_REG 0x7A
+#define DEV3_IMON_CM_VPROG7A_MODE_CTRL_REG 0x7B
+#define DEV3_IMON_CM_LDO4_THRSHLD_REG 0x81
+#define DEV3_IMON_CM_LDO5_THRSHLD_REG 0x82
+#define DEV3_IMON_CM_LDO6_THRSHLD_REG 0x83
+#define DEV3_IMON_CM_PROG1E_DATA_REG 0x86
+#define DEV3_IMON_CM_PROG1F_DATA_REG 0x87
+#define DEV3_IMON_CM_PROG2D_DATA_REG 0x88
+#define DEV3_IMON_CM_PROG4A_DATA_REG 0x89
+#define DEV3_IMON_CM_PROG4B_DATA_REG 0x8A
+#define DEV3_IMON_CM_PROG4C_DATA_REG 0x8B
+#define DEV3_IMON_CM_PROG4D_DATA_REG 0x8C
+#define DEV3_IMON_CM_PROG5A_DATA_REG 0x8D
+#define DEV3_IMON_CM_PROG5B_DATA_REG 0x8E
+#define DEV3_IMON_CM_PROG6A_DATA_REG 0x8F
+#define DEV3_IMON_CM_PROG6B_DATA_REG 0x90
+#define DEV3_IMON_CM_PROG7A_DATA_REG 0x91
+#define DEV3_IMON_CM_VPROG1E_INT_LVL_REG 0x97
+#define DEV3_IMON_CM_VPROG1F_INT_LVL_REG 0x98
+#define DEV3_IMON_CM_VPROG2D_INT_LVL_REG 0x99
+#define DEV3_IMON_CM_VPROG4A_INT_LVL_REG 0x9A
+#define DEV3_IMON_CM_VPROG4B_INT_LVL_REG 0x9B
+#define DEV3_IMON_CM_VPROG4C_INT_LVL_REG 0x9C
+#define DEV3_IMON_CM_VPROG4D_INT_LVL_REG 0x9D
+#define DEV3_IMON_CM_VPROG5A_INT_LVL_REG 0x9E
+#define DEV3_IMON_CM_VPROG5B_INT_LVL_REG 0x9F
+#define DEV3_IMON_CM_VPROG6A_INT_LVL_REG 0xA0
+#define DEV3_IMON_CM_VPROG6B_INT_LVL_REG 0xA1
+#define DEV3_IMON_CM_VPROG7A_INT_LVL_REG 0xA2
+
+// DEV 4 definitions
+
+#define DEV4_SVID_DEV4_STATUS_1_REG 0x10
+#define DEV4_SVID_DEV4_STATUS_2_REG 0x11
+#define DEV4_SVID_DEV4_STATUS2_LASTREAD_REG 0x1C
+#define DEV4_SVID_DEV4_SETREGADR_REG 0x35
+#define DEV4_VENDOR_VENDCTL0_REG 0x36
+#define DEV4_VENDOR_VENDCTL1_REG 0x37
+#define DEV4_VENDOR_VENDCTL2_REG 0x38
+#define DEV4_VENDOR_VENDCTL3_REG 0x39
+#define DEV4_VENDOR_NVM_MB_ADDRH_REG 0x3A
+#define DEV4_VENDOR_NVM_MB_ADDRL_REG 0x3B
+#define DEV4_VENDOR_NVM_MB_DATA_REG 0x3C
+#define DEV4_VENDOR_NVMDBUF0_REG 0x3D
+#define DEV4_VENDOR_NVMDBUF1_REG 0x3E
+#define DEV4_VENDOR_NVMDBUF2_REG 0x3F
+#define DEV4_VENDOR_NVMDBUF3_REG 0x40
+#define DEV4_VENDOR_NVMDBUF4_REG 0x41
+#define DEV4_VENDOR_NVMDBUF5_REG 0x42
+#define DEV4_VENDOR_NVMDBUF6_REG 0x43
+#define DEV4_VENDOR_NVMDBUF7_REG 0x44
+#define DEV4_VENDOR_NVMDBUF8_REG 0x45
+#define DEV4_VENDOR_NVMDBUF9_REG 0x46
+#define DEV4_VENDOR_NVMDBUF10_REG 0x47
+#define DEV4_VENDOR_NVMDBUF11_REG 0x48
+#define DEV4_VENDOR_NVMDBUF12_REG 0x49
+#define DEV4_VENDOR_NVMDBUF13_REG 0x4A
+#define DEV4_VENDOR_NVMDBUF14_REG 0x4B
+#define DEV4_VENDOR_NVMDBUF15_REG 0x4C
+#define DEV4_VENDOR_NVMDBUF16_REG 0x4D
+#define DEV4_VENDOR_NVMDBUF17_REG 0x4E
+#define DEV4_VENDOR_NVMDBUF18_REG 0x4F
+#define DEV4_VENDOR_NVMDBUF19_REG 0x50
+#define DEV4_VENDOR_NVMDBUF20_REG 0x51
+#define DEV4_VENDOR_NVMDBUF21_REG 0x52
+#define DEV4_VENDOR_NVMDBUF22_REG 0x53
+#define DEV4_VENDOR_NVMDBUF23_REG 0x54
+#define DEV4_VENDOR_NVMDBUF24_REG 0x55
+#define DEV4_VENDOR_NVMDBUF25_REG 0x56
+#define DEV4_VENDOR_NVMDBUF26_REG 0x57
+#define DEV4_VENDOR_NVMDBUF27_REG 0x58
+#define DEV4_VENDOR_NVMDBUF28_REG 0x59
+#define DEV4_VENDOR_NVMDBUF29_REG 0x5A
+#define DEV4_VENDOR_NVMDBUF30_REG 0x5B
+#define DEV4_VENDOR_NVMDBUF31_REG 0x5C
+#define DEV4_VENDOR_NVMDBUF32_REG 0x5D
+#define DEV4_VENDOR_NVMDBUF33_REG 0x5E
+#define DEV4_VENDOR_NVMCTL0_REG 0x5F
+#define DEV4_VENDOR_NVMCTL1_REG 0x60
+#define DEV4_VENDOR_OTPMR_REG 0x61
+#define DEV4_VENDOR_OTPMRA_RD1_REG 0x62
+#define DEV4_VENDOR_OTPMRA_RD2_REG 0x63
+#define DEV4_VENDOR_OTPMRB0_RD1_REG 0x64
+#define DEV4_VENDOR_OTPMRB0_RD2_REG 0x65
+#define DEV4_VENDOR_OTPMRB1_REG 0x66
+#define DEV4_VENDOR_NVMSTAT0_REG 0x67
+#define DEV4_VENDOR_SOAKING_STAT0_REG 0x68
+#define DEV4_VENDOR_SOAKING_STAT1_REG 0x69
+#define DEV4_VENDOR_NVM_USAGE_STATH_REG 0x6A
+#define DEV4_VENDOR_NVM_USAGE_STATL_REG 0x6B
+#define DEV4_VENDOR_CODSRC_REG 0x6C
+#define DEV4_VENDOR_ISOCTRL_REG 0x6D
+#define DEV4_VENDOR_OTPCONFIG_REG 0x6E
+#define DEV4_VIRQ_VENDIRQLVL1_REG 0x77
+#define DEV4_VIRQ_NVMVIRQ_REG 0x78
+#define DEV4_VIRQ_ADCTLP2VIRQ_REG 0x79
+#define DEV4_VIRQ_I2CSIFVIRQ_REG 0x7A
+#define DEV4_VIRQ_REGBUSVIRQ_REG 0x7B
+#define DEV4_VIRQ_CHGRVIRQ_REG 0x7C
+#define DEV4_VIRQ_TLP1VIRQ_REG 0x7D
+#define DEV4_VIRQ_DCDCVIRQ0_REG 0x7E
+#define DEV4_VIRQ_DCDCVIRQ1_REG 0x7F
+#define DEV4_VIRQ_VROCIRQ0_REG 0x80
+#define DEV4_VIRQ_VROCIRQ1_REG 0x81
+#define DEV4_VIRQ_VROCIRQ2_REG 0x82
+#define DEV4_VIRQ_VROCIRQ3_REG 0x83
+#define DEV4_VIRQ_MVENDIRQLVL1_REG 0x84
+#define DEV4_VIRQ_MNVMVIRQ_REG 0x85
+#define DEV4_VIRQ_MADCTLP2VIRQ_REG 0x86
+#define DEV4_VIRQ_MI2CSIFVIRQ_REG 0x87
+#define DEV4_VIRQ_MREGBUSVIRQ_REG 0x88
+#define DEV4_VIRQ_MCHGRVIRQ_REG 0x89
+#define DEV4_VIRQ_MTLP1VIRQ_REG 0x8A
+#define DEV4_VIRQ_MDCDCVIRQ0_REG 0x8B
+#define DEV4_VIRQ_MDCDCVIRQ1_REG 0x8C
+#define DEV4_VIRQ_MVROCIRQ0_REG 0x8D
+#define DEV4_VIRQ_MVROCIRQ1_REG 0x8E
+#define DEV4_VIRQ_MVROCIRQ2_REG 0x8F
+#define DEV4_VIRQ_MVROCIRQ3_REG 0x90
+#define DEV4_VIRQ_M_VEND_INT_REG 0x91
+#define DEV4_VIRQ_VROCIRQ4_REG 0x92
+#define DEV4_VIRQ_MVROCIRQ4_REG 0x93
+#define DEV4_TEST_TST_STARTUP_REG 0x9A
+#define DEV4_TEST_TST_FREQ_DIV0_REG 0x9B
+#define DEV4_TEST_TST_FREQ_DIV1_REG 0x9C
+#define DEV4_TEST_TST_FREQ_SEL0_REG 0x9D
+#define DEV4_TEST_TST_FREQ_SEL1_REG 0x9E
+#define DEV4_TEST_TST_COUNT_CTRL0_REG 0x9F
+#define DEV4_TEST_TST_COUNT_CTRL1_REG 0xA0
+#define DEV4_TEST_TST_COUNT0_TIME_REG 0xA1
+#define DEV4_TEST_TST_COUNT1_TIME_REG 0xA2
+#define DEV4_TEST_TST_COUNT0_REG 0xA3
+#define DEV4_TEST_TST_COUNT1_REG 0xA4
+#define DEV4_TEST_TST_VINMON_REG 0xA5
+#define DEV4_TEST_TST_VINMONRSLT_REG 0xA6
+#define DEV4_TEST_TST_SRCDET0_REG 0xA7
+#define DEV4_TEST_TST_SRCDET1_REG 0xA8
+#define DEV4_TEST_TST_USB_REG 0xA9
+#define DEV4_TEST_TST_VSWITCH0_REG 0xAA
+#define DEV4_TEST_TST_VSWITCH1_REG 0xAB
+#define DEV4_TEST_VUSBPHY_CP_REG 0xAC
+#define DEV4_TEST_VUSBPHY_CP_VOUT_REG 0xAD
+#define DEV4_TEST_TST_ATE_STRTUP_REG 0xAE
+#define DEV4_TEST_GPADC_TEST0_REG 0xAF
+#define DEV4_TEST_GPADC_TEST1_REG 0xB0
+#define DEV4_TEST_GPADC_PKTST_REG 0xB1
+#define DEV4_TEST_COMPTEST0_REG 0xB2
+#define DEV4_TEST_COMPTEST1_REG 0xB3
+#define DEV4_TEST_TST_ATE_CFG_REG 0xB4
+#define DEV4_TEST_TST_ATE_REF0_REG 0xB5
+#define DEV4_TEST_TST_ATE_REF1_REG 0xB6
+#define DEV4_DEBUG_PMICSPARE01_AO_REG 0xC0
+#define DEV4_DEBUG_PMICSPARE02_AI_REG 0xC1
+#define DEV4_DEBUG_PMICSPARE03_AO_REG 0xC2
+#define DEV4_DEBUG_PMICSPARE04_AI_REG 0xC3
+#define DEV4_DEBUG_PMICSPARE05_REG 0xC4
+#define DEV4_DEBUG_PMICSPARE06_REG 0xC5
+#define DEV4_DEBUG_PMICSPARE07_REG 0xC6
+#define DEV4_DEBUG_PMICSPARE08_REG 0xC7
+#define DEV4_DEBUG_PMICSPARE09_REG 0xC8
+#define DEV4_DEBUG_PMICSPARE10_REG 0xC9
+#define DEV4_DEBUG_PMICSPARE11_REG 0xCA
+#define DEV4_DEBUG_PMICSPARE12_REG 0xCB
+#define DEV4_DEBUG_I2C_HS_TIMING_REG 0xCC
+#define DEV4_DEBUG_DBGMON1_BLK_SEL_REG 0xCD
+#define DEV4_DEBUG_DBGMON1_SIG_SEL_REG 0xCE
+#define DEV4_DEBUG_DBGMON2_BLK_SEL_REG 0xCF
+#define DEV4_DEBUG_DBGMON2_SIG_SEL_REG 0xD0
+#define DEV4_DEBUG_DBGMON3_BLK_SEL_REG 0xD1
+#define DEV4_DEBUG_DBGMON3_SIG_SEL_REG 0xD2
+#define DEV4_DEBUG_DBGMON4_BLK_SEL_REG 0xD3
+#define DEV4_DEBUG_DBGMON4_SIG_SEL_REG 0xD4
+#define DEV4_DEBUG_PMICDBGCTRL1_REG 0xD5
+#define DEV4_DEBUG_PMICDBGCTRL2_REG 0xD6
+#define DEV4_DEBUG_REGBUS_ERR_CTL_REG 0xD7
+#define DEV4_DEBUG_REGBUS_ERR_STATUS_REG 0xD8
+#define DEV4_DEBUG_REGBUS_ERR_ADDRH_REG 0xD9
+#define DEV4_DEBUG_REGBUS_ERR_ADDRL_REG 0xDA
+#define DEV4_DEBUG_ANAMON0CTL0_REG 0xDB
+#define DEV4_DEBUG_ANAMON0CTL1_REG 0xDC
+#define DEV4_DEBUG_ANAMON1CTL0_REG 0xDD
+#define DEV4_DEBUG_ANAMON1CTL1_REG 0xDE
+#define DEV4_DEBUG_VCOMPTEST_REG 0xDF
+#define DEV4_DEBUG_DBG_USBBC1_REG 0xE0
+#define DEV4_DEBUG_DBG_USBBC2_REG 0xE1
+#define DEV4_DEBUG_DBG_USBBCSTAT_REG 0xE2
+#define DEV4_DEBUG_ANAMON2CTL0_REG 0xE3
+#define DEV4_DEBUG_ANAMON2CTL1_REG 0xE4
+
+// DEV5 definitions
+
+#define DEV5_ID_ID0_REG 0x00
+#define DEV5_ID_ID1_REG 0x01
+#define DEV5_IRQ_IRQLVL1_REG 0x02
+#define DEV5_IRQ_PWRSRCIRQ_REG 0x03
+#define DEV5_IRQ_THRMIRQ0_REG 0x04
+#define DEV5_IRQ_THRMIRQ1_REG 0x05
+#define DEV5_IRQ_THRMIRQ2_REG 0x06
+#define DEV5_IRQ_BCUIRQ_REG 0x07
+#define DEV5_IRQ_ADCIRQ_REG 0x08
+#define DEV5_IRQ_CHGRIRQ_REG 0x0A
+#define DEV5_IRQ_GPIO0IRQ_REG 0x0B
+#define DEV5_IRQ_GPIO1IRQ_REG 0x0C
+#define DEV5_IRQ_MTHRMIRQ0_REG 0x0D
+#define DEV5_IRQ_MIRQLVL1_REG 0x0E
+#define DEV5_IRQ_MPWRSRCIRQ_REG 0x0F
+#define DEV5_SVID_DEV5_STATUS_1_REG 0x10
+#define DEV5_SVID_DEV5_STATUS_2_REG 0x11
+#define DEV5_IRQ_MTHRMIRQ1_REG 0x12
+#define DEV5_IRQ_MTHRMIRQ2_REG 0x13
+#define DEV5_IRQ_MBCUIRQ_REG 0x14
+#define DEV5_IRQ_MADCIRQ_REG 0x15
+#define DEV5_IRQ_MCHGRIRQ_REG 0x17
+#define DEV5_IRQ_MGPIO0IRQ_REG 0x19
+#define DEV5_IRQ_MGPIO1IRQ_REG 0x1A
+#define DEV5_SVID_DEV5_STATUS2_LASTREAD_REG 0x1C
+#define DEV5_PWRSRC_SPWRSRC_REG 0x1E
+#define DEV5_EXTCTRL_REGLOCK_REG 0x1F
+#define DEV5_RESET_RESETSRC0_REG 0x20
+#define DEV5_RESET_RESETSRC1_REG 0x21
+#define DEV5_WAKE_WAKESRC_REG 0x22
+#define DEV5_PWRSRC_LOWBATTDET0_REG 0x23
+#define DEV5_PWRSRC_LOWBATTDET1_REG 0x24
+#define DEV5_PWRSRC_PSDETCTRL_REG 0x25
+#define DEV5_PB_PBCONFIG1_REG 0x26
+#define DEV5_PB_PBSTATUS_REG 0x27
+#define DEV5_PB_UBSTATUS_REG 0x28
+#define DEV5_EXTCTRL_MODEMCTRL_REG 0x29
+#define DEV5_EXTCTRL_BBCHGRCFG_REG 0x2A
+#define DEV5_GPIO_GPIO0P0CTLO_REG 0x2B
+#define DEV5_GPIO_GPIO0P1CTLO_REG 0x2C
+#define DEV5_GPIO_GPIO0P2CTLO_REG 0x2D
+#define DEV5_GPIO_GPIO0P3CTLO_REG 0x2E
+#define DEV5_GPIO_GPIO0P5CTLO_REG 0x30
+#define DEV5_GPIO_GPIO0P6CTLO_REG 0x31
+#define DEV5_GPIO_GPIO0P0CTLI_REG 0x33
+#define DEV5_GPIO_GPIO0P2CTLI_REG 0x34
+#define DEV5_SVID_DEV5_SETREGADR_REG 0x35
+#define DEV5_GPIO_GPIO0P3CTLI_REG 0x36
+#define DEV5_IRQ_CRITIRQ_REG 0x37
+#define DEV5_GPIO_GPIO0P5CTLI_REG 0x38
+#define DEV5_GPIO_GPIO0P6CTLI_REG 0x39
+#define DEV5_GPIO_GPIO1P0CTLO_REG 0x3B
+#define DEV5_GPIO_GPIO1P1CTLO_REG 0x3C
+#define DEV5_GPIO_GPIO1P0CTLI_REG 0x43
+#define DEV5_GPIO_GPIO1P1CTLI_REG 0x44
+#define DEV5_RESET_COLDRST_REG 0x53
+#define DEV5_VREG_V1P8ACNT_REG 0x56
+#define DEV5_VREG_V1P8SXCNT_REG 0x57
+#define DEV5_VREG_VDDQCNT_REG 0x58
+#define DEV5_VREG_V1P2ACNT_REG 0x59
+#define DEV5_VREG_V1P2SXCNT_REG 0x5A
+#define DEV5_VREG_V1P8AVSEL_REG 0x5B
+#define DEV5_VREG_VDDQVSEL_REG 0x5C
+#define DEV5_VREG_V2P8SXCNT_REG 0x5D
+#define DEV5_VREG_V3P3ACNT_REG 0x5E
+#define DEV5_VREG_V3P3SDCNT_REG 0x5F
+#define DEV5_VREG_VNNCNT_REG 0x63
+#define DEV5_VREG_VCC0CNT_REG 0x64
+#define DEV5_VREG_VCC1CNT_REG 0x65
+#define DEV5_VREG_VGGCNT_REG 0x66
+#define DEV5_VREG_VSDIOCNT_REG 0x67
+#define DEV5_VREG_V3P3AVSEL_REG 0x68
+#define DEV5_VREG_VLDOCNT_REG 0x69
+#define DEV5_VREG_VSWITCHCNT0_REG 0x6A
+#define DEV5_VREG_VSWITCHCNT1_REG 0x6C
+#define DEV5_ID_FWREV_REG 0x6D
+#define DEV5_WAKE_SRCWAKECFG_REG 0x8B
+#define DEV5_VREG_VPROG1ACNT_REG 0x90
+#define DEV5_VREG_VPROG1BCNT_REG 0x91
+#define DEV5_VREG_VPROG1FCNT_REG 0x95
+#define DEV5_VREG_VPROG2DCNT_REG 0x99
+#define DEV5_VREG_VPROG3ACNT_REG 0x9A
+#define DEV5_VREG_VPROG3BCNT_REG 0x9B
+#define DEV5_VREG_VPROG4ACNT_REG 0x9C
+#define DEV5_VREG_VPROG4BCNT_REG 0x9D
+#define DEV5_VREG_VPROG4CCNT_REG 0x9E
+#define DEV5_VREG_VPROG4DCNT_REG 0x9F
+#define DEV5_VREG_VPROG5ACNT_REG 0xA0
+#define DEV5_VREG_VPROG5BCNT_REG 0xA1
+#define DEV5_VREG_VPROG6ACNT_REG 0xA2
+#define DEV5_VREG_VPROG6BCNT_REG 0xA3
+#define DEV5_VREG_VPROG7ACNT_REG 0xA4
+#define DEV5_BCU_VWARNA_CFG_REG 0xB4
+#define DEV5_BCU_VWARNB_CFG_REG 0xB5
+#define DEV5_BCU_VCRIT_CFG_REG 0xB6
+#define DEV5_BCU_BCUDISB_BEH_REG 0xB8
+#define DEV5_BCU_BCUDISCRIT_BEH_REG 0xB9
+#define DEV5_BCU_BCUVSYS_DRP_BEH_REG 0xBA
+#define DEV5_BCU_SBCUIRQ_REG 0xBB
+#define DEV5_BCU_SBCUCTRL_REG 0xBC
+#define DEV5_VREG_VPROG1AVSEL_REG 0xC0
+#define DEV5_VREG_VPROG1BVSEL_REG 0xC1
+#define DEV5_VREG_V1P8SXVSEL_REG 0xC2
+#define DEV5_VREG_V1P2SXVSEL_REG 0xC3
+#define DEV5_VREG_V1P2AVSEL_REG 0xC4
+#define DEV5_VREG_VPROG1FVSEL_REG 0xC5
+#define DEV5_VREG_VSDIOVSEL_REG 0xC6
+#define DEV5_VREG_V2P8SXVSEL_REG 0xC7
+#define DEV5_VREG_V3P3SDVSEL_REG 0xC8
+#define DEV5_VREG_VPROG2DVSEL_REG 0xC9
+#define DEV5_VREG_VPROG3AVSEL_REG 0xCA
+#define DEV5_VREG_VPROG3BVSEL_REG 0xCB
+#define DEV5_VREG_VPROG4AVSEL_REG 0xCC
+#define DEV5_VREG_VPROG4BVSEL_REG 0xCD
+#define DEV5_VREG_VPROG4CVSEL_REG 0xCE
+#define DEV5_VREG_VPROG4DVSEL_REG 0xCF
+#define DEV5_VREG_VPROG5AVSEL_REG 0xD0
+#define DEV5_VREG_VPROG5BVSEL_REG 0xD1
+#define DEV5_VREG_VPROG6AVSEL_REG 0xD2
+#define DEV5_VREG_VPROG6BVSEL_REG 0xD3
+#define DEV5_VREG_VPROG7AVSEL_REG 0xD4
+#define DEV5_IRQ_THRMIRQ3_REG 0xD9
+#define DEV5_IRQ_MTHRMIRQ3_REG 0xDA
+#define DEV5_PB_PBCONFIG2_REG 0xDB
+#define DEV5_PMON_PSOCMONCTL_REG 0xDC
+#define DEV5_PMON_PSOCRSLTH_REG 0xDD
+#define DEV5_PMON_PSOCRSLTL_REG 0xDE
+#define DEV5_PMON_SOC_PALERTH_REG 0xE3
+#define DEV5_PMON_SOC_PALERTL_REG 0xE4
+#define DEV5_WAKE_WAKESRC2_REG 0xE5
+#define DEV5_WAKE_SPLTIMER_REG 0xE6
+#define DEV5_WAKE_SSPLTIMER_REG 0xE7
+#define DEV5_PWRSRC_BATTDETCTRL0_REG 0xF0
+#define DEV5_PWRSRC_BATTDETCTRL1_REG 0xF1
+#define DEV5_EXTCTRL_SOCCTRL_REG 0xF8
+#define DEV5_IRQ_MCRITIRQ_REG 0xFA
+#define DEV5_BCU_ICCMAXVCC_CFG_REG 0xFB
+#define DEV5_BCU_ICCMAXVNN_CFG_REG 0xFC
+#define DEV5_BCU_ICCMAXVGG_CFG_REG 0xFD
+#define DEV5_IRQ_MSVIDALERT_REG 0xFE
+
+/*
+USB Type C PD controller I2C and register definitions
+ToDo -- Move to EM code space
+*/
+
+#define USB_TYPEC_PD_CHANNEL_NUMBER 0x0
+#define USB_TYPEC_PD_SLAVE_ADDRESS 0x22
+#define USB_TYPEC_PD_POWER_REG 0x0B
+#define USB_TYPEC_PD_SWITCH0_REG 0x02
+#define USB_TYPEC_PD_MASK0_REG 0x0A
+#define USB_TYPEC_PD_STS_REG 0x40
+#define USB_TYPEC_PD_INTR_REG 0x42
+
+typedef struct _WC_PMIC_CONFIGURATION {
+ UINT8 Offset;
+ UINT8 Value;
+}WC_PMIC_CONFIGURATION;
+
+EFI_STATUS ConfigureWcPmicDev2();
+
+EFI_STATUS ConfigureWcPmicDev5();
+
+/*
+For DDR3L memory
+Sequence needs to happen before MRC init.
+
+Write to DEV5_VDDQVSEL_REG to change voltage from 1.24V to 1.35V.
+->Write 0x6E to offset 0x5C
+Enable V1P2A LDO
+->Write 0x01 to DEV_V1P2ACNT_REG
+*/
+EFI_STATUS
+EFIAPI
+VGGWrite (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+UINT8
+EFIAPI
+WcPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+WcPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+WcPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+WcPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+WcPmicGetBATID (void);
+
+UINT8
+EFIAPI
+WcPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+WcPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+WcPmicGetFABID(void);
+
+UINT16
+EFIAPI
+WcPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+WcPmicGetResetCause (void);
+
+VOID
+EFIAPI
+WcPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+WcPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGpioToggleForLpcConfig(void);
+
+VOID
+WcPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicSetVIDDecayWA (void);
+
+VOID
+WcProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicNVMUpdate(void);
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h new file mode 100644 index 0000000000..f509eed632 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h @@ -0,0 +1,315 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_CC_P_H_
+#define _PMIC_REG_CC_P_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/I2CLib.h>
+#include <Library/PmicLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+
+#define DELAY_BETWEEN_INSTRUCTION_1 50
+#define DELAY_BETWEEN_INSTRUCTION 10
+#define R_PMIC_PBCONFIG 0x26
+#define MASK_PMIC_PB_DISABLE 0xf0 //disable power button
+#define MASK_PBCONFIG_FCOT 0x0f //last 4 bits corresponds to FCOT
+
+RegInit_st g_Diaglog_ThermRegInit[]=
+{
+ {PMIC_REG_SYS0_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS0_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x0},
+ {PMIC_REG_SYS0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS1_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x0},
+ {PMIC_REG_SYS1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x0},
+
+ {PMIC_REG_SYS2_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0xCD}, // A0_P/A0_Alert/67 C
+ {PMIC_REG_SYS2_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x08},
+ {PMIC_REG_SYS2_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS2_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x0},
+
+ {PMIC_REG_TS_ENABLE, REG_OVERRIDE, 0xFF, 0x3f}, //enable all thermsistors
+};
+RegInit_st g_Rohm_ThermRegInit[]=
+{
+ {PMIC_REG_SYS0_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0xCD}, // the values are from Peter on B0 PO
+ {PMIC_REG_SYS0_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x08}, // enabled but threshold is 0
+ {PMIC_REG_SYS0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C}, //
+ {PMIC_REG_SYS0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS1_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x00},
+ {PMIC_REG_SYS1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS2_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x4C}, // A0_P/A0_Alert/67 C
+ {PMIC_REG_SYS2_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x00},
+ {PMIC_REG_SYS2_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS2_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_BAT0_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x3D}, // battery #0 alert0 50C (disabled)
+ {PMIC_REG_BAT0_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x97},
+ {PMIC_REG_BAT0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x3D}, // alert 1:45C
+ {PMIC_REG_BAT0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0xCA},
+ {PMIC_REG_BAT0_THRMCRIT_H, REG_OVERRIDE, 0xFF, 0x6A}, // 75C
+ {PMIC_REG_BAT0_THRMCRIT_L, REG_OVERRIDE, 0xFF, 0xF0}, //-55C
+
+ {PMIC_REG_BAT1_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x3D}, //disabled
+ {PMIC_REG_BAT1_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x97},
+ {PMIC_REG_BAT1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x3D},
+ {PMIC_REG_BAT1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0xCA},
+ {PMIC_REG_BAT1_THRMCRIT_H, REG_OVERRIDE, 0xFF, 0x6A},
+ {PMIC_REG_BAT1_THRMCRIT_L, REG_OVERRIDE, 0xFF, 0xF0},
+
+ {PMIC_REG_PMIC_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0xFE}, // 110C
+ {PMIC_REG_PMIC_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x17},
+ {PMIC_REG_PMIC_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x7E}, // 100C
+ {PMIC_REG_PMIC_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x2A},
+ {PMIC_REG_PMIC_THRMCRIT, REG_OVERRIDE, 0xFF, 0xFF}, // 123C overflow MSB1 bit in the design. so only value higher than 123 is acceptable.
+
+ {PMIC_REG_TS_ENABLE, REG_OVERRIDE, 0xFF, 0x3F}, // Enable all thermistors
+
+ {PMIC_REG_THRMMONCTL0, REG_OVERRIDE, 0xFF, 0xB}, //enable thermal automatic monitoring timer, 1s sample interval
+};
+
+GpioCfg_st g_GPIO_cfg[]= {
+ {"GPIO0P0", PMIC_REG_GPIO0P0CTLO, PMIC_REG_GPIO0P0CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//"Volumn up" (debounce enable)
+ {"GPIO0P1", PMIC_REG_GPIO0P1CTLO, PMIC_REG_GPIO0P1CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//"Volumn down" (debounce enable)
+
+ {"GPIO1P0", PMIC_REG_GPIO1P0CTLO, PMIC_REG_GPIO1P0CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU|PMIC_MASK_ALTFUNCEN), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) }, //enable altfunc "UIBTN_B" home screen (debounce enable)
+};
+
+GpioCfg_st g_Pmic_Gpio_Lpc_Cfg[]= {
+ {"GPIO1P1", PMIC_REG_GPIO1P1CTLO, PMIC_REG_GPIO1P1CTLI, DIR_OUTPUT, INTERRUPT_DIS, (PMIC_MASK_DRV|PMIC_MASK_RVAL_50K_PD|PMIC_MASK_DIR), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//PMIC_GPIO_1_LPC GPO low 0x3c:0x34
+
+};
+
+RegInit_st g_IntrRegInit[]=
+{
+ {PMIC_REG_MGPIO0IRQS0, REG_OVERRIDE, 0xff, 0xff}, //disable all GPIO interrupts
+ {PMIC_REG_MGPIO1IRQS0, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MGPIO0IRQSX, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MGPIO1IRQSX, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MADCIRQ0, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MADCIRQ1, REG_OVERRIDE, 0x1f, 0x1f},
+ {PMIC_REG_MCHGRIRQS0, REG_CLEAR, PMIC_MASK_MCHGR, PMIC_MASK_MCHGR}, //enable external charger interrupt
+ {PMIC_REG_MCHGRIRQSX, REG_CLEAR, PMIC_MASK_MCHGR, PMIC_MASK_MCHGR}, //enable external charger interrupt
+ {PMIC_REG_MPWRSRCIRQS0, REG_CLEAR, (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET), (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET) }, //enable power src interrupt
+ {PMIC_REG_MPWRSRCIRQSX, REG_CLEAR, (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET), (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET) },
+ {PMIC_REG_MIRQLVL1, REG_OVERRIDE, PMIC_MASK_ALL_IRQ, (PMIC_MASK_MPWRSRC|PMIC_MASK_MCHGRINT|PMIC_MASK_MADC|PMIC_MASK_MGPIO)}, //only enable 4kinds of intrs
+ {PMIC_REG_MTHRMIRQ0, REG_OVERRIDE, 0xff, 0xff}, //disable all THerm intrs
+ {PMIC_REG_MTHRMIRQ1, REG_OVERRIDE, 0xf, 0xf},
+ {PMIC_REG_MTHRMIRQ2, REG_OVERRIDE, 0x3f, 0x3f},
+
+ {PMIC_REG_GPIO0IRQ, REG_OVERRIDE, 0xff, 0xff}, //write clear
+ {PMIC_REG_GPIO1IRQ, REG_OVERRIDE, 0xff, 0xff},
+};
+
+RegInit_st g_BcuRegInit[]=
+{
+ {PMIC_REG_VWARNA_CFG, REG_CLEAR, PMIC_MASK_VWARNA_EN, PMIC_MASK_VWARNA_EN}, //TODO: require meaningful value from HW teams
+ {PMIC_REG_VWARNB_CFG, REG_CLEAR, PMIC_MASK_VWARNB_EN, PMIC_MASK_VWARNB_EN}, //disable VWENB
+ {PMIC_REG_VCRIT_CFG, REG_CLEAR, PMIC_MASK_VCRIT_EN, PMIC_MASK_VCRIT_EN}, //disable VCRIT
+ {PMIC_REG_BCUDISA_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUDISB_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUDISCRIT_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUPROCHOT_B_BEH,REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_MBCUIRQ, REG_OVERRIDE, PMIC_MASK_MBCU_ALL, PMIC_MASK_MBCU_ALL }, //mask all
+};
+
+RegInit_st g_MiscRegInit[]=
+{
+ // V2P8SX rail drops to 2.56V with Camera enabled. The voltage is at 2.8v on startup and drops to 2.56V when the camera is brought out of reset.
+ // PMIC_REG_V1P8SXCNT = 0x5D : The default and correct value is 011 for 2.8V. We are overriding the values.
+ {PMIC_REG_VBUSCNT, REG_OVERRIDE, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT}, //0-VBUS_EN is controlled by ULPI_VBUS_EN
+ {PMIC_REG_VHDMICNT, REG_OVERRIDE, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT}, //0-VBUS_EN is controlled by ULPI_VBUS_EN
+ {PMIC_REG_GPIO0P3CTLO,REG_OVERRIDE, 0xFF, 0x21}, //for PMIC audio reset GPIO
+ {PMIC_REG_V3P3SXCNT, REG_OVERRIDE, PMIC_VR_EN_BIT | PMIC_VR_LPEN_BIT | BIT7 | BIT6 | BIT5, PMIC_VR_EN_BIT | PMIC_VR_LPEN_BIT | BIT6 | BIT5},
+};
+
+UINT8
+EFIAPI
+CrcPlusPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+CrcPlusPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetBATID (void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetFABID(void);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetResetCause (void);
+
+VOID
+EFIAPI
+CrcPlusPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+CrcPlusPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGpioToggleForLpcConfig(void);
+
+VOID
+CrcPlusPmicModemWa(void);
+
+VOID
+CrcPlusPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicSetVIDDecayWA (void);
+
+VOID
+CrcPlusProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+EFI_STATUS
+CrcPlusPmicDisablePowerButton(
+ OUT UINT8 *ButtonHoldTime
+);
+
+EFI_STATUS
+CrcPlusPmicEnablePowerButton (
+ IN UINT8 ButtonHoldTime
+);
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h new file mode 100644 index 0000000000..88dfb31233 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h @@ -0,0 +1,173 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_TIDC_P_H_
+#define _PMIC_REG_TIDC_P_H_
+
+#define PMIC_DEV_TI (0x3<<6) //b'11
+#define PMIC_TI_MAJOR_PG10 (0x0<<3)
+#define PMIC_TI_MAJOR_PG20 (0x1<<3)
+
+#define PMIC_TI_I2C_SLAVE_ADDR_1 0x5C //7bits address
+#define PMIC_TI_I2C_SLAVE_ADDR_2 0x5D
+#define PMIC_TI_I2C_SLAVE_ADDR_3 0x5E //default from SPEC
+#define PMIC_TI_I2C_SLAVE_ADDR_4 0x5F
+
+#define PMIC_TI_I2C_1_SLAVE_ADDR_0 0x6B
+#define PMIC_TI_I2C_1_SLAVE_ADDR_1 0x68
+
+#define PMIC_TI_I2C_BUS_NO 0x2
+
+#define TI_POWERSRC_AND_CHARGER_STATUS 0x12
+
+#define USB3750_ADDR 0x68
+#define USB3750_CHRG_TYPE_REG 0x0
+
+#define TI_BATTERY_BPTH_VALID 0x380
+
+//Charger
+#define CHG_TI_BQ24296_REG0 0x00
+#define CHG_TI_BQ24296_REG1 0x01
+#define CHG_TI_BQ24296_REG2 0x02
+#define CHG_TI_BQ24296_REG3 0x03
+#define CHG_TI_BQ24296_REG4 0x04
+#define CHG_TI_BQ24296_REG5 0x05
+#define CHG_TI_BQ24296_REG6 0x06
+#define CHG_TI_BQ24296_REG7 0x07
+#define CHG_TI_BQ24296_REG8 0x08
+#define CHG_TI_BQ24296_REG9 0x09
+#define CHG_TI_BQ24296_REG10 0x0A
+//FuelGauge
+#define TI_BATT_CAPACITY 5100
+#define REG_TI_MIRQ_ADDR 0x02 //MIRQ Register
+#define REG_TI_ADCCTRL_ADDR 0x50 //ADC Control Register
+#define REG_TI_VBATLO_ADDR 0x55 //VBATLO
+#define REG_TI_VBATHI_ADDR 0x54 //VBATHigh
+#define REG_TI_DITEMPHI_ADDR 0x56 //Die Temp High
+#define REG_TI_BPTEMPHI_ADDR 0x58 //BP Temp High
+#define REG_TI_GPTEMPHI_ADDR 0x5A //GP ADC High
+#define REG_TI_IRQ_ADDR 0x01 //IRQ Register
+#define REG_TI_BPTHREMHI 0x58 //BPTHERM High
+#define REG_TI_BPTHERMLO 0x59 //BPTHERM Low
+#define REG_TI_CC_CTRL 0x60 //CC Control
+
+#define REG_TI_CC_ACC_BYT0 0x66 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT1 0x65 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT2 0x64 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT3 0x63 //CC accumulator Reg.
+
+#define REG_TI_CC_SMPL_BYT0 0x69 //CC Sample counter BYTE
+#define REG_TI_CC_SMPL_BYT1 0x68 //CC Sample counter BYTE
+#define REG_TI_CC_SMPL_BYT2 0x67 //CC Sample counter BYTE
+
+#define REG_TI_CC_INTG1_BYT1 0x6A //CC integrator Register MSB (0:5,6-7 = rsvd)
+#define REG_TI_CC_INTG1_BYT0 0x6B //CC integrator Register LSB
+
+#define EEPROM_ACCESS_CTRL 0x88
+#define EEPROM_REG20 0xF3 // 4:7 : CC offset
+#define EEPROM_GAIN_REG 0xF4 // 4:7 : CC gain
+#define OFFSET_REG_TRIM_REV_3 0xFD
+#define TRIM_REV_3_OFFSET_STEP 1
+#define DEFAULT_CC_OFFSET_STEP 2
+#define DEFAULT_CC_OFFSET_SHIFT 0
+#define TRIM_REV_3_OFFSET_SHIFT 1
+
+#define EEPROM_CTRL 0xFE
+#define EEPROM_CTRL_EEPSEL 0x3
+#define EEPROM_CTRL_EEPSEL_MASK 0x03
+#define EEPROM_BANK0_SEL 0x01
+#define EEPROM_BANK1_SEL 0x02
+
+#define REG_TI_ADCVBATZSEGE 0x53 //Data Register for ADC Calibration
+#define REG_TI_ADCVBATZSEGE_SHIFT 4
+
+#define SMPL_INTVL 0x03
+#define CURRENT_GAIN 366 //TBD from hw team, Rsens = 10 gain = 0.366, Rsens = 20 gain = 0.1831
+ //Rsens = 30, gain = 0.122066667
+#define MAX_CC_SCALE 3662 /*CC Accumulator Bit unit 3.662uV/10mohm */
+#define CC_SMPL_CTR_MAX_VAL 0xFFFFFF
+#define CC_CNTL_CC_CTR_EN BIT0
+#define CC_CNTL_CC_CLR_EN BIT1
+#define CC_CNTL_CC_CAL_EN BIT2
+#define CC_CNTL_CC_OFFSET_EN BIT3
+#define CC_CNTL_SMPL_INTVL (BIT4 | BIT5) //TODO: Check with hw for sample interval
+#define CC_GAIN_STEP 25
+#define DEFAULT_CC_OFFSET_STEP 2
+#define TRIM_REV_3_OFFSET_STEP 1
+
+//
+// 0x01- SDP
+// 0x02- CDP
+// 0x03- DCP
+// 0x04- ACA
+// 0x05- Unknow or Other Charger Type
+//
+#define CHG_SDP 0x01
+#define CHG_CDP 0x02
+#define CHG_DCP 0x03
+#define CHG_ACA 0x04
+#define CHG_UNKNW 0x05
+//ADC Channel
+#define CH_VBAT 0
+#define CH_DIETEMP 1
+#define CH_BPTHERM 2
+#define CH_GPADC 3
+
+//Following two macros return TRUE(1) if bit is set/cleared
+#define ISBITSET(var,bitpos) ((var & (1<<bitpos))>>bitpos)
+#define ISBITCLR(var,bitpos) (~(var | (~(1<<bitpos)))>>bitpos)
+
+#define BITSET(Data,BitPos) Data |= (1<<BitPos)
+#define BITCLR(Data,BitPos) Data &= ~(1<<BitPos)
+#define BITINV(Data,BitPos) Data ^= (1<<BitPos)
+
+//Get structure offset - Pass sturcuture name and element name as parameter
+#define OFFSETOF_STURCT(STRUCTURE,ELEMENT) ((int) (&(((STRUCTURE*)(0))->ELEMENT)))
+#define CONVERT8to16BIT(Lsb,Msb,Result) Result = (UINT16) (Lsb | ((UINT16)(Msb << 8)))
+#define CONVERT8to32BIT(BYT0,BYT1,BYT2,BYT3,Result) Result = (UINT32)(BYT0 | ((UINT32)(BYT1 << 8)) | ((UINT32)(BYT2 << 16)) | ((UINT32)(BYT3 << 24)))
+#define CONVERT8to24BIT(BYT0,BYT1,BYT2,Result) Result = (UINT32)(BYT0 | ((UINT32)(BYT1 << 8)) | ((UINT32)(BYT2 << 16)))
+
+static void ResetSemaphore(void);
+
+void SendDoorBellToPunit(void);
+
+EFI_STATUS
+EFIAPI
+AcquireOwnership(void);
+
+EFI_STATUS
+EFIAPI
+ReleaseOwnership(void);
+
+EFI_STATUS
+EFIAPI
+TiPmicDVFSInit(void);
+
+EFI_STATUS
+EFIAPI
+TiReadEeprom(void);
+
+EFI_STATUS
+EFIAPI
+TiReadOffsetGainCompensation(void);
+
+UINT16
+EFIAPI
+TiPmicGetCorrectedVoltage(void);
+
+#define DIV_ROUND_CLOSEST(x, divisor) \
+ (x > 0) ? ((x + divisor / 2) / divisor) : ((x - divisor / 2) / divisor)
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h new file mode 100644 index 0000000000..e1b042dcc5 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h @@ -0,0 +1,121 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_DCX_P_H_
+#define _PMIC_REG_DCX_P_H_
+
+#define PMIC_DC_X_I2C_BUSNO 6 //I2C6 is used. index from 0
+#define PMIC_DC_X_I2C_ADDR 0x34
+#define PMIC_DEV_DC_XPOWERS 0x41 // bit 7-6 & bit 3-0: 010001: IC is AXP288
+
+#define USB3750_ADDR 0x68
+#define USB3750_CHRG_TYPE_REG 0x0
+
+#define XPOWER_POWERSRC_AND_CHARGER_STATUS 0x02
+#define XPOWER_REG_SOC 0xB9 // Bit 7=soc is valid(1) or not valid(0)
+ // BIT 0 - 6 = SOC in %
+#define XPOWER_REG_MAXCAP1 0xE0 // Bit 7=Capacity is valid(1) or not valid(0)
+ // BIT 0 - 6 = Batt max capacity bit[14:8]
+#define XPOWER_REG_MAXCAP2 0xE1 // BIT 0 - 7 = Batt max capacity bit[7:0] multiply by 1.456mah
+#define XPOWER_REG_VOLTAGE1 0x78 // BIT[11:4]
+#define XPOWER_REG_VOLTAGE2 0x79 // BIT[3:0] = rsvd, BIT[7:4] = [3:0]
+#define XPOWER_REG_CHG_CU1 0x7A // BIT 0- 7 = Charging current [11:4]
+#define XPOWER_REG_CHG_CU2 0x7B // BIT 0- 3 =RSVD, 4-7 = Charging current [3:0] multiply by 1ma
+#define XPOWER_REG_DISCHG_CU1 0x7C // BIT 0- 7 = Charging current [11:4]
+#define XPOWER_REG_DISCHG_CU2 0x7D // BIT 0- 3 =RSVD, 4-7 = Charging current [3:0] multiply by 1ma
+#define XPOWER_REG_CHR_TYP 0x2F // BIT 0 - 4 = Reserved, 7-5 = chg src (01 = SDP, 02 = CPD, 03 = DCP)
+#define XPOWER_REG_CHG_STS 0x01 // BIT6 = Charging Indication, BIT5 = Battery pres
+#define XPOWER_BATT_CAPACITY 5100
+#define XPOWER_BATT_CHG_CNTL 0x2C //BIT 0 intiate charging
+#define XPOWER_BATT_ILIM 0x30 //30[0:1] : ilim
+#define XPOWER_BATT_ICHG 0x33 //33[3:0] : Ichg
+#define XPOWER_VBUS_CLIM_SET 0x35 //35[7:4] : vbus current limit set
+
+//DollarCove XPOWER FG Characterization data Provided by FG Mfg
+//This Registers 0xC0-0xDF is OCV Percentage Table ( Refer AXP288 Datasheet for more detail )
+//Characterization Start ----->
+#define XPOWER_FG_OCV_C0 00
+#define XPOWER_FG_OCV_C1 00
+#define XPOWER_FG_OCV_C2 00
+#define XPOWER_FG_OCV_C3 00
+#define XPOWER_FG_OCV_C4 00
+#define XPOWER_FG_OCV_C5 00
+
+#define XPOWER_FG_OCV_C6 01
+#define XPOWER_FG_OCV_C7 01
+#define XPOWER_FG_OCV_C8 02
+#define XPOWER_FG_OCV_C9 03
+#define XPOWER_FG_OCV_CA 04
+
+#define XPOWER_FG_OCV_CB 11
+#define XPOWER_FG_OCV_CC 17
+#define XPOWER_FG_OCV_CD 25
+#define XPOWER_FG_OCV_CE 37
+#define XPOWER_FG_OCV_CF 42
+#define XPOWER_FG_OCV_D0 45
+
+#define XPOWER_FG_OCV_D1 49
+#define XPOWER_FG_OCV_D2 52
+#define XPOWER_FG_OCV_D3 57
+#define XPOWER_FG_OCV_D4 61
+#define XPOWER_FG_OCV_D5 65
+#define XPOWER_FG_OCV_D6 68
+
+#define XPOWER_FG_OCV_D7 71
+#define XPOWER_FG_OCV_D8 75
+#define XPOWER_FG_OCV_D9 78
+
+#define XPOWER_FG_OCV_DA 80
+#define XPOWER_FG_OCV_DB 82
+#define XPOWER_FG_OCV_DC 86
+#define XPOWER_FG_OCV_DD 91
+#define XPOWER_FG_OCV_DE 95
+#define XPOWER_FG_OCV_DF 100
+
+#define BATRDC 75 //mO
+#define BATCAP 10164 //mAh
+
+#define BATTERY_MAX_CAP_HI (0x80|(((BATCAP*1000/1456)>>8)&0X7F))
+#define BATTERY_MAX_CAP_LO ((BATCAP*1000/1456)&0xFF)
+
+#define BATTERY_RDC1 (0xC0|((((BATRDC*10000+5371)/10742)>>8)&0x1F))
+#define BATTERY_RDC0 (((BATRDC*10000+5371)/10742)&0xFF)
+
+#define XPOWER_BATTERY_BPTH_VALID 0x0F00
+
+//Characterization Table End <-----------
+
+#define DC_X_PMIC_REG_VR_CTRL_DLDO1 0x15
+#define DC_X_PMIC_REG_VR_CTRL_DLDO2 0x16
+#define DC_X_PMIC_REG_VR_CTRL_DLDO3 0x17
+#define DC_X_PMIC_REG_VR_CTRL_DLDO4 0x18
+#define DC_X_PMIC_REG_VR_CTRL_ELDO1 0x19
+#define DC_X_PMIC_REG_VR_CTRL_ELDO2 0x1A
+#define DC_X_PMIC_REG_VR_CTRL_ELDO3 0x1B
+#define DC_X_MASK_ELDO_VOL_18 (BIT04|BIT02|BIT01)
+
+EFI_STATUS
+EFIAPI
+AcquireOwnership(void);
+
+EFI_STATUS
+EFIAPI
+ReleaseOwnership(void);
+
+EFI_STATUS
+EFIAPI
+DcXPmicDVFSInit(void);
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h new file mode 100644 index 0000000000..4067edf138 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h @@ -0,0 +1,33 @@ +/** @file
+ Declare the platform requirements for the SPI controller
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPI_PORT_H
+#define _SPI_PORT_H
+
+//------------------------------------------------------------------------------
+// Types
+//------------------------------------------------------------------------------
+
+//
+// Context passed from platform (board) layer to the SPI port driver.
+//
+typedef struct {
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT32 InputFrequencyHertz;
+} SPI_PLATFORM_CONTEXT;
+
+//------------------------------------------------------------------------------
+
+#endif // _SPI_PORT_H
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriver.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriver.h new file mode 100644 index 0000000000..1384d7b9ae --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriver.h @@ -0,0 +1,666 @@ +/** @file
+ Header file for Media Device Driver
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEDIA_DEVICE_DRIVER_H
+#define _MEDIA_DEVICE_DRIVER_H
+
+#include <Uefi.h>
+
+#include <Guid/EventGroup.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Mmc.h>
+#include <IndustryStandard/CeAta.h>
+#include <IndustryStandard/SdCard.h>
+
+//
+// Driver Consumed Protocol Prototypes
+//
+#include <Protocol/DevicePath.h>
+#include <Protocol/SdHostIo.h>
+
+//
+// Driver Produced Protocol Prototypes
+//
+#include <Protocol/DriverBinding.h>
+#include <Protocol/ComponentName.h>
+#include <Protocol/ComponentName2.h>
+#include <Protocol/BlockIo.h>
+
+extern EFI_COMPONENT_NAME_PROTOCOL gMediaDeviceComponentName;
+extern EFI_DRIVER_BINDING_PROTOCOL gMediaDeviceDriverBinding;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSdMediaDeviceName2;
+
+extern UINT32 gMediaDeviceDebugLevel;
+
+#define CARD_DATA_SIGNATURE SIGNATURE_32 ('c', 'a', 'r', 'd')
+#define CARD_PARTITION_SIGNATURE SIGNATURE_32 ('c', 'p', 'a', 'r')
+
+#define CARD_PARTITION_DATA_FROM_THIS(a) \
+ CR(a, MMC_PARTITION_DATA, BlockIo, CARD_PARTITION_SIGNATURE)
+
+#define CARD_DATA_FROM_THIS(a) \
+ ((CARD_PARTITION_DATA_FROM_THIS(a))->CardData)
+
+#define CARD_DATA_PARTITION_NUM(p) \
+ ((((UINTN) p) - ((UINTN) &(p->CardData->Partitions))) / sizeof (*p))
+
+//
+// Define RPMB Data Frame strucutre(512 Bytes). Byte order is MSB first.
+// Below is the memory layout of RPMBDataFrame.
+// When performing data exchange, some swap operation may need
+// +------------------------+
+// + Stuff[0] +
+// + ...... +
+// + Stuff[511] +
+// + RPMBKey[32] +
+// + Data[0] +
+// + ...... +
+// + Data[31] +
+// + Nonce[16] +
+// + WriteCounter4] +
+// + Address[0] +
+// + Address[1] +
+// + BlkCnt[0] +
+// + BlkCnt[1] +
+// + Result[0] +
+// + Result[1] +
+// + ReqResp[0] +
+// + ReqResp[1] +
+// +------------------------+
+#pragma pack(1)
+typedef struct {
+ UINT8 Stuff[196];
+ UINT8 RPMBKey[32];
+ UINT8 Data[256];
+ UINT8 Nonce[16];
+ UINT8 WriteCounter[4];
+ UINT16 Address;
+ UINT16 BlkCnt;
+ UINT16 Result;
+ UINT16 ReqResp;
+} RPMBDataFrame;
+#pragma pack()
+
+#define RPMB_REQUEST_KEY_WRITE 0x0100
+#define RPMB_REQUEST_CTR_READ 0x0200
+#define RPMB_REQUEST_AUTH_WRITE 0x0300
+#define RPMB_REQUEST_AUTH_READ 0x0400
+#define RPMB_REQUEST_READ_RESULT 0x0500
+
+#define RPMB_RESPONSE_KEY_WRITE 0x0001
+#define RPMB_RESPONSE_CTR_READ 0x0002
+#define RPMB_RESPONSE_AUTH_WRITE 0x0003
+#define RPMB_RESPONSE_AUTH_READ 0x0004
+
+#define RPMB_RESULT_OP_OK 0x0000
+#define RPMB_RESULT_GENERAL_FAIL 0x0100
+#define RPMB_RESULT_AUTH_FAIL 0x0200
+#define RPMB_RESULT_COUNTER_FAIL 0x0300
+#define RPMB_RESULT_ADDRESS_FAIL 0x0400
+#define RPMB_RESULT_WRITE_FAIL 0x0500
+#define RPMB_RESULT_READ_FAIL 0x0600
+#define RPMB_RESULT_KEY_NOT_PROGRAMMED 0x0700
+
+#define RPMB_PARTITION 3
+#define RPMB_DATA_FRAME_SIZE 512
+
+#define CARD_DATA_FROM_RPMB_THIS(a) \
+ CR(a, CARD_DATA, RPMBIo, CARD_DATA_SIGNATURE)
+
+//
+// Define a protocol for RPMB operation
+//
+// {2E7EF202-552A-4b1f-A0BD-B644216FA5C5}
+#define EFI_EMMC_RPMB_OP_PROTOCOL_GUID \
+ { \
+ 0x2e7ef202, 0x552a, 0x4b1f, 0xa0, 0xbd, 0xb6, 0x44, 0x21, 0x6f, 0xa5, 0xc5 } \
+ }
+
+typedef struct _EFI_EMMC_RPMB_OP_PROTOCOL EFI_EMMC_RPMB_OP_PROTOCOL;
+
+typedef BOOLEAN (EFIAPI *IS_RPMBKEY_PROGRAMMED)(IN EFI_EMMC_RPMB_OP_PROTOCOL *This);
+
+typedef EFI_STATUS (EFIAPI *EMMC_PROGRAM_RPMBKEY)(IN EFI_EMMC_RPMB_OP_PROTOCOL *This, IN UINT8 * KeyString);
+
+//
+// EMMC Card info Structures
+//
+struct _EFI_EMMC_RPMB_OP_PROTOCOL {
+ IS_RPMBKEY_PROGRAMMED EmmcIsRPMBProgrammed;
+ EMMC_PROGRAM_RPMBKEY EmmcProgramRPMBKey;
+};
+
+extern EFI_GUID gEfiEmmcRpmbOpProtocolGuid;
+
+//
+// Partition Number
+//
+#define NO_ACCESS_TO_BOOT_PARTITION 0x00
+#define BOOT_PARTITION_1 0x01
+#define BOOT_PARTITION_2 0x02
+#define REPLAY_PROTECTED_MEMORY_BLOCK 0x03
+#define GENERAL_PURPOSE_PARTITION_1 0x04
+#define GENERAL_PURPOSE_PARTITION_2 0x05
+#define GENERAL_PURPOSE_PARTITION_3 0x06
+#define GENERAL_PURPOSE_PARTITION_4 0x07
+
+//
+// Command timeout will be max 100 ms
+//
+#define TIMEOUT_COMMAND 100
+#define TIMEOUT_DATA 5000
+
+typedef enum{
+ UnknownCard = 0,
+ MMCCard, // MMC card
+ CEATACard, // CE-ATA device
+ SDMemoryCard, // SD 1.1 card
+ SDMemoryCard2, // SD 2.0 or above standard card
+ SDMemoryCard2High // SD 2.0 or above high capacity card
+} CARD_TYPE;
+
+typedef struct _CARD_DATA CARD_DATA;
+
+typedef struct {
+ //
+ //BlockIO
+ //
+ UINT32 Signature;
+
+ EFI_HANDLE Handle;
+
+ BOOLEAN Present;
+
+ EFI_DEVICE_PATH_PROTOCOL *DevPath;
+
+ EFI_BLOCK_IO_PROTOCOL BlockIo;
+
+ EFI_BLOCK_IO_MEDIA BlockIoMedia;
+
+ CARD_DATA *CardData;
+
+} MMC_PARTITION_DATA;
+
+#define MAX_NUMBER_OF_PARTITIONS 8
+
+struct _CARD_DATA {
+ //
+ //BlockIO
+ //
+ UINT32 Signature;
+
+ EFI_HANDLE Handle;
+
+ MMC_PARTITION_DATA Partitions[MAX_NUMBER_OF_PARTITIONS];
+
+ EFI_SD_HOST_IO_PROTOCOL *SdHostIo;
+ EFI_EMMC_RPMB_OP_PROTOCOL RPMBIo;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ CARD_TYPE CardType;
+
+ UINT8 CurrentBusWidth;
+ BOOLEAN DualVoltage;
+ BOOLEAN NeedFlush;
+ UINT8 Reserved[3];
+
+ UINT16 Address;
+ UINT32 BlockLen;
+ UINT32 MaxFrequency;
+ UINT64 BlockNumber;
+ //
+ //Common used
+ //
+ CARD_STATUS CardStatus;
+ OCR OCRRegister;
+ CID CIDRegister;
+ CSD CSDRegister;
+ EXT_CSD ExtCSDRegister;
+ UINT8 *RawBufferPointer;
+ UINT8 *AlignedBuffer;
+ //
+ //CE-ATA specific
+ //
+ TASK_FILE TaskFile;
+ IDENTIFY_DEVICE_DATA IndentifyDeviceData;
+ //
+ //SD specific
+ //
+ SCR SCRRegister;
+ SD_STATUS_REG SDSattus;
+ SWITCH_STATUS SwitchStatus;
+};
+
+/**
+ Entry point for Media Device EFI drivers.
+
+ @param[in] ImageHandle EFI_HANDLE
+ @param[in] SystemTable EFI_SYSTEM_TABLE
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_DEVICE_ERROR The function failed to complete
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Install Media Device BlockIo Protocol
+
+ @param[in] CardData Pointer to CARD_DATA
+
+ @retval EFI_SUCCESS BlockIo Protocol installed succesfully
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+**/
+EFI_STATUS
+MediaDeviceDriverInstallBlockIo (
+ IN CARD_DATA *CardData
+ );
+
+/**
+ Uninstall Media Device BlockIo Protocol
+
+ @param[in] CardData Pointer to CARD_DATA
+
+ @retval EFI_SUCCESS BlockIo Protocol uninstalled succesfully
+**/
+EFI_STATUS
+MediaDeviceDriverUninstallBlockIo (
+ IN CARD_DATA *CardData
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the EFI Driver.
+
+ @param[in] This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] Language A pointer to a three character ISO 639-2 language identifier.
+ This is the language of the driver name that that the caller
+ is requesting, and it must match one of the languages specified
+ in SupportedLanguages. The number of languages supported by a
+ driver is up to the driver writer.
+ @param[in] DriverName A pointer to the Unicode string to return. This Unicode string
+ is the name of the driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Language is NULL
+ @retval EFI_INVALID_PARAMETER DriverName is NULL
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by an EFI Driver.
+
+ @param[in] This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of a controller that the driver specified by
+ This is managing. This handle specifies the controller
+ whose name is to be returned.
+ @param[in] ChildHandle The handle of the child controller to retrieve the name
+ of. This is an optional parameter that may be NULL. It
+ will be NULL for device drivers. It will also be NULL
+ for a bus drivers that wish to retrieve the name of the
+ bus controller. It will not be NULL for a bus driver
+ that wishes to retrieve the name of a child controller.
+ @param[in] Language A pointer to a three character ISO 639-2 language
+ identifier. This is the language of the controller name
+ that that the caller is requesting, and it must match one
+ of the languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up to the
+ driver writer.
+ @param[in] ControllerName A pointer to the Unicode string to return. This Unicode
+ string is the name of the controller specified by
+ ControllerHandle and ChildHandle in the language
+ specified by Language from the point of view of the
+ driver specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in the
+ language specified by Language for the driver
+ specified by This was returned in DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceComponentNameGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle, OPTIONAL
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+/**
+ Test to see if this Media Device driver supports ControllerHandle.
+ Any ControllerHandle that has installed will be supported.
+
+ @param[in] This Protocol instance pointer
+ @param[in] Controller Handle of device to test
+ @param[in] RemainingDevicePath Not used
+
+ @retval EFI_SUCCESS This driver supports this device
+ @retval EFI_UNSUPPORTED This driver does not support this device
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceDriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Starting the Media Device Driver
+
+ @param[in] This Protocol instance pointer
+ @param[in] Controller Handle of device to start
+ @param[in] RemainingDevicePath Not used
+
+ @retval EFI_SUCCESS This driver start this device
+ @retval EFI_UNSUPPORTED This driver does not support this device
+ @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error
+ @retval EFI_OUT_OF_RESOURCES This driver cannot allocate resources
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceDriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Stop Media Device driver on ControllerHandle. Support stoping any child handles
+ created by this driver.
+
+ @param[in] This Protocol instance pointer
+ @param[in] Controller Handle of device to stop driver on
+ @param[in] NumberOfChildren Number of Children in the ChildHandleBuffer
+ @param[in] ChildHandleBuffer List of handles for the children we need to stop
+
+ @retval EFI_SUCCESS This driver stop this device
+ @retval EFI_DEVICE_ERROR This driver cannot be stop due to device Error
+**/
+EFI_STATUS
+EFIAPI
+MediaDeviceDriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+/**
+ MMC/SD card init function
+
+ @param[in] CardData Pointer to CARD_DATA
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size indicated
+**/
+EFI_STATUS
+MMCSDCardInit (
+ IN CARD_DATA *CardData
+ );
+
+/**
+ MMC/SD card BlockIo init function
+
+ @param[in] CardData Pointer to CARD_DATA
+
+ @retval EFI_SUCCESS Success
+**/
+EFI_STATUS
+MMCSDBlockIoInit (
+ IN CARD_DATA *CardData
+ );
+
+/**
+ Send command by using Host IO protocol
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] CommandIndex The command index to set the command index field of command register
+ @param[in] Argument Command argument to set the argument field of command register
+ @param[in] DataType TRANSFER_TYPE, indicates no data, data in or data out
+ @param[in] Buffer Contains the data read from / write to the device
+ @param[in] BufferSize The size of the buffer
+ @param[in] ResponseType RESPONSE_TYPE
+ @param[in] TimeOut Time out value in 1 ms unit
+ @param[in] ResponseData Depending on the ResponseType, such as CSD or card status
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_OUT_OF_RESOURCES A resource has run out.
+ @retval EFI_TIMEOUT The timeout time expired.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_DEVICE_ERROR The physical device reported an error while attempting the operation
+**/
+EFI_STATUS
+SendCommand (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData
+ );
+
+/**
+ Send the card FAST_IO command
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] RegisterAddress Register Address
+ @param[in] RegisterData Pointer to register Data
+ @param[in] Write TRUE for write, FALSE for read
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_DEVICE_ERROR The function failed with device error
+**/
+EFI_STATUS
+FastIO (
+ IN CARD_DATA *CardData,
+ IN UINT8 RegisterAddress,
+ IN OUT UINT8 *RegisterData,
+ IN BOOLEAN Write
+ );
+
+/**
+ Send the card APP_CMD command with the following command indicated
+ by CommandIndex
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] CommandIndex The command index to set the command index field of command register
+ @param[in] Argument Command argument to set the argument field of command register
+ @param[in] DataType TRANSFER_TYPE, indicates no data, data in or data out
+ @param[in] Buffer Contains the data read from / write to the device
+ @param[in] BufferSize The size of the buffer
+ @param[in] ResponseType RESPONSE_TYPE
+ @param[in] TimeOut Time out value in 1 ms unit
+ @param[in] ResponseData Depending on the ResponseType, such as CSD or card status
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_OUT_OF_RESOURCES A resource has run out.
+ @retval EFI_TIMEOUT The timeout time expired.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_DEVICE_ERROR The physical device reported an error while attempting the operation
+**/
+EFI_STATUS
+SendAppCommand (
+ IN CARD_DATA *CardData,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData
+ );
+
+/**
+ Function to get MMC EXT_CSD in 8 bits
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] Offset Register offset
+
+ @retval ExtCSDRegister Ext Csd register in 8 bits
+**/
+UINT32
+MmcGetExtCsd8 (
+ IN CARD_DATA *CardData,
+ IN UINTN Offset
+ );
+
+/**
+ Function to get MMC EXT_CSD in 24 bits
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] Offset Register offset
+
+ @retval ExtCSDRegister Ext Csd register in 24 bits
+**/
+UINT32
+MmcGetExtCsd24 (
+ IN CARD_DATA *CardData,
+ IN UINTN Offset
+ );
+
+/**
+ Function to get MMC EXT_CSD in 32 bits
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] Offset Register offset
+
+ @retval ExtCSDRegister Ext Csd register in 32 bits
+**/
+UINT32
+MmcGetExtCsd32 (
+ IN CARD_DATA *CardData,
+ IN UINTN Offset
+ );
+
+/**
+ Function to get MMC current partition
+
+ @param[in] CardData Pointer to CARD_DATA
+
+ @retval CurrentPartition MMC card current partition
+**/
+UINTN
+MmcGetCurrentPartitionNum (
+ IN CARD_DATA *CardData
+ );
+
+/**
+ Function to set Write Protection on the MMC
+
+ @param[in] Event EFI_EVENT
+ @param[in] Context Pointer to the context
+
+ @retval none
+**/
+VOID
+EFIAPI
+SetEmmcWpOnEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+);
+
+VOID
+SecureEraseEvent(
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ Function to select MMC partition
+
+ @param[in] CardData Pointer to CARD_DATA
+ @param[in] Partition Partition to select
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_DEVICE_ERROR The function failed with device error
+**/
+EFI_STATUS
+MmcSelectPartitionNum (
+ IN CARD_DATA *CardData,
+ IN UINT8 Partition
+ );
+
+/**
+ Function to select MMC partition
+
+ @param[in] Partition Pointer to MMC Partition data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_UNSUPPORTED The operation is not supported
+ @retval EFI_DEVICE_ERROR The function failed with device error
+**/
+EFI_STATUS
+MmcSelectPartition (
+ IN MMC_PARTITION_DATA *Partition
+ );
+
+VOID
+SecureErase(
+ CARD_DATA *CardData
+ );
+
+EFI_STATUS
+EFIAPI
+EmmcInstallRPMBProtocol (
+IN CARD_DATA *CardData
+);
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriverPei.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriverPei.h new file mode 100644 index 0000000000..5875b8d50a --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/MediaDeviceDriverPei.h @@ -0,0 +1,395 @@ +/** @file
+ Media Device Driver header
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEDIA_DEVICE_DRIVER_H
+#define _MEDIA_DEVICE_DRIVER_H
+#include <Uefi.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/TimerLib.h>
+#include <Ppi/Sdhc.h>
+#include <Ppi/PeiBlockIo.h>
+
+#include <IndustryStandard/Mmc.h>
+#include <IndustryStandard/SdCard.h>
+//
+// Driver Consumed Protocol Prototypes
+//
+#include <Protocol/DevicePath.h>
+//
+// Driver Produced Protocol Prototypes
+//
+#include <Ppi/BlockIo.h>
+
+extern UINT32 gMediaDeviceDebugLevel;
+
+#define PEI_CARD_DATA_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'd')
+#define PEI_CARD_PARTITION_SIGNATURE SIGNATURE_32 ('p', 'c', 'a', 'r')
+
+#define MAX_NUMBER_OF_PARTITIONS 8
+
+#define PEI_CARD_PARTITION_DATA_FROM_THIS(a) \
+ CR(a, PEI_MMC_PARTITION_DATA, BlockIo, PEI_CARD_PARTITION_SIGNATURE)
+
+#define PEI_CARD_DATA_FROM_THIS(a) \
+ ((PEI_CARD_PARTITION_DATA_FROM_THIS(a))->PeiCardData)
+
+#define PEI_CARD_DATA_PARTITION_NUM(p) \
+ ((((UINTN) p) - ((UINTN) &(p->PeiCardData->Partitions))) / sizeof (*p))
+
+ //
+ // Used to check-call local functions inside this eMMC module
+ //
+ // Func - The function name which needs to be checked
+ // Str - Optional, it is the description of the output infomation
+ // FailOrNot - When functional call is failed, it should stop or continue
+ //
+#define CHK_FUNC_CALL(Func, Str, FailOrNot) \
+ do { \
+ EFI_STATUS ret = Func; \
+ if (EFI_SUCCESS!= ret && TRUE == FailOrNot) { \
+ DEBUG((EFI_D_ERROR, "ERROR: %a,%d:", __FUNCTION__,__LINE__)); \
+ if ( NULL != (void *)Str ) {\
+ DEBUG((EFI_D_ERROR, "%a:", Str)); \
+ } \
+ DEBUG((EFI_D_ERROR, " Status = 0x%x\n", ret)); \
+ return ret; \
+ } \
+ } while (0)
+
+//
+// Partition Number
+//
+#define NO_ACCESS_TO_BOOT_PARTITION 0x00
+#define BOOT_PARTITION_1 0x01
+#define BOOT_PARTITION_2 0x02
+#define REPLAY_PROTECTED_MEMORY_BLOCK 0x03
+#define GENERAL_PURPOSE_PARTITION_1 0x04
+#define GENERAL_PURPOSE_PARTITION_2 0x05
+#define GENERAL_PURPOSE_PARTITION_3 0x06
+#define GENERAL_PURPOSE_PARTITION_4 0x07
+
+//
+// Command timeout will be max 100 ms
+//
+#define TIMEOUT_COMMAND 500
+#define TIMEOUT_DATA 5000
+
+typedef enum{
+ UnknownCard = 0,
+ MMCCard, // MMC card
+ CEATACard, // CE-ATA device
+ SDMemoryCard, // SD 1.1 card
+ SDMemoryCard2, // SD 2.0 or above standard card
+ SDMemoryCard2High // SD 2.0 or above high capacity card
+}CARD_TYPE;
+
+typedef struct _PEI_CARD_DATA PEI_CARD_DATA;
+
+/**
+ Writes the requested number of blocks to the specified block device.
+
+ The function writes the requested number of blocks to the device. All the
+ blocks are write, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to write to
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the write operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_WRITE_BLOCKS) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+typedef struct {
+ //
+ //BlockIO
+ //
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ BOOLEAN Present;
+ EFI_DEVICE_PATH_PROTOCOL *DevPath;
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI BlockIo;
+ EFI_PEI_WRITE_BLOCKS WriteBlocks;
+ EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
+ PEI_BLOCK_IO_MEDIA BlockIoMedia;
+ PEI_CARD_DATA *PeiCardData;
+} PEI_MMC_PARTITION_DATA;
+
+struct _PEI_CARD_DATA {
+ //
+ //BlockIO
+ //
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ PEI_MMC_PARTITION_DATA Partitions[MAX_NUMBER_OF_PARTITIONS];
+ EFI_PEI_PPI_DESCRIPTOR PpiList;
+ PEI_SD_CONTROLLER_PPI *SdControllerPpi;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ CARD_TYPE CardType;
+ UINT8 CurrentBusWidth;
+ BOOLEAN DualVoltage;
+ BOOLEAN NeedFlush;
+ UINT8 Reserved[3];
+ UINT16 Address;
+ UINT32 BlockLen;
+ UINT32 MaxFrequency;
+ UINT64 BlockNumber;
+ //
+ //Common used
+ //
+ CARD_STATUS CardStatus;
+ OCR OCRRegister;
+ CID CIDRegister;
+ CSD CSDRegister;
+ EXT_CSD ExtCSDRegister;
+ UINT8 *RawBufferPointer;
+ UINT8 *AlignedBuffer;
+
+ //
+ //SD specific
+ //
+ SCR SCRRegister;
+ SD_STATUS_REG SDSattus;
+ SWITCH_STATUS SwitchStatus;
+};
+
+EFI_STATUS
+EFIAPI
+MediaDeviceDriverEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+BotGetNumberOfBlockDevices (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ );
+
+EFI_STATUS
+EFIAPI
+BotGetMediaInfo (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ );
+
+EFI_STATUS
+EFIAPI
+MMCSDBlockReadBlocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+MMCSDBlockWriteBlocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+EFI_STATUS
+MMCSDCardInit (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+MMCSDBlockIoInit (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+SendCommand (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData
+ );
+
+EFI_STATUS
+FastIO (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINT8 RegisterAddress,
+ IN OUT UINT8 *RegisterData,
+ IN BOOLEAN Write
+ );
+
+EFI_STATUS
+IndentifyDevice (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+FlushCache (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+StandByImmediate (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+ReadDMAExt (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN EFI_LBA LBA,
+ IN UINT8 *Buffer,
+ IN UINT16 SectorCount
+ );
+
+EFI_STATUS
+WriteDMAExt (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN EFI_LBA LBA,
+ IN UINT8 *Buffer,
+ IN UINT16 SectorCount
+ );
+
+EFI_STATUS
+SoftwareReset (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+SendAppCommand (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData
+ );
+
+UINT32
+MmcGetExtCsd8 (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINTN Offset
+ );
+
+UINT32
+MmcGetExtCsd24 (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINTN Offset
+ );
+
+UINT32
+MmcGetExtCsd32 (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINTN Offset
+ );
+
+UINTN
+MmcGetCurrentPartitionNum (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+MmcSelectPartitionNum (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN UINT8 Partition
+ );
+
+EFI_STATUS
+MmcSelectPartition (
+ IN PEI_MMC_PARTITION_DATA *Partition
+ );
+
+EFI_STATUS
+MmcReadExtCsd (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+MmcMoveToTranState (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+
+EFI_STATUS
+MmcSelect (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN BOOLEAN Select
+ );
+
+EFI_STATUS
+MmcSendSwitch (
+ IN PEI_CARD_DATA *PeiCardData,
+ IN SWITCH_ARGUMENT *SwitchArgument
+ );
+
+EFI_STATUS
+MmcGoIdleState (
+ IN PEI_CARD_DATA *PeiCardData
+ );
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchAccess.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchAccess.h new file mode 100644 index 0000000000..f1432b56bc --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchAccess.h @@ -0,0 +1,405 @@ +/** @file
+ Macros that simplify accessing PCH devices's PCI registers.
+
+ ** NOTE ** these macros assume the PCH device is on BUS 0
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_ACCESS_H_
+#define _PCH_ACCESS_H_
+
+#include "PchRegs.h"
+
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND 1
+#endif
+#ifndef STALL_ONE_SECOND
+#define STALL_ONE_SECOND 1000000
+#endif
+
+///
+/// Memory Mapped PCI Access macros
+///
+///
+/// PCI Device MM Base
+///
+#ifndef MmPciAddress
+#define MmPciAddress(Segment, Bus, Device, Function, Register) \
+ ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + \
+ (UINTN) (Bus << 20) + \
+ (UINTN) (Device << 15) + \
+ (UINTN) (Function << 12) + \
+ (UINTN) (Register) \
+ )
+#endif
+///
+/// Pch Controller PCI access macros
+///
+#define PCH_RCRB_BASE ( \
+ MmioRead32 (MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ PCI_FUNCTION_NUMBER_PCH_LPC), \
+ R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \
+ )
+
+///
+/// Device 0x1b, Function 0
+///
+#define PchAzaliaPciCfg32(Register) \
+ MmioRead32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register) \
+ )
+
+#define PchAzaliaPciCfg32Or(Register, OrData) \
+ MmioOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchAzaliaPciCfg32And(Register, AndData) \
+ MmioAnd32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchAzaliaPciCfg16(Register) \
+ MmioRead16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register) \
+ )
+
+#define PchAzaliaPciCfg16Or(Register, OrData) \
+ MmioOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchAzaliaPciCfg16And(Register, AndData) \
+ MmioAnd16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))
+
+#define PchAzaliaPciCfg8Or(Register, OrData) \
+ MmioOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchAzaliaPciCfg8And(Register, AndData) \
+ MmioAnd8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_AZALIA, \
+ 0, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+///
+/// Device 0x1f, Function 0
+///
+#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
+
+#define PchLpcPciCfg32Or (Register, OrData) \
+ MmioOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchLpcPciCfg32And(Register, AndData) \
+ MmioAnd32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
+
+#define PchLpcPciCfg16Or(Register, OrData) \
+ MmioOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchLpcPciCfg16And(Register, AndData) \
+ MmioAnd16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
+
+#define PchLpcPciCfg8Or(Register, OrData) \
+ MmioOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ OrData \
+ )
+
+#define PchLpcPciCfg8And(Register, AndData) \
+ MmioAnd8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData \
+ )
+
+#define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_LPC, \
+ 0, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#ifdef SATA_SUPPORT
+///
+/// SATA device 0x13, Function 0
+///
+#define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
+
+#define PchSataPciCfg32Or(Register, OrData) \
+ MmioOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ OrData \
+ )
+
+#define PchSataPciCfg32And(Register, AndData) \
+ MmioAnd32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData \
+ )
+
+#define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr32 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
+
+#define PchSataPciCfg16Or(Register, OrData) \
+ MmioOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ OrData \
+ )
+
+#define PchSataPciCfg16And(Register, AndData) \
+ MmioAnd16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData \
+ )
+
+#define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr16 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
+
+#define PchSataPciCfg8Or(Register, OrData) \
+ MmioOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ OrData \
+ )
+
+#define PchSataPciCfg8And(Register, AndData) \
+ MmioAnd8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData \
+ )
+
+#define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \
+ MmioAndThenOr8 ( \
+ MmPciAddress (0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_SATA, \
+ PCI_FUNCTION_NUMBER_PCH_SATA, \
+ Register), \
+ AndData, \
+ OrData \
+ )
+
+#endif
+
+///
+/// Root Complex Register Block
+///
+#define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)
+
+#define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)
+
+#define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
+
+#define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
+
+#define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)
+
+#define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)
+
+#define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)
+
+#define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)
+
+#define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)
+
+#define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)
+
+#define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)
+
+#define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs.h new file mode 100644 index 0000000000..fb92c88ce3 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs.h @@ -0,0 +1,210 @@ +/** @file
+ Register names for PCH.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_H_
+#define _PCH_REGS_H_
+
+//
+// Bit Definitions.
+// @bug drive these definitions to code base. Should not need to be part of
+// chipset modules
+//
+#ifndef BIT0
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#define BIT32 0x100000000
+#define BIT33 0x200000000
+#define BIT34 0x400000000
+#define BIT35 0x800000000
+#define BIT36 0x1000000000
+#define BIT37 0x2000000000
+#define BIT38 0x4000000000
+#define BIT39 0x8000000000
+#define BIT40 0x10000000000
+#define BIT41 0x20000000000
+#define BIT42 0x40000000000
+#define BIT43 0x80000000000
+#define BIT44 0x100000000000
+#define BIT45 0x200000000000
+#define BIT46 0x400000000000
+#define BIT47 0x800000000000
+#define BIT48 0x1000000000000
+#define BIT49 0x2000000000000
+#define BIT50 0x4000000000000
+#define BIT51 0x8000000000000
+#define BIT52 0x10000000000000
+#define BIT53 0x20000000000000
+#define BIT54 0x40000000000000
+#define BIT55 0x80000000000000
+#define BIT56 0x100000000000000
+#define BIT57 0x200000000000000
+#define BIT58 0x400000000000000
+#define BIT59 0x800000000000000
+#define BIT60 0x1000000000000000
+#define BIT61 0x2000000000000000
+#define BIT62 0x4000000000000000
+#define BIT63 0x8000000000000000
+#endif
+///
+/// The default PCH PCI bus number
+///
+#define DEFAULT_PCI_BUS_NUMBER_PCH 0
+
+//
+// Default Vendor ID and Subsystem ID
+//
+#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor ID
+#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsystem ID
+#define V_PCH_DEFAULT_SVID_SID (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID
+
+///
+/// Include device register definitions
+///
+#include "PchRegs/PchRegsHda.h"
+#include "PchRegs/PchRegsIsh.h"
+#include "PchRegs/PchRegsLpe.h"
+#include "PchRegs/PchRegsLpss.h"
+#ifdef PCIESC_SUPPORT
+#include "PchRegs/PchRegsPcie.h"
+#endif
+#include "PchRegs/PchRegsPcu.h"
+#include "PchRegs/PchRegsRcrb.h"
+#ifdef SATA_SUPPORT
+#include "PchRegs/PchRegsSata.h"
+#endif
+#include "PchRegs/PchRegsScc.h"
+#include "PchRegs/PchRegsSmbus.h"
+#include "PchRegs/PchRegsSpi.h"
+#include "PchRegs/PchRegsUsb.h"
+
+#define IS_PCH_LPC_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_LPC_DEVICE_ID_0) || \
+ (DeviceId == V_PCH_LPC_DEVICE_ID_1) || \
+ (DeviceId == V_PCH_LPC_DEVICE_ID_2) || \
+ (DeviceId == V_PCH_LPC_DEVICE_ID_3) \
+ )
+
+#ifndef SATA_SUPPORT
+#define IS_PCH_SATA_DEVICE_ID(DeviceId) 0
+#else
+#define IS_PCH_SATA_DEVICE_ID(DeviceId) \
+ ( \
+ IS_PCH_SATA_AHCI_DEVICE_ID (DeviceId) || \
+ IS_PCH_SATA_MODE_DEVICE_ID (DeviceId) || \
+ IS_PCH_SATA_RAID_DEVICE_ID (DeviceId) \
+ )
+#endif
+
+#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \
+ )
+
+#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \
+ )
+
+#define IS_PCH_SATA_MODE_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \
+ (DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \
+ )
+#define IS_PCH_USB_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_XHCI_DEVICE_ID_0) \
+ )
+#ifndef PCIESC_SUPPORT
+#define IS_PCH_PCIE_DEVICE_ID(DeviceId) 0
+#else
+#define IS_PCH_PCIE_DEVICE_ID(DeviceId) \
+ ( \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \
+ (DeviceId == V_PCH_PCIE_DEVICE_ID_7) \
+ )
+#endif
+
+///
+/// Any device ID that is Cherryview SC
+///
+#define IS_PCH_CHV_DEVICE_ID(DeviceId) \
+ ( \
+ IS_PCH_LPC_DEVICE_ID (DeviceId) || \
+ IS_PCH_SATA_DEVICE_ID (DeviceId) || \
+ IS_PCH_USB_DEVICE_ID (DeviceId) || \
+ IS_PCH_PCIE_DEVICE_ID (DeviceId) || \
+ (DeviceId) == V_PCH_SMBUS_DEVICE_ID || \
+ (DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \
+ (DeviceId) == V_PCH_HDA_DEVICE_ID_1 \
+ )
+
+#define IS_SUPPORTED_DEVICE_ID(DeviceId) IS_PCH_CHV_DEVICE_ID (DeviceId)
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsHda.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsHda.h new file mode 100644 index 0000000000..61d15cdea8 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsHda.h @@ -0,0 +1,60 @@ +/** @file
+ Register names for PCH High Definition Audio device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_HDA_H_
+#define _PCH_REGS_HDA_H_
+
+//
+// Azalia Controller Registers (D27:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_AZALIA 27
+#define PCI_FUNCTION_NUMBER_PCH_AZALIA 0
+//
+#define R_PCH_HDA_DEVVENID 0x00 // Device / Vendor ID
+#define B_PCH_HDA_DEVVENID_DEVICE_ID 0xFFFF0000 // Device ID
+#define B_PCH_HDA_DEVVENID_VENDOR_ID 0x0000FFFF // Vendor ID
+#define V_PCH_HDA_DEVVENID_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
+#define V_PCH_HDA_DEVICE_ID_0 0x2284
+#define V_PCH_HDA_DEVICE_ID_1 0x2285
+
+#define R_PCH_HDA_SVID 0x2C // Sub System Vendor ID
+#define B_PCH_HDA_SVID 0xFFFF
+
+#define R_PCH_HDA_PCS 0x54 // Power Management Control and Status
+#define B_PCH_HDA_PCS_DATA 0xFF000000 // Data, does not apply
+#define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply
+#define B_PCH_HDA_PCS_PMES BIT15 // PME Status
+#define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable
+#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) // Power State - D0/D3 Hot
+#define V_PCH_HDA_PCS_PS0 0x00
+#define V_PCH_HDA_PCS_PS3 0x03
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsIsh.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsIsh.h new file mode 100644 index 0000000000..293f5143bf --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsIsh.h @@ -0,0 +1,93 @@ +/** @file
+ Register names for Integrated Sensor Hub.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_ISH_H_
+#define _PCH_REGS_ISH_H_
+
+//
+// ISH Config Registers (D10:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_ISH 10
+#define PCI_FUNCTION_NUMBER_PCH_ISH 0
+
+#define R_PCH_ISH_DEVVENID 0x00 // Device / Vendor ID
+#define B_PCH_ISH_DEVVENID_DEVICE_ID 0xFFFF0000 // Device ID
+#define B_PCH_ISH_DEVVENID_VENDOR_ID 0x0000FFFF // Vendor ID
+#define V_PCH_ISH_DEVVENID_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
+
+#define R_PCH_ISH_STSCMD 0x04 // Status Command
+#define B_PCH_ISH_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_ISH_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_ISH_STSCMD_CAP_LST BIT20 // Capabilities List
+#define B_PCH_ISH_STSCMD_INTR_STS BIT19 // Interrupt Status
+#define B_PCH_ISH_STSCMD_INTR_DIS BIT10 // Interrupt Disable
+#define B_PCH_ISH_STSCMD_SERR_EN BIT8 // SERR Enable
+#define B_PCH_ISH_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_ISH_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_ISH_RID_CC 0x08 // Revision ID and Class Code
+#define B_PCH_ISH_RID_CC_BCC 0xFF000000 // Base Class Code
+#define B_PCH_ISH_RID_CC_SCC 0x00FF0000 // Sub Class Code
+#define B_PCH_ISH_RID_CC_PI 0x0000FF00 // Programming Interface
+#define B_PCH_ISH_RID_CC_RID 0x000000FF // Revision Identification
+
+#define R_PCH_ISH_BAR0 0x10 // BAR 0
+#define B_PCH_ISH_BAR0_BA 0xFFFFF000 // Base Address
+#define V_PCH_ISH_BAR0_SIZE 0x1000
+#define N_PCH_ISH_BAR0_ALIGNMENT 12
+#define B_PCH_ISH_BAR0_PREF BIT3 // Prefetchable
+#define B_PCH_ISH_BAR0_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_ISH_BAR0_SPTYP BIT0 // Space Type (Memory)
+
+#define R_PCH_ISH_BAR1 0x18 // BAR 1
+#define B_PCH_ISH_BAR1_BA 0xFFFFF000 // Base Address
+#define B_PCH_ISH_BAR1_PREF BIT3 // Prefetchable
+#define B_PCH_ISH_BAR1_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_ISH_BAR1_SPTYP BIT0 // Space Type (Memory)
+#define V_PCH_ISH_BAR1_SIZE (1 << 12)
+
+#define R_PCH_ISH_SSID 0x2C // Sub System ID
+#define B_PCH_ISH_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_ISH_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_ISH_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_ISH_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_ISH_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_ISH_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_ISH_INTR 0x3C // Interrupt
+#define B_PCH_ISH_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_ISH_INTR_MG 0x00FF0000
+#define B_PCH_ISH_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_ISH_INTR_IL 0x000000FF // Interrupt Line
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpe.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpe.h new file mode 100644 index 0000000000..4aa84faa00 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpe.h @@ -0,0 +1,93 @@ +/** @file
+ Register names for Low Power Audio device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_LPE_H_
+#define _PCH_REGS_LPE_H_
+
+//
+// LPE Config Registers (D21:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPE 21
+#define PCI_FUNCTION_NUMBER_PCH_LPE 0
+
+#define R_PCH_LPE_DEVVENID 0x00 // Device / Vendor ID
+#define B_PCH_LPE_DEVVENID_DEVICE_ID 0xFFFF0000 // Device ID
+#define B_PCH_LPE_DEVVENID_VENDOR_ID 0x0000FFFF // Vendor ID
+#define V_PCH_LPE_DEVVENID_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
+
+#define R_PCH_LPE_STSCMD 0x04 // Status Command
+#define B_PCH_LPE_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPE_STSCMD_RCA BIT28 // RCA
+#define B_PCH_LPE_STSCMD_CAP_LST BIT20 // Capabilities List
+#define B_PCH_LPE_STSCMD_INTR_STS BIT19 // Interrupt Status
+#define B_PCH_LPE_STSCMD_INTR_DIS BIT10 // Interrupt Disable
+#define B_PCH_LPE_STSCMD_SERR_EN BIT8 // SERR Enable
+#define B_PCH_LPE_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPE_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPE_RID_CC 0x08 // Revision ID and Class Code
+#define B_PCH_LPE_RID_CC_BCC 0xFF000000 // Base Class Code
+#define B_PCH_LPE_RID_CC_SCC 0x00FF0000 // Sub Class Code
+#define B_PCH_LPE_RID_CC_PI 0x0000FF00 // Programming Interface
+#define B_PCH_LPE_RID_CC_RID 0x000000FF // Revision Identification
+
+#define R_PCH_LPE_BAR0 0x10 // BAR 0
+#define B_PCH_LPE_BAR0_BA 0xFFE00000 // Base Address
+#define V_PCH_LPE_BAR0_SIZE 0x200000
+#define N_PCH_LPE_BAR0_ALIGNMENT 21
+#define B_PCH_LPE_BAR0_PREF BIT3 // Prefetchable
+#define B_PCH_LPE_BAR0_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_LPE_BAR0_SPTYP BIT0 // Space Type (Memory)
+
+#define R_PCH_LPE_BAR1 0x18 // BAR 1
+#define B_PCH_LPE_BAR1_BA 0xFFFFF000 // Base Address
+#define B_PCH_LPE_BAR1_PREF BIT3 // Prefetchable
+#define B_PCH_LPE_BAR1_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_LPE_BAR1_SPTYP BIT0 // Space Type (Memory)
+#define V_PCH_LPE_BAR1_SIZE (1 << 12)
+
+#define R_PCH_LPE_SSID 0x2C // Sub System ID
+#define B_PCH_LPE_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPE_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPE_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPE_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPE_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPE_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPE_INTR 0x3C // Interrupt
+#define B_PCH_LPE_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPE_INTR_MG 0x00FF0000
+#define B_PCH_LPE_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPE_INTR_IL 0x000000FF // Interrupt Line
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpss.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpss.h new file mode 100644 index 0000000000..e80e0bcc03 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsLpss.h @@ -0,0 +1,506 @@ +/** @file
+ Register names for Low Power Sub System (LPSS) module.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_LPSS_H_
+#define _PCH_REGS_LPSS_H_
+
+//
+// Low Power Input Output (LPSS) Module Registers
+//
+
+//
+// LPSS DMAC Modules
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30
+#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0
+
+#define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command
+#define B_PCH_LPSS_DMAC_STSCMD_SSE BIT30 // Signaled System Error
+#define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPSS_DMAC_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_LPSS_DMAC_STSCMD_STA BIT27 // Signaled Target Abort
+#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_LPSS_DMAC_CLHB 0x0C
+#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_LPSS_DMAC_BAR 0x10 // BAR
+#define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address
+#define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000
+#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14
+#define B_PCH_LPSS_DMAC_BAR_SI 0x00003FF0 // Size Indicator
+#define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1
+#define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_DMAC_BAR1_SIZE 0x1000
+#define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID
+#define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt
+#define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000
+#define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID
+#define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version
+#define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status
+#define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID
+#define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// LPSS I2C Module
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7
+
+#define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
+#define B_PCH_LPSS_I2C_STSCMD_SSE BIT30 // Signaled System Error
+#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPSS_I2C_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_LPSS_I2C_STSCMD_STA BIT27 // Signaled Target Abort
+#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_LPSS_I2C_CLHB 0x0C
+#define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_LPSS_I2C_BAR 0x10 // BAR
+#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_I2C_BAR_SIZE 0x1000
+#define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12
+#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
+#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_I2C_BAR1_SIZE 0x1000
+#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID
+#define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt
+#define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000
+#define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID
+#define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version
+#define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status
+#define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID
+#define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// LPSS I2C Module
+// Memory Space Registers
+//
+#define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset
+#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
+#define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
+
+//
+// LPSS PWM Modules
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2
+
+#define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command
+#define B_PCH_LPSS_PWM_STSCMD_SSE BIT30 // Signaled System Error
+#define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPSS_PWM_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_LPSS_PWM_STSCMD_STA BIT27 // Signaled Target Abort
+#define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_LPSS_PWM_CLHB 0x0C
+#define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_LPSS_PWM_BAR 0x10 // BAR
+#define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_PWM_BAR_SIZE 0x1000
+#define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12
+#define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1
+#define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_PWM_BAR1_SIZE 0x1000
+#define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID
+#define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt
+#define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000
+#define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID
+#define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version
+#define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status
+#define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID
+#define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// LPSS PWM Module
+// Memory Space Registers
+//
+#define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset
+#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
+#define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
+
+//
+// PWM2 CTRL Registers
+//
+#define R_PCH_LPSS_PWM_CTRL 0x0 // PWM2 Control register
+#define R_PCH_LPSS_PWM_CTRL_PWM_ENABLE BIT31 // PWM_ENABLE
+#define R_PCH_LPSS_PWM_CTRL_PWM_SW_UPDATE BIT30 // PWM_SW_UPDATE
+
+//
+// LPSS HSUART Modules
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4
+
+#define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command
+#define B_PCH_LPSS_HSUART_STSCMD_SSE BIT30 // Signaled System Error
+#define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPSS_HSUART_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_LPSS_HSUART_STSCMD_STA BIT27 // Signaled Target Abort
+#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_LPSS_HSUART_CLHB 0x0C
+#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_LPSS_HSUART_BAR 0x10 // BAR
+#define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000
+#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12
+#define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1
+#define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_HSUART_BAR1_SIZE 0x1000
+#define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID
+#define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt
+#define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000
+#define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID
+#define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version
+#define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status
+#define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID
+#define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// LPSS HSUART Module
+// Memory Space Registers
+//
+#define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters
+#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
+#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
+#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
+#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
+
+#define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset
+#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
+#define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
+
+//
+// LPSS SPI Module
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI2 6
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI3 7
+
+#define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command
+#define B_PCH_LPSS_SPI_STSCMD_SSE BIT30 // Signaled System Error
+#define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // Received Master Abort
+#define B_PCH_LPSS_SPI_STSCMD_RTA BIT28 // Received Target Abort
+#define B_PCH_LPSS_SPI_STSCMD_STA BIT27 // Signaled Target Abort
+#define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_LPSS_SPI_CLHB 0x0C
+#define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_LPSS_SPI_BAR 0x10 // BAR
+#define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_SPI_BAR_SIZE 0x1000
+#define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12
+#define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1
+#define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_LPSS_SPI_BAR1_SIZE 0x1000
+#define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID
+#define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt
+#define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000
+#define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID
+#define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version
+#define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status
+#define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID
+#define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// LPSS SPI Module
+// Memory Space Registers
+//
+#define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters
+#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
+#define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
+#define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
+#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
+
+#define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset
+#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
+#define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcie.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcie.h new file mode 100644 index 0000000000..0982a4218e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcie.h @@ -0,0 +1,549 @@ +/** @file
+ Register names for PCI-E root port devices
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+#define PCH_PCIE_MAX_ROOT_PORTS 4
+
+
+/// PCI Express Root Ports (D28:F0~F3)
+///
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
+
+#define R_PCH_PCIE_ID 0x00 // Identifiers
+#define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID
+#define V_PCH_PCIE_DEVICE_ID_0 0x22C8 // PCIE Root Port #1
+#define V_PCH_PCIE_DEVICE_ID_1 0x22C9 // PCIE Root Port #1
+#define V_PCH_PCIE_DEVICE_ID_2 0x22CA // PCIE Root Port #2
+#define V_PCH_PCIE_DEVICE_ID_3 0x22CB // PCIE Root Port #2
+#define V_PCH_PCIE_DEVICE_ID_4 0x22CC // PCIE Root Port #3
+#define V_PCH_PCIE_DEVICE_ID_5 0x22CD // PCIE Root Port #3
+#define V_PCH_PCIE_DEVICE_ID_6 0x22CE // PCIE Root Port #4
+#define V_PCH_PCIE_DEVICE_ID_7 0x22CF // PCIE Root Port #4
+#define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID
+#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define R_PCH_PCIE_CMD_PSTS 0x04 // Device Command; Primary Status
+#define S_PCH_PCIE_CMD_PSTS 4
+#define B_PCH_PCIE_CMD_PSTS_DPE BIT31 // Detected Parity Error
+#define B_PCH_PCIE_CMD_PSTS_SSE BIT30 // Signaled System Error
+#define B_PCH_PCIE_CMD_PSTS_RMA BIT29 // Received Master Abort
+#define B_PCH_PCIE_CMD_PSTS_RTA BIT28 // Received Target Abort
+#define B_PCH_PCIE_CMD_PSTS_STA BIT27 // Signaled Target Abort
+#define B_PCH_PCIE_CMD_PSTS_DEV_STS (BIT26 | BIT25) // Primary DEVSEL# Timing Status
+#define B_PCH_PCIE_CMD_PSTS_DPED BIT24 // Master Data Parity Error Detected
+#define B_PCH_PCIE_CMD_PSTS_FB2BC BIT23 // Primary Fast Back to Back Capable
+#define B_PCH_PCIE_CMD_PSTS_66MHZ_CAP BIT21 // Primary 66 MHz Capable
+#define B_PCH_PCIE_CMD_PSTS_CAP_LST BIT20 // Capabilities List
+#define B_PCH_PCIE_CMD_PSTS_INTR_STS BIT19 // Interrupt Status
+#define B_PCH_PCIE_CMD_PSTS_ID BIT10 // Interrupt Disable
+#define B_PCH_PCIE_CMD_PSTS_FBE BIT9 // Fast Back to Back Enable
+#define B_PCH_PCIE_CMD_PSTS_SEE BIT8 // SERR# Enable
+#define B_PCH_PCIE_CMD_PSTS_WCC BIT7 // Wait Cycle Control
+#define B_PCH_PCIE_CMD_PSTS_PER BIT6 // Parity Error Response Enable
+#define B_PCH_PCIE_CMD_PSTS_VPS BIT5 // VGA Palette Snoop
+#define B_PCH_PCIE_CMD_PSTS_MWIE BIT4 // Memory Write and Invalidate Enable
+#define B_PCH_PCIE_CMD_PSTS_SCE BIT3 // Special Cycle Enable
+#define B_PCH_PCIE_CMD_PSTS_BME BIT2 // Bus Master Enable
+#define B_PCH_PCIE_CMD_PSTS_MSE BIT1 // Memory Space Enable
+#define B_PCH_PCIE_CMD_PSTS_IOSE BIT0 // I/O Space Enable
+
+#define R_PCH_PCIE_RID_CC 0x08 // Revision ID; Class Code
+#define B_PCH_PCIE_RID_CC_BCC 0xFF000000 // Base Class Code
+#define B_PCH_PCIE_RID_CC_SCC 0x00FF0000 // Sub Class Code
+#define B_PCH_PCIE_RID_CC_PI 0x0000FF00 // Programming Interface
+#define B_PCH_PCIE_RID_CC_RID 0x000000FF // Revision ID
+
+#define R_PCH_PCIE_CLS_PLT_HTYPE 0x0C // Cache Line size; Primary Latency Timer; Header Type
+#define B_PCH_PCIE_CLS_PLT_HTYPE_MFD BIT23 // Multi-function Device
+#define B_PCH_PCIE_CLS_PLT_HTYPE_HTYPE 0x007F0000 // Header Type
+#define B_PCH_PCIE_CLS_PLT_HTYPE_CT 0x0000F800 // Latency Count
+#define B_PCH_PCIE_CLS_PLT_HTYPE_LS 0x000000FF // Line Size
+
+#define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer
+#define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer
+#define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number
+#define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number
+#define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number
+
+#define R_PCH_PCIE_IOBL_SSTS 0x1C // I/O Base and Limit; Secondary Status
+#define B_PCH_PCIE_IOBL_SSTS_DPE BIT31 // Detected Parity Error
+#define B_PCH_PCIE_IOBL_SSTS_RSE BIT30 // Received System Error
+#define B_PCH_PCIE_IOBL_SSTS_RMA BIT29 // Received Master Abort
+#define B_PCH_PCIE_IOBL_SSTS_RTA BIT28 // Received Target Abort
+#define B_PCH_PCIE_IOBL_SSTS_STA BIT27 // Signaled Target Abort
+#define B_PCH_PCIE_IOBL_SSTS_SDTS (BIT26 | BIT25) // Secondary DEVSEL# Timing Status
+#define B_PCH_PCIE_IOBL_SSTS_DPD BIT24 // Data Parity Error Detected
+#define B_PCH_PCIE_IOBL_SSTS_SFBC BIT23 // Secondary Fast Back to Back Capable
+#define B_PCH_PCIE_IOBL_SSTS_SC66 BIT22 // Secondary 66 MHz Capable
+#define B_PCH_PCIE_IOBL_SSTS_IOLA 0xF000 // I/O Address Limit
+#define B_PCH_PCIE_IOBL_SSTS_IOLC 0x0F00 // I/O Limit Address Capability
+#define B_PCH_PCIE_IOBL_SSTS_IOBA 0x00F0 // I/O Base Address
+#define B_PCH_PCIE_IOBL_SSTS_IOBC 0x000F // I/O Base Address Capability
+
+#define R_PCH_PCIE_MBL 0x20 // Memory Base and Limit
+#define B_PCH_PCIE_MBL_ML 0xFFF00000 // Memory Limit
+#define B_PCH_PCIE_MBL_MB 0x0000FFF0 // Memory Base
+
+#define R_PCH_PCIE_PMBL 0x24 // Prefetchable Memory Base and Limit
+#define B_PCH_PCIE_PMBL_PML 0xFFF00000 // Prefetchable Memory Limit
+#define B_PCH_PCIE_PMBL_I64L 0x000F0000 // 64-bit Indicator
+#define B_PCH_PCIE_PMBL_PMB 0x0000FFF0 // Prefetchable Memory Base
+#define B_PCH_PCIE_PMBL_I64B 0x0000000F // 64-bit Indicator
+
+#define R_PCH_PCIE_PMBU32 0x28 // Prefetchable Memory Base Upper 32 Bits
+#define B_PCH_PCIE_PMBU32 0xFFFFFFFF // Prefetchable Memory Base Upper Portion
+
+#define R_PCH_PCIE_PMLU32 0x2C // Prefetchable Memory Limit Upper 32 Bits
+#define B_PCH_PCIE_PMLU32 0xFFFFFFFF // Prefetchable Memory Limit Upper Portion
+
+#define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer
+#define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer
+
+#define R_PCH_PCIE_INTR_BCTRL 0x3C // Interrupt Information; Bridge Control
+#define B_PCH_PCIE_INTR_BCTRL_DTSE BIT27 // Discard Timer SERR# Enable
+#define B_PCH_PCIE_INTR_BCTRL_DTS BIT26 // Discard Timer Status
+#define B_PCH_PCIE_INTR_BCTRL_SDT BIT25 // Secondary Discard Timer
+#define B_PCH_PCIE_INTR_BCTRL_PDT BIT24 // Primary Discard Timer
+#define B_PCH_PCIE_INTR_BCTRL_FBE BIT23 // Fast Back to Back Enable
+#define B_PCH_PCIE_INTR_BCTRL_SBR BIT22 // Secondary Bus Reset
+#define B_PCH_PCIE_INTR_BCTRL_MAM BIT21 // Master Abort Mode
+#define B_PCH_PCIE_INTR_BCTRL_V16 BIT20 // VGA 16-bit Decode
+#define B_PCH_PCIE_INTR_BCTRL_VE BIT19 // VGA Enable
+#define B_PCH_PCIE_INTR_BCTRL_IE BIT18 // ISA Enable
+#define B_PCH_PCIE_INTR_BCTRL_SE BIT17 // SERR# Enable
+#define B_PCH_PCIE_INTR_BCTRL_PERE BIT16 // Parity Error Response Enable
+#define B_PCH_PCIE_INTR_BCTRL_IPIN 0xFF00 // Interrupt Pin
+#define B_PCH_PCIE_INTR_BCTRL_ILINE 0x00FF // Interrupt Line
+
+#define R_PCH_PCIE_CLIST_XCAP 0x40 // Capabilities List; PCI Express Capabilities
+#define B_PCH_PCIE_CLIST_XCAP_IMN 0x3E000000 // Interrupt Message Number
+#define B_PCH_PCIE_CLIST_XCAP_SI BIT24 // Slot Implemented
+#define B_PCH_PCIE_CLIST_XCAP_DT 0x00F00000 // Device / Port Type
+#define B_PCH_PCIE_CLIST_XCAP_CV 0x000F0000 // Capability Version
+#define B_PCH_PCIE_CLIST_XCAP_NEXT 0x0000FF00 // Next Capabilities
+#define B_PCH_PCIE_CLIST_XCAP_CID 0x000000FF // Capability ID
+
+#define R_PCH_PCIE_DCAP 0x44 // Device Capabilities
+#define S_PCH_PCIE_DCAP 4
+#define B_PCH_PCIE_DCAP_CSPS 0x0C000000 // Captured Slot Power Limit Scale (Not Supported)
+#define B_PCH_PCIE_DCAP_CSPV 0x03FC0000 // Captured Slot Power Limit Value (Not Supported)
+#define B_PCH_PCIE_DCAP_RBER BIT15 // Role Based Error Reporting
+#define B_PCH_PCIE_DCAP_PIP BIT14 // Reserved, previously was Power Indicator Present
+#define B_PCH_PCIE_DCAP_AIP BIT13 // Reserved, previously was Attention Indicator Present
+#define B_PCH_PCIE_DCAP_ABP BIT12 // Reserved, previously was Attention Button Present
+#define B_PCH_PCIE_DCAP_E1AL 0x00000E00 // Endpoint L1 Acceptable Latency
+#define B_PCH_PCIE_DCAP_E0AL 0x000001C0 // Endpoint L0 Acceptable Latency
+#define B_PCH_PCIE_DCAP_ETFS BIT5 // Extended Tag Field Supported
+#define B_PCH_PCIE_DCAP_PFS 0x00000018 // Phantom Function Supported
+#define B_PCH_PCIE_DCAP_MPS 0x00000007 // Max Payload Size Supported
+
+#define R_PCH_PCIE_DCTL_DSTS 0x48 // Device Control; Device Status
+#define S_PCH_PCIE_DCTL_DSTS 4
+#define B_PCH_PCIE_DCTL_DSTS_TDP BIT21 // Transactions Pending
+#define B_PCH_PCIE_DCTL_DSTS_APD BIT20 // AUX Power Detected
+#define B_PCH_PCIE_DCTL_DSTS_URD BIT19 // Unsupported Request Detected
+#define B_PCH_PCIE_DCTL_DSTS_FED BIT18 // Fatal Error Detected
+#define B_PCH_PCIE_DCTL_DSTS_NFED BIT17 // Non-Fatal Error Detected
+#define B_PCH_PCIE_DCTL_DSTS_CED BIT16 // Correctable Error Detected
+#define B_PCH_PCIE_DCTL_DSTS_MRRS 0x7000 // Max Read Request Size
+#define B_PCH_PCIE_DCTL_DSTS_ENS BIT11 // Enable No Snoop
+#define B_PCH_PCIE_DCTL_DSTS_APME BIT10 // Aux Power PM Enable
+#define B_PCH_PCIE_DCTL_DSTS_PFE BIT9 // Phantom Function Enable (Not Supported)
+#define B_PCH_PCIE_DCTL_DSTS_ETFE BIT8 // Extended Tag Field Enable (Not Supported)
+#define B_PCH_PCIE_DCTL_DSTS_MPS (BIT7 | BIT6 | BIT5) // Max Payload Size
+#define B_PCH_PCIE_DCTL_DSTS_ERO BIT4 // Enable Relaxed Ordering (Not Supported)
+#define B_PCH_PCIE_DCTL_DSTS_URE BIT3 // Unsupported Request Reporting Enable
+#define B_PCH_PCIE_DCTL_DSTS_FEE BIT2 // Fatal Error Reporting Enable
+#define B_PCH_PCIE_DCTL_DSTS_NFE BIT1 // Non-Fatal Error Reporting Enable
+#define B_PCH_PCIE_DCTL_DSTS_CEE BIT0 // Correctable Error Reporting Enable
+
+#define R_PCH_PCIE_LCAP 0x4C // Link Capabilities
+#define B_PCH_PCIE_LCAP_PN 0xFF000000 // Port Number
+#define V_PCH_PCIE_LCAP_PN1 (1 << 24) // Port Number 1
+#define V_PCH_PCIE_LCAP_PN2 (2 << 24) // Port Number 2
+#define V_PCH_PCIE_LCAP_PN3 (3 << 24) // Port Number 3
+#define V_PCH_PCIE_LCAP_PN4 (4 << 24) // Port Number 4
+#define V_PCH_PCIE_LCAP_PN5 (5 << 24) // Port Number 5
+#define V_PCH_PCIE_LCAP_PN6 (6 << 24) // Port Number 6
+#define V_PCH_PCIE_LCAP_PN7 (7 << 24) // Port Number 7
+#define V_PCH_PCIE_LCAP_PN8 (8 << 24) // Port Number 8
+#define B_PCH_PCIE_LCAP_LBNC BIT21 // Link Bandwidth Notification Capability
+#define B_PCH_PCIE_LCAP_LARC BIT20 // Link Active Reporting Capable
+#define B_PCH_PCIE_LCAP_SDERC BIT19 // Surprise Down Error Reporting Capable
+#define B_PCH_PCIE_LCAP_CPM BIT18 // Clock Power Management
+#define B_PCH_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) // L1 Exit Latency
+#define B_PCH_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) // L0s Exit Latency
+#define B_PCH_PCIE_LCAP_APMS (BIT11 | BIT10) // Active State Link PM Support
+#define V_PCH_PCIE_LCAP_APMS_L0S (1 << 10) // L0s Entry Supported
+#define V_PCH_PCIE_LCAP_APMS_L0S_L1 (3 << 10) // Both L0s and L1 Supported
+#define B_PCH_PCIE_LCAP_MLW 0x000003F0 // Maximum Link Width
+#define B_PCH_PCIE_LCAP_SLS 0x0000000F // Supported Link Speeds
+
+#define R_PCH_PCIE_LCTL_LSTS 0x50 // Link Control; Link Status
+#define B_PCH_PCIE_LCTL_LSTS_LABS BIT31 // Link Autonomous Bandwidth Status
+#define B_PCH_PCIE_LCTL_LSTS_LBMS BIT30 // Link Bandwidth Management Status
+#define B_PCH_PCIE_LCTL_LSTS_DLLA BIT29 // Link Active
+#define B_PCH_PCIE_LCTL_LSTS_SCC BIT28 // Slot Clock Configuration
+#define B_PCH_PCIE_LCTL_LSTS_LT BIT27 // Link Training
+#define B_PCH_PCIE_LCTL_LSTS_LTE BIT26 // Reserved, previously was Link Training Error
+#define B_PCH_PCIE_LCTL_LSTS_NLW 0x03F00000 // Negotiated Link Width
+#define V_PCH_PCIE_LCTL_LSTS_NLW_1 0x00100000
+#define V_PCH_PCIE_LCTL_LSTS_NLW_2 0x00200000
+#define V_PCH_PCIE_LCTL_LSTS_NLW_4 0x00400000
+#define B_PCH_PCIE_LCTL_LSTS_LS 0x000F0000 // Current Link Speed
+#define B_PCH_PCIE_LCTL_LSTS_LABIE BIT11 // Link Autonomous Bandwidth Interrupt Enable
+#define B_PCH_PCIE_LCTL_LSTS_LBMIE BIT10 // Link Bandwidth Management Interrupt Enable
+#define B_PCH_PCIE_LCTL_LSTS_HAWD BIT9 // Hardware Autonomous Width Disable
+#define B_PCH_PCIE_LCTL_LSTS_ES BIT7 // Extended Synch
+#define B_PCH_PCIE_LCTL_LSTS_CCC BIT6 // Common Clock Configuration
+#define B_PCH_PCIE_LCTL_LSTS_RL BIT5 // Retrain Link
+#define B_PCH_PCIE_LCTL_LSTS_LD BIT4 // Link Disable
+#define B_PCH_PCIE_LCTL_LSTS_RCBC BIT3 // Read Completion Boundary
+#define B_PCH_PCIE_LCTL_LSTS_ASPM (BIT1 | BIT0) // Active State Link PM Control
+#define V_PCH_PCIE_LCTL_LSTS_ASPM_L0S 1 // L0s Entry Enabled
+#define V_PCH_PCIE_LCTL_LSTS_ASPM_L1 2 // L1 Entry Enable
+#define V_PCH_PCIE_LCTL_LSTS_ASPM_L0S_L1 3 // L0s and L1 Entry Enabled
+
+#define R_PCH_PCIE_SLCAP 0x54 // Slot Capabilities
+#define S_PCH_PCIE_SLCAP 4
+#define B_PCH_PCIE_SLCAP_PSN 0xFFF80000 // Physical Slot Number
+#define N_PCH_PCIE_SLCAP_PSN 19
+#define B_PCH_PCIE_SLCAP_NCCS BIT18 // No Command Completed Support
+#define B_PCH_PCIE_SLCAP_EMIP BIT17 // Electromechanical Interlock Present
+#define B_PCH_PCIE_SLCAP_SLS (BIT16 | BIT15) // Slot Power Limit Scale
+#define B_PCH_PCIE_SLCAP_SLV 0x00007F80 // Slot Power Limit Value
+#define B_PCH_PCIE_SLCAP_HPC BIT6 // Hot Plug Capable
+#define B_PCH_PCIE_SLCAP_HPS BIT5 // Hot Plug Surprise
+#define B_PCH_PCIE_SLCAP_PIP BIT4 // Power Indicator Present
+#define B_PCH_PCIE_SLCAP_AIP BIT3 // Attention Indicator Present
+#define B_PCH_PCIE_SLCAP_MSP BIT2 // MRL Sensor Present
+#define B_PCH_PCIE_SLCAP_PCP BIT1 // Power Controller Present
+#define B_PCH_PCIE_SLCAP_ABP BIT0 // Attention Buttion Present
+
+#define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status
+#define S_PCH_PCIE_SLCTL_SLSTS 4
+#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed
+#define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
+#define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
+#define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
+#define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
+#define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected
+#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable
+#define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control
+#define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable
+#define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
+#define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable
+
+#define R_PCH_PCIE_RCTL 0x5C // Root Control
+#define S_PCH_PCIE_RCTL 2
+#define B_PCH_PCIE_RCTL_PIE BIT3 // PME Interrupt Enable
+#define B_PCH_PCIE_RCTL_SFE BIT2 // System Error on Fatal Error Enable
+#define B_PCH_PCIE_RCTL_SNE BIT1 // System Error on Non-Fatal Error Enable
+#define B_PCH_PCIE_RCTL_SCE BIT0 // System Error on Correctable Error Enable
+
+#define R_PCH_PCIE_RSTS 0x60 // Root Status
+#define S_PCH_PCIE_RSTS 4
+#define B_PCH_PCIE_RSTS_PP BIT17 // PME PEnding
+#define B_PCH_PCIE_RSTS_PS BIT16 // PME Status
+#define B_PCH_PCIE_RSTS_RID 0x0000FFFF // PME Requestor ID
+
+#define R_PCH_PCIE_DCAP2 0x64 // Device Capabilities 2
+#define B_PCH_PCIE_DCAP2_OBFFS (BIT19 | BIT18) // Optimized Buffer Flush / Fill Supported
+#define B_PCH_PCIE_DCAP2_LTRMS BIT11 // LTR Mechanism Supported
+#define B_PCH_PCIE_DCAP2_CTDS BIT4 // Completion Timeout Disable Supported
+#define B_PCH_PCIE_DCAP2_CTRS 0xF // Completion Timeout Ranges Supported
+#define V_PCH_PCIE_DCAP2_CTRS_UNSUPPORTED 0x0
+#define V_PCH_PCIE_DCAP2_CTRS_RANGE_A 0x1 // 50 us to 10 ms
+#define V_PCH_PCIE_DCAP2_CTRS_RANGE_B 0x2 // 10 ms to 250 ms
+#define V_PCH_PCIE_DCAP2_CTRS_RANGE_C 0x4 // 250 ms to 4 s
+#define V_PCH_PCIE_DCAP2_CTRS_RANGE_D 0x8 // 4 s to 64 s
+
+#define R_PCH_PCIE_DCTL2_DSTS2 0x68 // Device Control 2; Device Status 2
+#define B_PCH_PCIE_DCTL2_DSTS2_OBFFEN (BIT14 | BIT13) // Optimized Buffer Flush / Fill Enable
+#define B_PCH_PCIE_DCTL2_DSTS2_LTRME BIT10 // LTR Mechanism Enable
+#define B_PCH_PCIE_DCTL2_DSTS2_CTD BIT4 // Completion Timeout Disable
+#define B_PCH_PCIE_DCTL2_DSTS2_CTV 0xF // Completion Timeout Value
+#define V_PCH_PCIE_DCTL2_DSTS2_CTV_DEFAULT 0x0
+#define V_PCH_PCIE_DCTL2_DSTS2_CTV_40MS_50MS 0x5
+#define V_PCH_PCIE_DCTL2_DSTS2_CTV_160MS_170MS 0x6
+#define V_PCH_PCIE_DCTL2_DSTS2_CTV_400MS_500MS 0x9
+#define V_PCH_PCIE_DCTL2_DSTS2_CTV_1P6S_1P7S 0xA
+
+#define R_PCH_PCIE_LCTL2_LSTS2 0x70 // Link Control 2; Link Status 2
+#define B_PCH_PCIE_LCTL2_LSTS2_CDL BIT16 // Current De-emphasis Level
+#define B_PCH_PCIE_LCTL2_LSTS2_CD BIT12 // Compliance De-emphasis
+#define B_PCH_PCIE_LCTL2_LSTS2_CSOS BIT11 // Compliance SOS
+#define B_PCH_PCIE_LCTL2_LSTS2_EMC BIT10 // Enter Modified Compliance
+#define B_PCH_PCIE_LCTL2_LSTS2_TM (BIT9 | BIT8 | BIT7) // Transmit Margin
+#define B_PCH_PCIE_LCTL2_LSTS2_SD BIT6 // Selectable De-emphasis
+#define B_PCH_PCIE_LCTL2_LSTS2_HASD BIT5 // Reserved. Hardware Autonomous Speed Disable
+#define B_PCH_PCIE_LCTL2_LSTS2_EC BIT4 // Enter Compliance
+#define B_PCH_PCIE_LCTL2_LSTS2_TLS (BIT3 | BIT2 | BIT1 | BIT0) // Target Link Speed
+
+#define R_PCH_PCIE_MID_MC 0x80 // Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message Control
+#define S_PCH_PCIE_MID_MC 4
+#define B_PCH_PCIE_MID_MC_C64 BIT23 // 64 Bit Address Capable
+#define B_PCH_PCIE_MID_MC_MME (BIT22 | BIT21 | BIT20) // Multiple Message Enable
+#define B_PCH_PCIE_MID_MC_MMC 0x000E0000 // Multiple Message Capable
+#define B_PCH_PCIE_MID_MC_MSIE BIT16 // MSI Enable
+#define B_PCH_PCIE_MID_MC_NEXT 0xFF00 // Next Pointer
+#define B_PCH_PCIE_MID_MC_CID 0x00FF // Capability ID
+
+#define R_PCH_PCIE_MA 0x84 // Message Signaled Interrupt Message Address
+#define S_PCH_PCIE_MA 4
+#define B_PCH_PCIE_MA_ADDR 0xFFFFFFFC // Address
+
+#define R_PCH_PCIE_MD 0x88 // Message Signaled Interrupt Message data
+#define S_PCH_PCIE_MD 2
+#define B_PCH_PCIE_MD_DATA 0xFFFF // Data
+
+#define R_PCH_PCIE_SVCAP 0x90 // Subsystem Vendor Capability
+#define S_PCH_PCIE_SVCAP 2
+#define B_PCH_PCIE_SVCAP_NEXT 0xFF00 // Next Capability
+#define B_PCH_PCIE_SVCAP_CID 0x00FF // Capability Identifier
+
+#define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs
+#define S_PCH_PCIE_SVID 4
+#define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier
+#define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier
+
+#define R_PCH_PCIE_PMCAP_PMC 0xA0 // Power Management Capability; PCI Power Management Capabilities
+#define S_PCH_PCIE_PMCAP_PMC 4
+#define B_PCH_PCIE_PMCAP_PMC_PMES 0xF8000000 // PME Support
+#define B_PCH_PCIE_PMCAP_PMC_D2S BIT26 // D2 Support
+#define B_PCH_PCIE_PMCAP_PMC_D1S BIT25 // D1 Support
+#define B_PCH_PCIE_PMCAP_PMC_AC 0x01C00000 // Aux Current
+#define B_PCH_PCIE_PMCAP_PMC_DSI BIT21 // Device Specific Initialization
+#define B_PCH_PCIE_PMCAP_PMC_PMEC BIT19 // PME Clock
+#define B_PCH_PCIE_PMCAP_PMC_VS 0x00070000 // Version
+#define B_PCH_PCIE_PMCAP_PMC_NEXT 0x0000FF00 // Next Capability
+#define B_PCH_PCIE_PMCAP_PMC_CID 0x000000FF // Capability Identifier
+
+#define R_PCH_PCIE_PMCS 0xA4 // PCI Power Management Control and Status
+#define S_PCH_PCIE_PMCS 4
+#define B_PCH_PCIE_PMCS_BPCE BIT23 // Bus Power / Clock Control Enable
+#define B_PCH_PCIE_PMCS_B23S BIT22 // B2 / B3 Support
+#define B_PCH_PCIE_PMCS_PMES BIT15 // PME Status
+#define B_PCH_PCIE_PMCS_PMEE BIT8 // PME Enable
+#define B_PCH_PCIE_PMCS_NSR BIT3 // No Soft Reset
+#define B_PCH_PCIE_PMCS_PS (BIT1 | BIT0) // Power State
+#define V_PCH_PCIE_PMCS_D0 0x00 // D0 State
+#define V_PCH_PCIE_PMCS_D3H 0x03 // D3 Hot State
+
+#define R_PCH_PCIE_MANID 0xF8 // Manufacturer's ID
+#define B_PCH_PCIE_MANID_DPID 0x0F000000 // Dot Portion of Process ID
+#define B_PCH_PCIE_MANID_SID 0x00FF0000 // Stepping Identifier
+#define B_PCH_PCIE_MANID_MID 0x0000FF00 // Manufacturing Identifier
+#define B_PCH_PCIE_MANID_PD 0x000000FF // Process / Dot
+
+#define R_PCH_PCIE_AECH 0x100 // Advanced Error Reporting Capability Header
+#define B_PCH_PCIE_AECH_NCO 0xFFF00000 // Next Capability Offset
+#define B_PCH_PCIE_AECH_CV 0x000F0000 // Capability Version
+#define B_PCH_PCIE_AECH_CID 0x0000FFFF // Capability ID
+
+#define R_PCH_PCIE_UES 0x104 // Uncorrectable Error Status
+#define S_PCH_PCIE_UES 4
+#define B_PCH_PCIE_UES_URE BIT20 // Unsupported Request Error Status
+#define B_PCH_PCIE_UES_EE BIT19 // ECRC Error Status
+#define B_PCH_PCIE_UES_MT BIT18 // Malformed TLP Status
+#define B_PCH_PCIE_UES_RO BIT17 // Receiver Overflow Status
+#define B_PCH_PCIE_UES_UC BIT16 // Unexpected Completion Status
+#define B_PCH_PCIE_UES_CA BIT15 // Completer Abort Status
+#define B_PCH_PCIE_UES_CT BIT14 // Completion Timeout Status
+#define B_PCH_PCIE_UES_FCPE BIT13 // Flow Control Protocol Error Status (Not Supported)
+#define B_PCH_PCIE_UES_PT BIT12 // Poisoned TLP Status
+#define B_PCH_PCIE_UES_DLPE BIT4 // DataLink Protocol Error Status
+#define B_PCH_PCIE_UES_TE BIT0 // Training Error Status (Not Supported)
+
+#define R_PCH_PCIE_UEM 0x108 // Uncorrectable Error Mask
+#define S_PCH_PCIE_UEM 4
+#define B_PCH_PCIE_UEM_URE BIT20 // Unsupported Request Error Mask
+#define B_PCH_PCIE_UEM_EE BIT19 // ECRC Error Mask
+#define B_PCH_PCIE_UEM_MT BIT18 // Malformed TLP Mask
+#define B_PCH_PCIE_UEM_RO BIT17 // Receiver Overflow Mask
+#define B_PCH_PCIE_UEM_UC BIT16 // Unexpected Completion Mask
+#define B_PCH_PCIE_UEM_CA BIT15 // Completer Abort Mask
+#define B_PCH_PCIE_UEM_CT BIT14 // Completion Timeout Mask
+#define B_PCH_PCIE_UEM_FCPE BIT13 // Flow Control Protocol Error Mask (Not Supported)
+#define B_PCH_PCIE_UEM_PT BIT12 // Poisoned TLP Mask
+#define B_PCH_PCIE_UEM_DLPE BIT4 // DataLink Protocol Error Mask
+#define B_PCH_PCIE_UEM_TE BIT0 // Training Error Mask (Not Supported)
+
+#define R_PCH_PCIE_UEV 0x10C // Uncorrectable Error Severity
+#define S_PCH_PCIE_UEV 4
+#define B_PCH_PCIE_UEV_URE BIT20 // Unsupported Request Error Severity
+#define B_PCH_PCIE_UEV_EE BIT19 // ECRC Error Severity
+#define B_PCH_PCIE_UEV_MT BIT18 // Malformed TLP Severity
+#define B_PCH_PCIE_UEV_RO BIT17 // Receiver Overflow Severity
+#define B_PCH_PCIE_UEV_UC BIT16 // Unexpected Completion Severity
+#define B_PCH_PCIE_UEV_CA BIT15 // Completion Abort Severity
+#define B_PCH_PCIE_UEV_CT BIT14 // Completion Timeout Severity
+#define B_PCH_PCIE_UEV_FCPE BIT13 // Flow Control Protocol Error Severity
+#define B_PCH_PCIE_UEV_PT BIT12 // Poisoned TLP Severity
+#define B_PCH_PCIE_UEV_DLPE BIT4 // Data Link Protocol Error Severity
+#define B_PCH_PCIE_UEV_TE BIT0 // Training Error Severity (Not Supported)
+
+#define R_PCH_PCIE_CES 0x110 // Correctable Error Status
+#define S_PCH_PCIE_CES 4
+#define B_PCH_PCIE_CES_ANFES BIT13 // Advisory Non-Fatal Error Status
+#define B_PCH_PCIE_CES_RTT BIT12 // Replay Timer Timeout Status
+#define B_PCH_PCIE_CES_RNR BIT8 // Replay Number Rollover Status
+#define B_PCH_PCIE_CES_BD BIT7 // Bad DLLP Status
+#define B_PCH_PCIE_CES_BT BIT6 // Bad TLP Status
+#define B_PCH_PCIE_CES_RE BIT0 // Receiver Error Status
+
+#define R_PCH_PCIE_CEM 0x114 // Correctable Error Mask
+#define S_PCH_PCIE_CEM 4
+#define B_PCH_PCIE_CEM_ANFEM BIT13 // Advisory Non-Fatal Error Mask
+#define B_PCH_PCIE_CEM_RTT BIT12 // Replay Timer Timeout Mask
+#define B_PCH_PCIE_CEM_RNR BIT8 // Replay Number Rollover Mask
+#define B_PCH_PCIE_CEM_BD BIT7 // Bad DLLP Mask
+#define B_PCH_PCIE_CEM_BT BIT6 // Bad TLP Mask
+#define B_PCH_PCIE_CEM_RE BIT0 // Receiver Error Mask
+
+#define R_PCH_PCIE_AECC 0x118 // Advanced Error Capabilities and Control
+#define S_PCH_PCIE_AECC 4
+#define B_PCH_PCIE_AECC_ECE BIT8 // ECRC Check Enable
+#define B_PCH_PCIE_AECC_ECC BIT7 // ECRC Check Capable
+#define B_PCH_PCIE_AECC_EGE BIT6 // ECRC Generation Enable
+#define B_PCH_PCIE_AECC_EGC BIT5 // ECRC Generation Capable
+#define B_PCH_PCIE_AECC_FEP 0x0000001F // First Error Pointer
+
+#define R_PCH_PCIE_HL_DW1 0x11C // Header Log DW1
+
+#define R_PCH_PCIE_HL_DW2 0x120 // Header Log DW2
+
+#define R_PCH_PCIE_HL_DW3 0x124 // Header Log DW3
+
+#define R_PCH_PCIE_HL_DW4 0x128 // Header Log DW4
+
+#define R_PCH_PCIE_REC 0x12C // Root Error Command
+#define B_PCH_PCIE_REC_FERE BIT2 // Fatal Error Report Enable
+#define B_PCH_PCIE_REC_NERE BIT1 // Non-Fatal Error Report Enable
+#define B_PCH_PCIE_REC_CERE BIT0 // Correctable Error Report Enable
+
+#define R_PCH_PCIE_RES 0x130 // Root Error Status
+#define S_PCH_PCIE_RES 4
+#define B_PCH_PCIE_RES_AEMN 0xF8000000 // Advanced Error Interrupt Message Number
+#define B_PCH_PCIE_RES_FEMR BIT6 // Fatal Error Messages Received
+#define B_PCH_PCIE_RES_NFEMR BIT5 // Non-Fatal Error Messages Received
+#define B_PCH_PCIE_RES_FUF BIT4 // First Uncorrectable Fatal
+#define B_PCH_PCIE_RES_MENR BIT3 // Multiple ERR_FATAL / NONFATAL Received
+#define B_PCH_PCIE_RES_ENR BIT2 // ERR_FATAL / NONFATAL Received
+#define B_PCH_PCIE_RES_MCR BIT1 // Multiple ERR_COR Received
+#define B_PCH_PCIE_RES_CR BIT0 // ERR_COR Received
+
+#define R_PCH_PCIE_ESID 0x134 // Error Source Identification
+#define B_PCH_PCIE_ESID_EFNFSID 0xFFFF0000 // ERR_FATAL / NONFATAL Source Identification
+#define B_PCH_PCIE_ESID_ECSID 0x0000FFFF // ERR_COR Source Identification
+
+#define R_PCH_PCIE_L1SECH 0x200 // L1 Sub-States Extended Capability Header
+#define B_PCH_PCIE_L1SECH_NCO 0xFFF00000
+#define B_PCH_PCIE_L1SECH_CV (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCIE_L1SECH_PCIEEC 0xFFFF
+
+#define R_PCH_PCIE_L1SCAP 0x204 // L1 Sub-States Capabilities
+#define B_PCH_PCIE_L1SCAP_PTV 0xF00000
+#define B_PCH_PCIE_L1SCAP_PTPOS (BIT17 | BIT16)
+#define B_PCH_PCIE_L1SCAP_PCMRT 0xFF00
+#define B_PCH_PCIE_L1SCAP_LFASL1SS BIT5 // LFAS L1 Substates Supported
+#define B_PCH_PCIE_L1SCAP_CKRQL1SS BIT4 // CLKREQ# L1 Substates Supported
+#define B_PCH_PCIE_L1SCAP_AL1SS BIT3 // ASPM L1 Substates Supported
+#define B_PCH_PCIE_L1SCAP_PL1SS BIT2 // PCI-PM L1 Substates Supported
+#define B_PCH_PCIE_L1SCAP_L1SS BIT1 // L1.SNOOZ Sub-State Supported
+#define B_PCH_PCIE_L1SCAP_L1OS BIT0 // L1.OFF Power Management Supported
+
+#define R_PCH_PCIE_L1SCTL1 0x208 // L1 Sub-States Control 1
+#define B_PCH_PCIE_L1SCTL1_L1OFFLTRTLSV (BIT31 | BIT30 | BIT29) // L1.OFF LTR Threshold Latency Scale Value
+#define B_PCH_PCIE_L1SCTL1_L1OFFLTRTLV 0x3FF0000 // L1.OFF LTR Threshold Latency Value
+#define B_PCH_PCIE_L1SCTL1_CMRT 0xFF00 // Tcommon_mode time
+#define B_PCH_PCIE_L1SCTL1_SLSM BIT4
+#define B_PCH_PCIE_L1SCTL1_AL1SE BIT3 // ASPM L1 Substates Enable
+#define B_PCH_PCIE_L1SCTL1_PPL1SE BIT2 // PCI-PM L1 Substates Enable
+#define B_PCH_PCIE_L1SCTL1_L1SE BIT1 // L1.SNOOZ Power Management Enable
+#define B_PCH_PCIE_L1SCTL1_L1OE BIT0 // L1.OFF Power Management Enable
+
+#define R_PCH_PCIE_L1SCTL2 0x20C // L1 Sub-States Control 2
+#define B_PCH_PCIE_L1SCTL2_POWT 0xF8
+#define B_PCH_PCIE_L1SCTL2_TPOS (BIT1 | BIT0)
+#define V_PCH_PCIE_L1SCTL2_TPOS_2US 0
+#define V_PCH_PCIE_L1SCTL2_TPOS_10US BIT0
+#define V_PCH_PCIE_L1SCTL2_TPOS_100US BIT1
+
+#define R_PCH_PCIE_PCIESTS1 0x328 // PCI Express Status 1
+#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 // LTSM State
+#define B_PCH_PCIE_PCIESTS1_LNKSTAT 0x00780000 // Link Status
+#define B_PCH_PCIE_PCIESTS1_REPLAYNUM (BIT18 | BIT17) // Replay Number
+#define B_PCH_PCIE_PCIESTS1_DLLRETRY BIT16 // Data Link Layer Retry
+#define B_PCH_PCIE_PCIESTS1_LANESTAT 0x0000F000 // Lane Status
+#define B_PCH_PCIE_PCIESTS1_NXTTXSEQNUM 0x00000FFF // Next Transmitted Sequence Number
+
+#define R_PCH_PCIE_PCIESTS2 0x32C // PCI Express Status 2
+#define B_PCH_PCIE_PCIESTS2_P48PNCCWSSCMES BIT31 // PCIe Port 4/8 Non-Common Clock With SSC Mode Enable Strap
+#define B_PCH_PCIE_PCIESTS2_P37PNCCWSSCMES BIT30 // PCIe Port 3/7 Non-Common Clock With SSC Mode Enable Strap
+#define B_PCH_PCIE_PCIESTS2_P26PNCCWSSCMES BIT29 // PCIe Port 2/6 Non-Common Clock With SSC Mode Enable Strap
+#define B_PCH_PCIE_PCIESTS2_P15PNCCWSSCMES BIT28 // PCIe Port 1/5 Non-Common Clock With SSC Mode Enable Strap
+#define B_PCH_PCIE_PCIESTS2_NXTRCVSEQ 0x0FFF0000 // Next Receive Sequence Number
+#define B_PCH_PCIE_PCIESTS2_LASTACKSEQNUM 0x00000FFF // Last Acknowledged Sequence Number
+
+#define R_PCH_PCIE_PCIECMMPC 0x330 // PCI Express Compliance Measurement Mode (CMM) Port Control
+#define S_PCH_PCIE_PCIECMMPC 4
+#define B_PCH_PCIE_PCIECMMPC_SYM3SEL BIT29 // CMM Symbol [3] Select
+#define B_PCH_PCIE_PCIECMMPC_SYM2SEL BIT28 // CMM Symbol [2] Select
+#define B_PCH_PCIE_PCIECMMPC_SYM1SEL BIT27 // CMM Symbol [1] Select
+#define B_PCH_PCIE_PCIECMMPC_SYM0SEL BIT26 // CMM Symbol [0] Select
+#define B_PCH_PCIE_PCIECMMPC_ERRLANENUM (BIT23 | BIT22) // CMM Error Lane Number
+#define B_PCH_PCIE_PCIECMMPC_INVERT (BIT15 | BIT14 | BIT13) // CMM Invert
+#define B_PCH_PCIE_PCIECMMPC_SYMERRNUMINV (BIT12 | BIT11 | BIT10) // CMM Symbol Error Number Invert
+#define B_PCH_PCIE_PCIECMMPC_SYMERRNUM (BIT9 | BIT8) // CMM Symbol Error Number
+#define B_PCH_PCIE_PCIECMMPC_ERRDET BIT7 // CMM Error Detected
+#define B_PCH_PCIE_PCIECMMPC_SLNINVCMM (BIT6 | BIT5) // Select Lane Number to be Inverted for CMM
+#define B_PCH_PCIE_PCIECMMPC_AUTOINVERT BIT4 // CMM AutoInvert
+#define B_PCH_PCIE_PCIECMMPC_STAT BIT3 // CMM Status
+#define B_PCH_PCIE_PCIECMMPC_INVEN BIT2 // CMM Invert Enable
+#define B_PCH_PCIE_PCIECMMPC_START BIT0 // CMM Start
+
+#define R_PCH_PCIE_PCIECMMSB 0x334 // PCI Express Compliance Measurement Mode Symbol Buffer
+#define B_PCH_PCIE_PCIECMMSB_DATA3 0xFF000000 // CMM Data [3]
+#define B_PCH_PCIE_PCIECMMSB_DATA2 0x00FF0000 // CMM Data [2]
+#define B_PCH_PCIE_PCIECMMSB_DATA1 0x0000FF00 // CMM Data [1]
+#define B_PCH_PCIE_PCIECMMSB_DATA0 0x000000FF // CMM Data [0]
+
+#define B_PCH_CFIO_PAD_PCIE_CLKREQB(X) ((X) < (PCH_PCIE_MAX_ROOT_PORTS/2)?(0x5C00 + (X * 0x8)):(0x5C08 + (0x10 * (X - 1))))
+
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcu.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcu.h new file mode 100644 index 0000000000..6f7624ad77 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsPcu.h @@ -0,0 +1,1272 @@ +/** @file
+ Register names for PCU device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCU Registers (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+typedef enum {
+ SocA0 = 0,
+ SocA1 = 1,
+ SocA2 = 2,
+ SocA3 = 3,
+ SocA4 = 4,
+ SocA5 = 5,
+ SocA6 = 6,
+ SocA7 = 7,
+ SocB0 = 8,
+ SocB1 = 9,
+ SocB2 = 10,
+ SocB3 = 11,
+ SocB4 = 12,
+ SocB5 = 13,
+ SocB6 = 14,
+ SocB7 = 15,
+ SocC0 = 16,
+ SocC1 = 17,
+ SocC2 = 18,
+ SocC3 = 19,
+ SocC4 = 20,
+ SocC5 = 21,
+ SocC6 = 22,
+ SocC7 = 23,
+ SocD0 = 24,
+ SocD1 = 25,
+ SocD2 = 26,
+ SocD3 = 27,
+ SocD4 = 28,
+ SocD5 = 29,
+ SocD6 = 30,
+ SocD7 = 31,
+ SocSteppingMax
+} SOC_STEPPING;
+
+typedef enum {
+ SocPackage17x17T4 = 0,
+ SocPackage25x27 = 1,
+ SocPackage17x17T3 = 2,
+ SocPackageCoPop = 3,
+ SocPackageMax
+} SOC_PACKAGE;
+
+#define R_PCH_LPC_REG_ID 0x00 // Identifiers Register
+#define B_PCH_LPC_DEVICE_ID 0xFFFF0000 // Device Identification
+#define B_PCH_LPC_VENDOR_ID 0x0000FFFF // Vendor Identification
+#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Vendor ID for Intel
+//
+// General PCU Device ID
+//
+#define V_PCH_LPC_DEVICE_ID_0 0x229C
+#define V_PCH_LPC_DEVICE_ID_1 0x229D
+#define V_PCH_LPC_DEVICE_ID_2 0x229E
+#define V_PCH_LPC_DEVICE_ID_3 0x229F
+
+#define R_PCH_LPC_COMMAND 0x04 // Command
+#define B_PCH_LPC_COMMAND_ID BIT10 // Interrupt Disable
+#define B_PCH_LPC_COMMAND_FBE BIT9 // Fast Back to Back Enable
+#define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable
+#define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control
+#define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable
+#define B_PCH_LPC_COMMAND_VPS BIT5 // VGA Palette Snoop
+#define B_PCH_LPC_COMMAND_MWIE BIT4 // Memory Write and Invalidate Enable
+#define B_PCH_LPC_COMMAND_SCE BIT3 // Special Cycle Enable
+#define B_PCH_LPC_COMMAND_BME BIT2 // Bus Master Enable
+#define B_PCH_LPC_COMMAND_MSE BIT1 // Memory Space Enable
+#define B_PCH_LPC_COMMAND_IOSE BIT0 // I/O Space Enable
+
+#define R_PCH_LPC_DEV_STS 0x06 // Status
+#define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error
+#define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error
+#define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort
+#define B_PCH_LPC_DEV_STS_RTA BIT12 // Received Target Abort
+#define B_PCH_LPC_DEV_STS_STA BIT11 // Signaled Target Abort
+#define B_PCH_LPC_DEV_STS_DEVT_STS (BIT10 | BIT9) // DEVSEL# Timing Status
+#define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error
+#define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable
+#define B_PCH_LPC_DEV_STS_66MHZ_CAP BIT5 // 66 MHz capable
+#define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List
+#define B_PCH_LPC_DEV_STS_INT_STS BIT3 // Interrupt Status
+
+#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code
+#define B_PCH_LPC_RID_CC_BCC 0xFF000000 // Base Class Code
+#define B_PCH_LPC_RID_CC_SCC 0x00FF0000 // Sub-Class Code
+#define B_PCH_LPC_RID_CC_PI 0x0000FF00 // Programming Interface
+#define B_PCH_LPC_RID_CC_RID 0x000000FF // Revision ID
+#define B_PCH_LPC_RID_PACKAGE_TYPE_MASK 0x03 // SoC Package Type Mask (Ignoring SoC Stepping)
+#define V_PCH_LPC_RID_PACKAGE_TYPE_17x17_T4 0x00 // 17x17 Type 4 Package
+#define V_PCH_LPC_RID_PACKAGE_TYPE_25x27 0x01 // 25x27 Package
+#define V_PCH_LPC_RID_PACKAGE_TYPE_17x17_T3 0x02 // 17x17 Type 3 Package
+#define V_PCH_LPC_RID_PACKAGE_TYPE_COPOP 0x03 // CoPOP Package
+#define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type)
+#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping
+#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping
+#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping
+#define V_PCH_LPC_RID_A3 0x0C // A3 Stepping
+#define V_PCH_LPC_RID_A4 0x80 // A4 Stepping
+#define V_PCH_LPC_RID_A5 0x84 // A5 Stepping
+#define V_PCH_LPC_RID_A6 0x88 // A6 Stepping
+#define V_PCH_LPC_RID_A7 0x8C // A7 Stepping
+#define V_PCH_LPC_RID_B0 0x10 // B0 Stepping
+#define V_PCH_LPC_RID_B1 0x14 // B1 Stepping
+#define V_PCH_LPC_RID_B2 0x18 // B2 Stepping
+#define V_PCH_LPC_RID_B3 0x1C // B3 Stepping
+#define V_PCH_LPC_RID_B4 0x90 // B4 Stepping
+#define V_PCH_LPC_RID_B5 0x94 // B5 Stepping
+#define V_PCH_LPC_RID_B6 0x98 // B6 Stepping
+#define V_PCH_LPC_RID_B7 0x9C // B7 Stepping
+#define V_PCH_LPC_RID_C0 0x20 // C0 Stepping
+#define V_PCH_LPC_RID_C1 0x24 // C1 Stepping
+#define V_PCH_LPC_RID_C2 0x28 // C2 Stepping
+#define V_PCH_LPC_RID_C3 0x2C // C3 Stepping
+#define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping
+#define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping
+#define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping
+#define V_PCH_LPC_RID_C7 0xAC // C7 Stepping
+
+#define R_PCH_LPC_MLT 0x0D // Master Latency Timer
+#define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count
+
+#define R_PCH_LPC_HEADTYP 0x0E // Header Type
+#define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device
+#define B_PCH_LPC_HEADTYP_HT 0x7F // Header Type
+
+#define R_PCH_LPC_SS 0x2C // Subsystem ID & Vendor ID
+#define B_PCH_LPC_SS_SSID 0xFFFF0000 // Subsystem ID
+#define B_PCH_LPC_SS_SSVID 0x0000FFFF // Subsystem Vendor ID
+
+#define R_PCH_LPC_CAP_LIST 0x34 // Capability List
+#define B_PCH_LPC_CAP_LIST_CP 0xFF // Capability Pointer
+
+#define R_PCH_LPC_ACPI_BASE 0x40 // ABASE, 16bit
+#define B_PCH_LPC_ACPI_BASE_BAR 0x0000FF80 // Base Address, 128 Bytes
+#define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_ACPI_BASE_MEMI BIT0 // Memory Space Indication
+
+#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes
+#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00 // Base Address
+#define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_PMC_BASE_MEMI BIT0 // Memory Space Indication
+
+#define R_PCH_LPC_IO_BASE 0x4C // IOBASE, 32bit
+#define B_PCH_LPC_IO_BASE_BAR 0xFFFC0000 // Base Address, 256 KiloBytes
+#define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_IO_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_IO_BASE_MEMI BIT0 // Memory Space Indication
+
+#define R_PCH_LPC_ILB_BASE 0x50 // IBASE, 32bit
+#define B_PCH_LPC_ILB_BASE_BAR 0xFFFFE000 // Base Address, 8 KiloBytes
+#define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_ILB_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_ILB_BASE_MEMI BIT0 // Memory Space Indication
+
+#define R_PCH_LPC_SPI_BASE 0x54 // SBASE, 32bit
+#define B_PCH_LPC_SPI_BASE_BAR 0xFFFFFE00 // Base Address, 512 bytes
+#define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_SPI_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_SPI_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_SPI_BASE_MEMI BIT0 // Memory Space Indicator
+
+#define R_PCH_LPC_MPHY_BASE 0x58 // MPBASE, 32bit
+#define B_PCH_LPC_MPHY_BASE_BAR 0xFFF00000 // Base Address, 1 MegaByte
+#define B_PCH_LPC_MPHY_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_MPHY_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_MPHY_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_MPHY_BASE_MEMI BIT0 // Memory Space Indicator
+
+#define R_PCH_LPC_PUNIT_BASE 0x5C // PUBASE, 32bit
+#define B_PCH_LPC_PUNIT_BASE_BAR 0xFFFFF800 // Base Address, 2 KiloBytes
+#define B_PCH_LPC_PUNIT_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_LPC_PUNIT_BASE_ADDRNG BIT2 // Address Range
+#define B_PCH_LPC_PUNIT_BASE_EN BIT1 // Enable Bit
+#define B_PCH_LPC_PUNIT_BASE_MEMI BIT0 // Memory Space Indicator
+
+#define R_PCH_LPC_UART_CTRL 0x80 // UART Control
+#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
+
+#define R_PCH_LPC_FWH_BIOS_DEC 0xD8 // BIOS Decode Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EE0 BIT12 // E0-E8 Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_ED8 BIT11 // D8-DF Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_ED0 BIT10 // D0-D8 Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EC8 BIT9 // C8-CF Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_LFE BIT7 // Legacy F Segment Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_E70 BIT3 // 70-7F Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_E50 BIT1 // 50-5F Enable
+#define B_PCH_LPC_FWH_BIOS_DEC_E40 BIT0 // 40-4F Enable
+
+#define R_PCH_LPC_FDCAP 0xE0 // Feature Detection Capability ID
+#define B_PCH_LPC_FDCAP_NEXT 0xFF00 // Next Capability
+#define B_PCH_LPC_FDCAP_CAPID 0x00FF // Capability ID
+
+#define R_PCH_LPC_FDLEN 0xE2 // Feature Detection Capability Length
+#define B_PCH_LPC_FDLEN_CAPLEN 0xFF // Capability Length
+
+#define R_PCH_LPC_FDVER 0xE3 // Feature Detection Capability Version
+#define B_PCH_LPC_FDVER_VSCID 0xF0 // Vendor Specific Capability ID
+#define B_PCH_LPC_FDVER_CAPVER 0x0F // Capability Version
+
+#define R_PCH_LPC_FVECTIDX 0xE4 // Feature Vector Index
+
+#define R_PCH_LPC_FVECTD 0xE8 // Feature Vector Data
+
+#define R_PCH_LPC_RCBA 0xF0 // RCBA, 32bit
+#define B_PCH_LPC_RCBA_BAR 0xFFFFFC00 // Base Address, 1 KiloByte
+#define B_PCH_LPC_RCBA_EN BIT0 // Enable Bit
+
+//
+// iLB Memory Space Registers (IBASE)
+//
+#define R_PCH_ILB_ACPI_CNT 0x00 // ACPI Control
+#define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_9 0 // IRQ9
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_10 BIT0 // IRQ10
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_11 BIT1 // IRQ11
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_DIS (BIT1 | BIT0) // Routing Disabled
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20 BIT2 // IRQ20 (Only if APIC enabled)
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_21 (BIT2 | BIT0) // IRQ21 (Only if APIC enabled)
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_22 (BIT2 | BIT1) // IRQ22 (Only if APIC enabled)
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled)
+
+#define R_PCH_ILB_MC 0x04 // Miscellaneous Control
+#define B_PCH_ILB_MC_AME BIT0 // Alternate Access Mode Enable
+
+#define R_PCH_ILB_PIRQA_ROUT 0x08 // PIRQA Routing Control
+#define R_PCH_ILB_PIRQB_ROUT 0x09 // PIRQB Routing Control
+#define R_PCH_ILB_PIRQC_ROUT 0x0A // PIRQC Routing Control
+#define R_PCH_ILB_PIRQD_ROUT 0x0B // PIRQD Routing Control
+#define R_PCH_ILB_PIRQE_ROUT 0x0C // PIRQE Routing Control
+#define R_PCH_ILB_PIRQF_ROUT 0x0D // PIRQF Routing Control
+#define R_PCH_ILB_PIRQG_ROUT 0x0E // PIRQG Routing Control
+#define R_PCH_ILB_PIRQH_ROUT 0x0F // PIRQH Routing Control
+//
+// Bit values are the same for R_PCH_ILB_PIRQA_ROUT to R_PCH_ILB_PIRQH_ROUT
+//
+#define B_PCH_ILB_PIRQX_ROUT_IRQEN BIT7 // Interrupt Routing Enable
+#define B_PCH_ILB_PIRQX_ROUT 0x0F // IRQ Routing
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_3 0x03 // Route to IRQ3
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_4 0x04 // Route to IRQ4
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_5 0x05 // Route to IRQ5
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_6 0x06 // Route to IRQ6
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_7 0x07 // Route to IRQ7
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_9 0x09 // Route to IRQ9
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_10 0x0A // Route to IRQ10
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_11 0x0B // Route to IRQ11
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_12 0x0C // Route to IRQ12
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_14 0x0E // Route to IRQ14
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_15 0x0F // Route to IRQ15
+
+#define R_PCH_ILB_SERIRQ_CNT 0x10 // Serial IRQ Control
+#define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode
+
+#define R_PCH_ILB_ULKMC 0x14 // USB Legacy Keyboard / Mouse Control
+#define B_PCH_ILB_ULKMC_TRAPBY64W BIT11 // SMI Caused by Port 64 Write
+#define B_PCH_ILB_ULKMC_TRAPBY64R BIT10 // SMI Caused by Port 64 Read
+#define B_PCH_ILB_ULKMC_TRAPBY60W BIT9 // SMI Caused by Port 60 Write
+#define B_PCH_ILB_ULKMC_TRAPBY60R BIT8 // SMI Caused by Port 60 Read
+#define B_PCH_ILB_ULKMC_64WEN BIT3 // SMI on Port 64 Writes Enable
+#define B_PCH_ILB_ULKMC_64REN BIT2 // SMI on Port 64 Reads Enable
+#define B_PCH_ILB_ULKMC_60WEN BIT1 // SMI on Port 60 Writes Enable
+#define B_PCH_ILB_ULKMC_60REN BIT0 // SMI on Port 60 Reads Enable
+
+#define R_PCH_ILB_FWH_BIOS_SEL 0x18 // FWH ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_F8 0xF0000000 // F8-FF ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_F0 0x0F000000 // F0-F7 ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_E8 0x00F00000 // E8-EF ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_E0 0x000F0000 // E0-E7 ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_D8 0x0000F000 // D8-DF ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_D0 0x00000F00 // D0-D7 ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_C8 0x000000F0 // C8-CF ID Select
+#define B_PCH_ILB_FWH_BIOS_SEL_C0 0x0000000F // C0-C7 ID Select
+
+#define R_PCH_ILB_BIOS_CNTL 0x1C // BIOS Control
+#define S_PCH_ILB_BIOS_CNTL 4
+#define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable
+#define B_PCH_ILB_BIOS_CNTL_LE BIT1 // Lock Enable
+#define N_PCH_ILB_BIOS_CNTL_LE 1
+#define B_PCH_ILB_BIOS_CNTL_WP BIT0 // Write Protect
+
+#define R_PCH_ILB_D0IR 0x20 // Device 0 Interrupt Route
+#define R_PCH_ILB_D1IR 0x22 // Device 1 Interrupt Route
+#define R_PCH_ILB_D2IR 0x24 // Device 2 Interrupt Route
+#define R_PCH_ILB_D3IR 0x26 // Device 3 Interrupt Route
+#define R_PCH_ILB_D4IR 0x28 // Device 4 Interrupt Route
+#define R_PCH_ILB_D5IR 0x2A // Device 5 Interrupt Route
+#define R_PCH_ILB_D6IR 0x2C // Device 6 Interrupt Route
+#define R_PCH_ILB_D7IR 0x2E // Device 7 Interrupt Route
+#define R_PCH_ILB_D8IR 0x30 // Device 8 Interrupt Route
+#define R_PCH_ILB_D9IR 0x32 // Device 9 Interrupt Route
+#define R_PCH_ILB_D10IR 0x34 // Device 10 Interrupt Route
+#define R_PCH_ILB_D11IR 0x36 // Device 11 Interrupt Route
+#define R_PCH_ILB_D12IR 0x38 // Device 12 Interrupt Route
+#define R_PCH_ILB_D13IR 0x3A // Device 13 Interrupt Route
+#define R_PCH_ILB_D14IR 0x3C // Device 14 Interrupt Route
+#define R_PCH_ILB_D15IR 0x3E // Device 15 Interrupt Route
+#define R_PCH_ILB_D16IR 0x40 // Device 16 Interrupt Route
+#define R_PCH_ILB_D17IR 0x42 // Device 17 Interrupt Route
+#define R_PCH_ILB_D18IR 0x44 // Device 18 Interrupt Route
+#define R_PCH_ILB_D19IR 0x46 // Device 19 Interrupt Route
+#define R_PCH_ILB_D20IR 0x48 // Device 20 Interrupt Route
+#define R_PCH_ILB_D21IR 0x4A // Device 21 Interrupt Route
+#define R_PCH_ILB_D22IR 0x4C // Device 22 Interrupt Route
+#define R_PCH_ILB_D23IR 0x4E // Device 23 Interrupt Route
+#define R_PCH_ILB_D24IR 0x50 // Device 24 Interrupt Route
+#define R_PCH_ILB_D25IR 0x52 // Device 25 Interrupt Route
+#define R_PCH_ILB_D26IR 0x54 // Device 26 Interrupt Route
+#define R_PCH_ILB_D27IR 0x56 // Device 27 Interrupt Route
+#define R_PCH_ILB_D28IR 0x58 // Device 28 Interrupt Route
+#define R_PCH_ILB_D29IR 0x5A // Device 29 Interrupt Route
+#define R_PCH_ILB_D30IR 0x5C // Device 30 Interrupt Route
+#define R_PCH_ILB_D31IR 0x5E // Device 31 Interrupt Route
+
+#define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) // INTD Mask
+#define V_PCH_ILB_DXXIR_IDR_PIRQA 0 // INTD Mapping to IRQ A
+#define V_PCH_ILB_DXXIR_IDR_PIRQB BIT12 // INTD Mapping to IRQ B
+#define V_PCH_ILB_DXXIR_IDR_PIRQC BIT13 // INTD Mapping to IRQ C
+#define V_PCH_ILB_DXXIR_IDR_PIRQD (BIT13 | BIT12) // INTD Mapping to IRQ D
+#define V_PCH_ILB_DXXIR_IDR_PIRQE BIT14 // INTD Mapping to IRQ E
+#define V_PCH_ILB_DXXIR_IDR_PIRQF (BIT14 | BIT12) // INTD Mapping to IRQ F
+#define V_PCH_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) // INTD Mapping to IRQ G
+#define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H
+
+#define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) // INTC Mask
+#define V_PCH_ILB_DXXIR_ICR_PIRQA 0 // INTC Mapping to IRQ A
+#define V_PCH_ILB_DXXIR_ICR_PIRQB BIT8 // INTC Mapping to IRQ B
+#define V_PCH_ILB_DXXIR_ICR_PIRQC BIT9 // INTC Mapping to IRQ C
+#define V_PCH_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) // INTC Mapping to IRQ D
+#define V_PCH_ILB_DXXIR_ICR_PIRQE BIT10 // INTC Mapping to IRQ E
+#define V_PCH_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) // INTC Mapping to IRQ F
+#define V_PCH_ILB_DXXIR_ICR_PIRQG (BIT10 | BIT9) // INTC Mapping to IRQ G
+#define V_PCH_ILB_DXXIR_ICR_PIRQH (BIT10 | BIT9 | BIT8) // INTC Mapping to IRQ H
+
+#define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask
+#define V_PCH_ILB_DXXIR_IBR_PIRQA 0 // INTB Mapping to IRQ A
+#define V_PCH_ILB_DXXIR_IBR_PIRQB BIT4 // INTB Mapping to IRQ B
+#define V_PCH_ILB_DXXIR_IBR_PIRQC BIT5 // INTB Mapping to IRQ C
+#define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) // INTB Mapping to IRQ D
+#define V_PCH_ILB_DXXIR_IBR_PIRQE BIT6 // INTB Mapping to IRQ E
+#define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F
+#define V_PCH_ILB_DXXIR_IBR_PIRQG (BIT6 | BIT5) // INTB Mapping to IRQ G
+#define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H
+
+#define B_PCH_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) // INTA Mask
+#define V_PCH_ILB_DXXIR_IAR_PIRQA 0 // INTA Mapping to IRQ A
+#define V_PCH_ILB_DXXIR_IAR_PIRQB BIT0 // INTA Mapping to IRQ B
+#define V_PCH_ILB_DXXIR_IAR_PIRQC BIT1 // INTA Mapping to IRQ C
+#define V_PCH_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) // INTA Mapping to IRQ D
+#define V_PCH_ILB_DXXIR_IAR_PIRQE BIT2 // INTA Mapping to IRQ E
+#define V_PCH_ILB_DXXIR_IAR_PIRQF (BIT2 | BIT0) // INTA Mapping to IRQ F
+#define V_PCH_ILB_DXXIR_IAR_PIRQG (BIT2 | BIT1) // INTA Mapping to IRQ G
+#define V_PCH_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H
+
+#define R_PCH_ILB_OIC 0x60 // Other Interrupt Controller
+#define B_PCH_ILB_OIC_SIRQEN BIT12 // Serial IRQ Enable
+#define B_PCH_ILB_OIC_AEN BIT8 // APIC Enable
+
+#define R_PCH_ILB_RTC_CONF 0x64 // RTC Control
+#define B_PCH_ILB_RTC_CONF_UCMOS_LOCK BIT1 // Upper 128 Byte Lock
+#define B_PCH_ILB_RTC_CONF_LCMOS_LOCK BIT0 // Lower 128 Byte Lock
+
+#define R_PCH_ILB_BCS 0x6C // BIOS Control Status
+#define B_PCH_ILB_BCS_SMIWPEN BIT1 // SMI WPD Enable
+#define B_PCH_ILB_BCS_SMIWPST BIT0 // SMI WPD Status
+
+#define R_PCH_ILB_LE 0x70 // LE
+#define B_PCH_ILB_LE_IRQ12C BIT1 // IRQ12 Cause
+#define B_PCH_ILB_LE_IRQ1C BIT0 // IRQ1 Cause
+
+#define R_PCH_ILB_GNMI 0x80 // NMI Register
+#define S_PCH_ILB_GNMI 4
+#define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable
+#define N_PCH_ILB_GNMI_NMI2SMIEN 6
+#define B_PCH_ILB_GNMI_NMI2SMIST BIT5 // NMI to SMI Status
+#define N_PCH_ILB_GNMI_NMI2SMIST 5
+#define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW
+#define B_PCH_ILB_GNMI_NMINS BIT3 // NMI NOW Status
+#define B_PCH_ILB_GNMI_GNMIED BIT2 // GPIO NMI Edge Detection
+#define B_PCH_ILB_GNMI_GNMIE BIT1 // GPIO NMI Enable
+#define B_PCH_ILB_GNMI_GNMIS BIT0 // GPIO NMI Status
+
+#define R_PCH_ILB_LPCC 0x84 // LPC Control
+#define B_PCH_ILB_LPCC_LPCCLK_SLC BIT8 // iLPCCLK Mux Select
+#define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3
+#define B_PCH_ILB_LPCC_CLKRUN_EN BIT2 // LPC CLKRUN Protocol Enable
+#define B_PCH_ILB_LPCC_LPCCLK1EN BIT1 // Clock 1 Enable
+#define B_PCH_ILB_LPCC_LPCCLK0EN BIT0 // Clock 0 Enable
+
+#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control
+#define B_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
+//
+// ACPI and Legacy I/O Registers (ABASE)
+//
+#define R_PCH_ACPI_PM1_STS 0x00 // Power Management 1 Status
+#define S_PCH_ACPI_PM1_STS 2
+#define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status
+#define B_PCH_ACPI_PM1_STS_WAK_PCIE BIT14 // PCI Express Wake Status
+#define B_PCH_ACPI_PM1_STS_USB_CLKLESS BIT13 // USB Clockless Status
+#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 // Power Button Override Status
+#define B_PCH_ACPI_PM1_STS_RTC BIT10 // RTC Status
+#define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 // Power Button Status
+#define B_PCH_ACPI_PM1_STS_GBL BIT5 // Global Status
+#define B_PCH_ACPI_PM1_STS_TMROF BIT0 // Timer Overflow Status
+#define N_PCH_ACPI_PM1_STS_WAK 15
+#define N_PCH_ACPI_PM1_STS_PRBTNOR 11
+#define N_PCH_ACPI_PM1_STS_RTC 10
+#define N_PCH_ACPI_PM1_STS_PWRBTN 8
+#define N_PCH_ACPI_PM1_STS_GBL 5
+#define N_PCH_ACPI_PM1_STS_TMROF 0
+
+#define R_PCH_ACPI_PM1_EN 0x02 // Power Management 1 Enables
+#define S_PCH_ACPI_PM1_EN 2
+#define B_PCH_ACPI_PM1_WAK_DIS_PCIE BIT14 // PCI Express Wake Disable
+#define B_PCH_ACPI_PM1_EN_USB_CLKLESS BIT13 // USB Clockless Enable Bit
+#define B_PCH_ACPI_PM1_EN_RTC BIT10 // RTC Alarm Enable Bit
+#define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 // Power Button Enable Bit
+#define B_PCH_ACPI_PM1_EN_GBL BIT5 // Global Enable Bit
+#define B_PCH_ACPI_PM1_EN_TMROF BIT0 // Timer Overflow Interrupt Enable Bit
+#define N_PCH_ACPI_PM1_EN_RTC 10
+#define N_PCH_ACPI_PM1_EN_PWRBTN 8
+#define N_PCH_ACPI_PM1_EN_GBL 5
+#define N_PCH_ACPI_PM1_EN_TMROF 0
+
+#define R_PCH_ACPI_PM1_CNT 0x04 // Power Management 1 Control
+#define S_PCH_ACPI_PM1_CNT 4
+#define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable
+#define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) // Sleep Type
+#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 // ON (S0)
+#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 // Puts CPU in S1 state (S1)
+#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 // Suspend-to-RAM (S3)
+#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 // Suspend-to-Disk (S4)
+#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 // Soft Off (S5)
+#define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2
+#define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1 // Treated as Scratchpad Bit
+#define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0 // SCI Enable
+
+#define R_PCH_ACPI_PM1_TMR 0x08 // Power Management 1 Timer
+#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF // The timer value mask
+#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 // The timer is 24 bit overflow
+#define V_PCH_ACPI_PM1_TMR_FREQUENCY 3579545 // Timer Frequency
+#define V_PCH_ACPI_PM1_TMR_NUM_BITS 24 // Programmed to 24 not 32
+#define V_PCH_ACPI_PM1_TMR_MAX_BITS 32
+
+#define R_PCH_ACPI_GPE0a_STS 0x20 // General Purpose Event 0a Status
+#define S_PCH_ACPI_GPE0a_STS 4
+#define B_PCH_ACPI_GPE0a_STS_CORE_GPIO 0xFF000000 // CORE GPIO Status
+#define B_PCH_ACPI_GPE0a_STS_SUS_GPIO 0x00FF0000 // SUS GPIO Status
+#define B_PCH_ACPI_GPE0a_STS_TCO BIT14 // TCO Status (B0 stepping and onwards)
+#define B_PCH_ACPI_GPE0a_STS_PME_B0 BIT13 // Power Management Event Bus 0 Status
+#define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 // Battery Low Status
+#define B_PCH_ACPI_GPE0a_STS_PCI_EXP BIT9 // PCI Express Status
+#define B_PCH_ACPI_GPE0a_STS_PCIE_WAKE3 BIT8 // PCI Express Wake 3 Status
+#define B_PCH_ACPI_GPE0a_STS_PCIE_WAKE2 BIT7 // PCI Express Wake 2 Status
+#define B_PCH_ACPI_GPE0a_STS_PCIE_WAKE1 BIT6 // PCI Express Wake 1 Status
+#define B_PCH_ACPI_GPE0a_STS_GUNIT_SCI BIT5 // GUNIT SCI Status
+#define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status
+#define B_PCH_ACPI_GPE0a_STS_PCIE_WAKE0 BIT3 // PCI Express Wake 0 Status
+#define B_PCH_ACPI_GPE0a_STS_SWGPE BIT2 // Software GPE Status
+#define B_PCH_ACPI_GPE0a_STS_HOT_PLUG BIT1 // Hot Plug Status
+#define B_PCH_ACPI_GPE0a_STS_PMU_WAKEB BIT0 // PMU Wake B Status
+#define N_PCH_ACPI_GPE0a_STS_TCO 14
+#define N_PCH_ACPI_GPE0a_STS_PME_B0 13
+#define N_PCH_ACPI_GPE0a_STS_BATLOW 10
+#define N_PCH_ACPI_GPE0a_STS_PCI_EXP 9
+#define N_PCH_ACPI_GPE0a_STS_GUNIT_SCI 5
+#define N_PCH_ACPI_GPE0a_STS_PUNIT_SCI 4
+#define N_PCH_ACPI_GPE0a_STS_SWGPE 2
+#define N_PCH_ACPI_GPE0a_STS_HOT_PLUG 1
+
+#define R_PCH_ACPI_GPE0a_EN 0x28 // General Purpose Event 0a Enables
+#define S_PCH_ACPI_GPE0a_EN 4
+#define B_PCH_ACPI_GPE0a_EN_CORE_GPIO 0xFF000000 // CORE GPIO Enable
+#define B_PCH_ACPI_GPE0a_EN_SUS_GPIO 0x00FF0000 // SUS GPIO Enable
+#define B_PCH_ACPI_GPE0a_EN_TCO BIT14 // TCO Enable (B0 stepping and onwards)
+#define B_PCH_ACPI_GPE0a_EN_PME_B0 BIT13 // Power Management Event Bus 0 Enable
+#define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 // Battery Low Enable
+#define B_PCH_ACPI_GPE0a_EN_PCI_EXP BIT9 // PCI Express Enable
+#define B_PCH_ACPI_GPE0a_EN_PCIE_WAKE3 BIT8 // PCI Express Enable 3 Enable
+#define B_PCH_ACPI_GPE0a_EN_PCIE_WAKE2 BIT7 // PCI Express Enable 2 Enable
+#define B_PCH_ACPI_GPE0a_EN_PCIE_WAKE1 BIT6 // PCI Express Enable 1 Enable
+#define B_PCH_ACPI_GPE0a_EN_PCIE_WAKE0 BIT3 // PCI Express Enable 0 Enable
+#define B_PCH_ACPI_GPE0a_EN_SWGPE BIT2 // Software GPE Enable
+#define B_PCH_ACPI_GPE0a_EN_HOT_PLUG BIT1 // Hot Plug Enable
+#define B_PCH_ACPI_GPE0a_EN_PMU_WAKEB BIT0 // PMU Wake B Enable
+#define N_PCH_ACPI_GPE0a_EN_TCO 14
+#define N_PCH_ACPI_GPE0a_EN_PME_B0 13
+#define N_PCH_ACPI_GPE0a_EN_BATLOW 10
+#define N_PCH_ACPI_GPE0a_EN_PCI_EXP 9
+#define N_PCH_ACPI_GPE0a_EN_SWGPE 2
+#define N_PCH_ACPI_GPE0a_EN_HOT_PLUG 1
+
+#define R_PCH_SMI_EN 0x30 // SMI Control and Enable
+#define S_PCH_SMI_EN 4
+#define B_PCH_SMI_EN_INTEL_USB2 BIT18 // Intel USB 2 Enable
+#define B_PCH_SMI_EN_LEGACY_USB BIT17 // Legacy USB Enable
+#define B_PCH_SMI_EN_PERIODIC BIT14 // Periodic Enable
+#define B_PCH_SMI_EN_TCO BIT13 // TCO Enable
+#define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS
+#define B_PCH_SMI_EN_SWSMI_TMR BIT6 // Software SMI Timer Enable
+#define B_PCH_SMI_EN_APMC BIT5 // APMC Enable
+#define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable
+#define B_PCH_SMI_EN_BIOS BIT2 // BIOS Enable
+#define B_PCH_SMI_EN_EOS BIT1 // End of SMI
+#define B_PCH_SMI_EN_GBL_SMI BIT0 // Global SMI Enable
+#define N_PCH_SMI_EN_GPIO_UNLOCK 27
+#define N_PCH_SMI_EN_INTEL_USB2 18
+#define N_PCH_SMI_EN_LEGACY_USB 17
+#define N_PCH_SMI_EN_PERIODIC 14
+#define N_PCH_SMI_EN_TCO 13
+#define N_PCH_SMI_EN_BIOS_RLS 7
+#define N_PCH_SMI_EN_SWSMI_TMR 6
+#define N_PCH_SMI_EN_APMC 5
+#define N_PCH_SMI_EN_ON_SLP_EN 4
+#define N_PCH_SMI_EN_BIOS 2
+#define N_PCH_SMI_EN_EOS 1
+#define N_PCH_SMI_EN_GBL_SMI 0
+
+#define R_PCH_SMI_STS 0x34 // SMI Status Register
+#define S_PCH_SMI_STS 4
+#define B_PCH_SMI_STS_GUNIT_SMI BIT29 // GUNIT SMI Status
+#define B_PCH_SMI_STS_PUNIT_SMI BIT28 // PUNIT SMI Status
+#define B_PCH_SMI_STS_SPI BIT26 // SPI SMI Status
+#define B_PCH_SMI_STS_PCI_EXP BIT20 // PCI Express SMI Status
+#define B_PCH_SMI_STS_INTEL_USB2 BIT18 // Intel USB 2 Status
+#define B_PCH_SMI_STS_LEGACY_USB BIT17 // Legacy USB Status
+#define B_PCH_SMI_STS_SMBUS BIT16 // SMBUS SMI Status
+#define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status
+#define B_PCH_SMI_STS_PERIODIC BIT14 // Periodic Status
+#define B_PCH_SMI_STS_TCO BIT13 // TCO Status
+#define B_PCH_SMI_STS_GPE0 BIT9 // GPE0 Status
+#define B_PCH_SMI_STS_PM1_STS_REG BIT8 // PM1 Status Register
+#define B_PCH_SMI_STS_SWSMI_TMR BIT6 // Software SMI Timer Status
+#define B_PCH_SMI_STS_APM BIT5 // APM Status
+#define B_PCH_SMI_STS_ON_SLP_EN BIT4 // SMI On Sleep Enable Status
+#define B_PCH_SMI_STS_BIOS BIT2 // BIOS Status
+#define N_PCH_SMI_STS_SPI 26
+#define N_PCH_SMI_STS_PCI_EXP 20
+#define N_PCH_SMI_STS_INTEL_USB2 18
+#define N_PCH_SMI_STS_LEGACY_USB 17
+#define N_PCH_SMI_STS_SMBUS 16
+#define N_PCH_SMI_STS_ILB 15
+#define N_PCH_SMI_STS_PERIODIC 14
+#define N_PCH_SMI_STS_TCO 13
+#define N_PCH_SMI_STS_GPE0 9
+#define N_PCH_SMI_STS_PM1_STS_REG 8
+#define N_PCH_SMI_STS_SWSMI_TMR 6
+#define N_PCH_SMI_STS_APM 5
+#define N_PCH_SMI_STS_ON_SLP_EN 4
+#define N_PCH_SMI_STS_BIOS 2
+
+#define R_PCH_ALT_GP_SMI_EN 0x38 // Alternate GPI SMI Enable
+#define S_PCH_ALT_GP_SMI_EN 2
+#define B_PCH_ALT_GP_SMI_EN_CORE_GPIO 0xFF00 // CORE GPIO SMI Enable
+#define B_PCH_ALT_GP_SMI_EN_SUS_GPIO 0x00FF // SUS GPIO SMI Enable
+
+#define R_PCH_ALT_GP_SMI_STS 0x3A // Alternate GPI SMI Status
+#define S_PCH_ALT_GP_SMI_STS 2
+#define B_PCH_ALT_GP_SMI_STS_CORE_GPIO 0xFF00 // CORE GPIO SMI Status
+#define B_PCH_ALT_GP_SMI_STS_SUS_GPIO 0x00FF // SUS GPIO SMI Status
+
+#define R_PCH_UPRWC 0x3C // USB Per-Port Registers Write Control
+#define S_PCH_UPRWC 2
+#define B_PCH_UPRWC_WR_EN_SMI_STS BIT8 // Write Enable Status
+#define B_PCH_UPRWC_WR_EN BIT1 // USB Per-Port Registers Write Enable
+#define B_PCH_UPRWC_WR_EN_SMI_EN BIT0 // Write Enable SMI Enable
+
+#define R_PCH_ACPI_GPE_CNTL 0x40 // General Purpose Event Control
+#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 // Software GPE Control
+
+#define R_PCH_ACPI_PM2_CNT 0x50 // PM2a Control Block
+#define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0 // Scratchpad Bit
+
+#define R_PCH_TCO_RLD 0x60 // TCO Reload
+#define B_PCH_TCO_RLD_VAL 0x3FF // TCO Timer Count Value
+
+#define R_PCH_TCO_STS 0x64 // TCO Timer Status
+#define S_PCH_TCO_STS 4
+#define B_PCH_TCO_STS_SECOND_TO BIT17 // Second Timeout Status
+#define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout
+#define N_PCH_TCO_STS_TIMEOUT 3
+
+#define R_PCH_TCO_CNT 0x68 // TCO Control
+#define S_PCH_TCO_CNT 2
+#define B_PCH_TCO_CNT_OS_POLICY (BIT21 | BIT20) // OS Policy
+#define B_PCH_TCO_CNT_LOCK BIT12 // TCO Enable Lock
+#define B_PCH_TCO_CNT_TMR_HLT BIT11 // TCO Timer Halt
+
+#define R_PCH_TCO_TMR 0x70 // TCO Timer
+#define B_PCH_TCO_TMR_TCO_TRLD 0x3FF0000
+
+//
+// PMC Memory Space Registers (PBASE)
+//
+#define R_PCH_PMC_PRSTS 0x00 // Power and Reset Status
+#define B_PCH_PMC_PRSTS_PRODID 0xFF000000 // Power Management Controller Product ID
+#define B_PCH_PMC_PRSTS_REVID 0x00FF0000 // Power Management Controller Revision ID
+#define B_PCH_PMC_PRSTS_PM_WD_TMR BIT15 // PMC Watchdog Timer Status
+#define B_PCH_PMC_PRSTS_CODE_COPIED_STS BIT11 // Patch Copied Over Status
+#define B_PCH_PMC_PRSTS_CODE_LOAD_TO BIT9 // Patch Load Timeout Status
+#define B_PCH_PMC_PRSTS_OP_STS BIT8 // PMC Operational Status
+#define B_PCH_PMC_PRSTS_SEC_GBLRST_STS BIT7 // SEC Global Reset Status
+#define B_PCH_PMC_PRSTS_SEC_WD_TMR_STS BIT6 // SEC Watchdog Timer Status
+#define B_PCH_PMC_PRSTS_WOL_OVR_WK_STS BIT5 // Wake On LAN Override Wake Status
+#define B_PCH_PMC_PRSTS_HOST_WAKE_STS BIT4 // PMC Host Wake Status
+
+#define R_PCH_PMC_PM_CFG 0x08 // Power Management Configuration
+#define B_PCH_PMC_PM_CFG_SPS BIT5 // Shutdown Policy Select
+#define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap
+#define B_PCH_PMC_PM_CFG_SX_ENT_TO_EN BIT3 // S1 / 3 / 4 / 5 Entry Timeout Enable
+#define B_PCH_PMC_PM_CFG_TIMING_T581 (BIT1 | BIT0) // Timing t581
+
+#define R_PCH_PMC_PM_STS 0x0C // Power Management Status
+#define B_PCH_PMC_PM_STS_PMC_MSG_FULL BIT24 // PMC Message Full Status
+#define B_PCH_PMC_PM_STS_PMC_MSG_4_FULL BIT23 // PMC 4 Message Full Status
+#define B_PCH_PMC_PM_STS_PMC_MSG_3_FULL BIT22 // PMC 3 Message Full Status
+#define B_PCH_PMC_PM_STS_PMC_MSG_2_FULL BIT21 // PMC 2 Message Full Status
+#define B_PCH_PMC_PM_STS_PMC_MSG_1_FULL BIT20 // PMC 1 Message Full Status
+#define B_PCH_PMC_PM_STS_CODE_REQ BIT8 // Patch Request Status
+#define B_PCH_PMC_PM_STS_HPR_ENT_TO BIT2 // Host partition Reset Entry Timeout Status
+#define B_PCH_PMC_PM_STS_SX_ENT_TO BIT1 // S3 / 4 / 5 Entry Timeout Status
+
+#define R_PCH_PMC_MTPMC 0x10 // Message to PMC
+
+#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1
+#define B_PCH_PMC_GEN_PMCON_UART_EN BIT24 // UART Debug Port Enable
+#define B_PCH_PMC_GEN_PMCON_DRAM_INIT BIT23 // DRAM Initialization Scratchpad Bit
+#define B_PCH_PMC_GEN_PMCON_MEM_SR BIT21 // Memory Placed in Self-Refresh
+#define B_PCH_PMC_GEN_PMCON_SRS BIT20 // System Reset Status
+#define B_PCH_PMC_GEN_PMCON_CTS BIT19 // CPU Thermal Trip Status
+#define B_PCH_PMC_GEN_PMCON_MIN_SLP_S4 BIT18 // Minimum SLP_S4# Assertion Width Violation Status
+#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure
+#define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable
+#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure
+#define B_PCH_PMC_GEN_PMCON_WOL_ENABLE_OVERRIDE BIT13 // WOL Enable Override
+#define B_PCH_PMC_GEN_PMCON_DISABLE_SX_STRETCH BIT12 // Disable SLP_X Scretching After SUS Well Power Up
+#define B_PCH_PMC_GEN_PMCON_SLP_S3_MAW (BIT11 | BIT10) // SLP_S3# Minimum Assertion Width
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_60US 0x000 // 60 micro seconds
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_1MS 0x400 // 1 milli second
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_50MS 0x800 // 50 milli seconds
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_2S 0xC00 // 2 seconds
+#define B_PCH_PMC_GEN_PMCON_GEN_RST_STS BIT9 // General Reset Status
+#define B_PCH_PMC_GEN_PMCON_RTC_RESERVED BIT8 // RTC Reserved
+#define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) // SWSMI Rate Select
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_64MS 0xC0 // 64ms +/- 4ms
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_32MS 0x80 // 32ms +/- 4ms
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_16MS 0x40 // 16ms +/- 4ms
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_1_5MS 0x00 // 1.5ms +/- 0.6ms
+#define B_PCH_PMC_GEN_PMCON_SLP_S4_MAW (BIT5 | BIT4) // SLP_S4# Minimum Assertion Width
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_1S 0x30 // 1 second
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_2S 0x20 // 2 seconds
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_3S 0x10 // 3 seconds
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S 0x00 // 4 seconds
+#define B_PCH_PMC_GEN_PMCON_SLP_S4_ASE BIT3 // SLP_S4# Assertion Scretch Enable
+#define B_PCH_PMC_GEN_PMCON_RTC_PWR_STS BIT2 // RTC Power Status
+#define B_PCH_PMC_GEN_PMCON_AFTERG3_EN BIT0 // After G3 State Enable
+
+#define R_PCH_PMC_GEN_PMCON_2 0x24 // General PM Configuration 2
+#define B_PCH_PMC_GEN_PMCON_LOCK_S4_STRET_LD BIT18 // SLP_S3 / SLP_S4 Stretching Policy Lock-Down
+#define B_PCH_PMC_GEN_PMCON_BIOS_PCI_EXP_EN BIT10 // BIOS PCI Express Enable
+#define B_PCH_PMC_GEN_PMCON_PWRBTN_LVL BIT9 // Power Button Level
+#define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock
+#define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) // Period SMI Select
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_64S 0x0000 // 64 seconds
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_32S 0x0001 // 32 seconds
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_16S 0x0002 // 16 seconds
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_8S 0x0003 // 8 seconds
+
+#define R_PCH_PMC_MFPMC 0x28 // Message from PMC
+
+#define R_PCH_PMC_SEC_STS 0x2C // SEC Status
+#define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause
+
+#define R_PCH_PMC_CRID 0x30 // Configured Revision ID
+#define B_PCH_PMC_CRID_RID_SEL (BIT1 | BIT0) // Revision ID Select
+
+#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7 BIT31 // LPSS2 I2C #7
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 BIT30 // LPSS2 I2C #6
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5 BIT29 // LPSS2 I2C #5
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 BIT28 // LPSS2 I2C #4
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 BIT27 // LPSS2 I2C #3
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2 BIT26 // LPSS2 I2C #2
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 BIT25 // LPSS2 I2C #1
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC0 BIT24 // LPSS2 DMA Disable
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC3 BIT23 // PCI Express Function 3 Disable
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC2 BIT22 // PCI Express Function 2 Disable
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC1 BIT21 // PCI Express Function 1 Disable
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 BIT20 // PCI Express Function 0 Disable
+#define N_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 20
+#define B_PCH_PMC_FUNC_DIS_SEC BIT19 // SEC Disable
+#define B_PCH_PMC_FUNC_DIS_USH BIT18 // USH Disable
+#define B_PCH_PMC_FUNC_DIS_SATA BIT17 // SATA Disable
+#define B_PCH_PMC_FUNC_DIS_UFS BIT15 // UFS Disable
+#define B_PCH_PMC_FUNC_DIS_OTG BIT14 // USB OTG Disable
+#define B_PCH_PMC_FUNC_DIS_LPE BIT13 // LPE Disable
+#define B_PCH_PMC_FUNC_DIS_AZALIA BIT12 // Azalia Disable
+#define B_PCH_PMC_FUNC_DIS_SDIO3 BIT10 // SCC SDIO #3 (Device 18, SD Card) Disable
+#define B_PCH_PMC_FUNC_DIS_SDIO2 BIT9 // SCC SDIO #2 (Device 17, SDIO) Disable
+#define B_PCH_PMC_FUNC_DIS_SDIO1 BIT8 // SCC SDIO #1 (Device 16, eMMC) Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC7 BIT7 // LPSS1 SPI #3 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC6 BIT6 // LPSS1 SPI #2 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC5 BIT5 // LPSS1 SPI #1 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC4 BIT4 // LPSS1 HS-UART #2 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC3 BIT3 // LPSS1 HS-UART #1 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC2 BIT2 // LPSS1 PWM #2 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC1 BIT1 // LPSS1 PWM #1 Disable
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC0 BIT0 // LPSS1 DMA Disable
+
+#define R_PCH_PMC_FUNC_DIS2 0x38 // Function Disable 2 Register
+#define B_PCH_PMC_FUNC_DIS2_DIS_DONE BIT31 // Function Disable Done (B0 stepping and onwards)
+#define B_PCH_PMC_FUNC_DIS2_ISH BIT4 // ISH Disable
+#define B_PCH_PMC_FUNC_DIS2_GMM BIT3 // GMM Disable
+#define B_PCH_PMC_FUNC_DIS2_USH_SS_PHY BIT2 // USH Super Speed PHY Disable
+#define B_PCH_PMC_FUNC_DIS2_OTG_SS_PHY BIT1 // OTG Super Speed PHY Disable
+#define B_PCH_PMC_FUNC_DIS2_SMBUS BIT0 // SMBus Disable
+#define R_PCH_PMC_S0IX_WAKE_EN 0x3C // S0ix Wake Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_ALLDEV 0xFFFFFF // S0ix Wake Enable All Devices
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_SE BIT23 // GPIO SouthEast Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_ISH_PMC BIT22 // ISH PMC Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_ISH_PMC_IPC BIT21 // ISH PMC IPC Pop Up Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_N BIT20 // GPIO North IRQ Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_SW_IOAPIC BIT19 // GPIO SouthWest IOxAPIC Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_N_IOAPIC BIT18 // GPIO North IOxAPIC Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_LAN_B BIT17 // LAN_B Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_ILB_NMI BIT16 // iLB NMI Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_SCI_REQ BIT15 // SCI Request Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_SMI_PENDING BIT14 // SMI Pending Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_UXD_PCU BIT13 // UXD PCU Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_AOT_S0I3 BIT12 // AOT S0i3 Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_AOT_S0I2 BIT11 // AOT S0i2 Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_AOT_S0I1 BIT10 // AOT S0i1 Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_IOXAPIC BIT9 // IOxAPIC Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_E BIT8 // GPIO East Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_N_GPE BIT7 // GPIO North GPE Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_SW_GPE BIT6 // GPIO SouthWest Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_GPIO_SE_GPE BIT5 // GPIO SouthEast Wake Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_LPC_CLKRUNB BIT4 // LPC CLKRUNB Wake Pop Up Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_SEC_TIMER BIT3 // SeC Timer Wake Pop Up Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_LPE_PMC_IPC BIT2 // LPE PMC IPC Pop Up Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_LPE_PMC BIT1 // LPE PMC Wake Pop Up Event Enable
+#define B_PCH_PMC_S0IX_WAKE_EN_NFC BIT0 // NFC Wake Pop Up Event Enable
+
+#define R_PCH_PMC_S0IX_WAKE_STS 0x40 // S0ix Wake Status
+#define B_PCH_PMC_S0IX_WAKE_STS_ALLDEV 0xFFFFFF // S0ix Wake Status All Devices
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_SE BIT23 // GPIO SouthEast Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_ISH_PMC BIT22 // ISH PMC Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_ISH_PMC_IPC BIT21 // ISH PMC IPC Pop Up Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_N BIT20 // GPIO North IRQ Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_SW_IOAPIC BIT19 // GPIO SouthWest IOxAPIC Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_N_IOAPIC BIT18 // GPIO North IOxAPIC Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_LAN_B BIT17 // LAN_B Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_ILB_NMI BIT16 // iLB NMI Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_SCI_REQ BIT15 // SCI Request Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_SMI_PENDING BIT14 // SMI Pending Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_UXD_PCU BIT13 // UXD PCU Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_AOT_S0I3 BIT12 // AOT S0i3 Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_AOT_S0I2 BIT11 // AOT S0i2 Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_AOT_S0I1 BIT10 // AOT S0i1 Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_IOXAPIC BIT9 // IOxAPIC Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_E BIT8 // GPIO East Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_N_GPE BIT7 // GPIO North GPE Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_SW_GPE BIT6 // GPIO SouthWest Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_GPIO_SE_GPE BIT5 // GPIO SouthEast Wake Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_LPC_CLKRUNB BIT4 // LPC CLKRUNB Wake Pop Up Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_SEC_TIMER BIT3 // SeC Timer Wake Pop Up Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_LPE_PMC_IPC BIT2 // LPE PMC IPC Pop Up Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_LPE_PMC BIT1 // LPE PMC Wake Pop Up Event Status
+#define B_PCH_PMC_S0IX_WAKE_STS_NFC BIT0 // NFC Wake Pop Up Event Status
+
+#define R_PCH_PMC_S0IX_CTL 0x44 // S0ix Control
+#define B_PCH_PMC_S0IX_CTL_S0IX_RR 0xFF // S0ix Rail Ramp Time
+#define B_PCH_PMC_S0IX_CTL_S0IX_RR_MS BIT7 // Ramp Time in Millisecond, Each Tick is 1ms
+#define B_PCH_PMC_S0IX_CTL_S0IX_RR_US 0 // Ramp Time in Microsecond, Each Tick is 2us
+
+#define R_PCH_PMC_PMIR 0x48 // Extended Test Mode Register (ETR)
+#define B_PCH_PMC_PMIR_CF9LOCK BIT31 // CF9h Lockdown
+#define B_PCH_PMC_PMIR_LTR_DEF BIT22 // LTR Default
+#define B_PCH_PMC_PMIR_IGNORE_HPET BIT21 // Ignore HPET Disable Check Before Going to S0i2
+#define B_PCH_PMC_PMIR_CF9GR BIT20 // CF9h Global Reset
+#define B_PCH_PMC_PMIR_CWORWRE BIT18 // CF9h Without Resume Well Reset Enable
+#define B_PCH_PMC_PMIR_MAX_S0IX (BIT17 | BIT16) // Max S0ix State SoC Can Go
+
+#define R_PCH_PMC_VLT 0x50 // Voltage Detect Register
+#define B_PCH_PMC_VLT_FUSES 0xFF // Voltage Detect Fuses
+
+#define R_PCH_PMC_S0IA_TMR_UPPER 0x54 // S0I Ready Residency Timer
+
+#define R_PCH_PMC_GPI_ROUT 0x58 // GPI Rout
+#define B_PCH_PMC_GPI_ROUT_0 (BIT1 | BIT0)
+#define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2)
+#define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4)
+#define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
+#define B_PCH_PMC_GPI_ROUT_4 (BIT9 | BIT8)
+#define B_PCH_PMC_GPI_ROUT_5 (BIT11 | BIT10)
+#define B_PCH_PMC_GPI_ROUT_6 (BIT13 | BIT12)
+#define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14)
+#define B_PCH_PMC_GPI_ROUT_8 (BIT17 | BIT16)
+#define B_PCH_PMC_GPI_ROUT_9 (BIT19 | BIT18)
+#define B_PCH_PMC_GPI_ROUT_10 (BIT21 | BIT20)
+#define B_PCH_PMC_GPI_ROUT_11 (BIT23 | BIT22)
+#define B_PCH_PMC_GPI_ROUT_12 (BIT25 | BIT24)
+#define B_PCH_PMC_GPI_ROUT_13 (BIT27 | BIT26)
+#define B_PCH_PMC_GPI_ROUT_14 (BIT29 | BIT28)
+#define B_PCH_PMC_GPI_ROUT_15 (BIT31 | BIT30)
+
+#define R_PCH_PMC_S0IA_TMR 0x5C // S0I Ready Residency Timer
+
+#define R_PCH_PMC_PCC0 0x60 // Platform Clock Control 0
+#define R_PCH_PMC_PCC1 0x64 // Platform Clock Control 1
+#define R_PCH_PMC_PCC2 0x68 // Platform Clock Control 2
+#define R_PCH_PMC_PCC3 0x6C // Platform Clock Control 3
+#define R_PCH_PMC_PCC4 0x70 // Platform Clock Control 4
+#define R_PCH_PMC_PCC5 0x74 // Platform Clock Control 5
+#define B_PCH_PMC_PCCX_CLK_FREQ BIT2 // Clock Frequency
+#define V_PCH_PMC_PCCX_CLK_FREQ_19P2MHZ_PLL BIT2 // 19.2 MHz (LPPLL Driven)
+#define V_PCH_PMC_PCCX_CLK_FREQ_19P2MHZ_XTAL 0 // 19.2 MHz (XTAL Driven)
+#define B_PCH_PMC_PCCX_CLK_CTL (BIT1 | BIT0) // Clock Control
+#define V_PCH_PMC_PCCX_CLK_CTL_FORCE_OFF BIT1 // Force Off
+#define V_PCH_PMC_PCCX_CLK_CTL_FORCE_ON BIT0 // Force On
+#define V_PCH_PMC_PCCX_CLK_CTL_D3_GATED 0 // Gated on D3
+
+#define R_PCH_PMC_S0IR_TMR_UPPER 0x78 // S0I Ready Residency Upper Timer
+#define B_PCH_PMC_S0IR_TMR_UPPER_RTIME 0xFF // Time Spent in S0I Ready State
+
+#define R_PCH_PMC_S0I1_TMR_UPPER 0x7C // S0I1 Ready Residency Timer
+
+#define R_PCH_PMC_S0IR_TMR 0x80 // S0I Ready Residency Timer
+#define B_PCH_PMC_S0IR_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I Ready State
+
+#define R_PCH_PMC_S0I1_TMR 0x84 // S0I1 Ready Residency Timer
+#define B_PCH_PMC_S0I1_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I1 Ready State
+
+#define R_PCH_PMC_S0I2_TMR 0x88 // S0I2 Ready Residency Timer
+#define B_PCH_PMC_S0I2_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I2 Ready State
+
+#define R_PCH_PMC_S0I3_TMR 0x8C // S0I3 Ready Residency Timer
+#define B_PCH_PMC_S0I3_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I3 Ready State
+
+#define R_PCH_PMC_S0_TMR 0x90 // S0 Residency Timer
+#define B_PCH_PMC_S0_TMR_RTIME 0xFFFFFFFF // Time Spent in S0 State
+
+#define R_PCH_PMC_S0I2_TMR_UPPER 0x94 // S0I2 Residency Upper Timer
+#define B_PCH_PMC_S0I2_TMR_UPPER_RTIME 0xFF // Time Spent in S0I2 Ready State
+
+#define R_PCH_PMC_PSS 0x98 // Power Island Power Status
+#define B_PCH_PMC_PSS_PG_STS_DFX_ALL 0xFC000000 // All DFX
+#define B_PCH_PMC_PSS_PG_STS_ISH BIT18 // ISH
+#define B_PCH_PMC_PSS_PG_STS_USB BIT16 // USB
+#define B_PCH_PMC_PSS_PG_STS_OTG_UXE BIT15 // OTG UX Engine
+#define B_PCH_PMC_PSS_PG_STS_OTG_UXD_FD_SX BIT12 // OTG UXD FD SX
+#define B_PCH_PMC_PSS_PG_STS_OTG_UXD BIT11 // OTG UXD
+#define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio
+#define B_PCH_PMC_PSS_PG_STS_LPSS BIT5 // LPSS
+#define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe
+#define B_PCH_PMC_PSS_PG_STS_SEC BIT3 // SeC
+#define B_PCH_PMC_PSS_PG_STS_HDA BIT2 // HDA
+#define B_PCH_PMC_PSS_PG_STS_SATA BIT1 // SATA
+
+#define R_PCH_PMC_S0I3_TMR_UPPER 0x9C // S0I3 Ready Residency Upper Timer
+#define B_PCH_PMC_S0I3_TMR_UPPER_RTIME 0xFF // Time Spent in S0I3 State
+
+#define R_PCH_PMC_D3_STS_0 0xA0 // D3 Status 0
+#define B_PCH_PMC_D3_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7
+#define B_PCH_PMC_D3_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6
+#define B_PCH_PMC_D3_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5
+#define B_PCH_PMC_D3_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4
+#define B_PCH_PMC_D3_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3
+#define B_PCH_PMC_D3_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2
+#define B_PCH_PMC_D3_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1
+#define B_PCH_PMC_D3_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0
+#define B_PCH_PMC_D3_STS_0_PCIEF3 BIT23 // PCIe Function 3
+#define B_PCH_PMC_D3_STS_0_PCIEF2 BIT22 // PCIe Function 2
+#define B_PCH_PMC_D3_STS_0_PCIEF1 BIT21 // PCIe Function 1
+#define B_PCH_PMC_D3_STS_0_PCIEF0 BIT20 // PCIe Function 0
+#define B_PCH_PMC_D3_STS_0_SEC BIT19 // SeC
+#define B_PCH_PMC_D3_STS_0_USH BIT18 // USH
+#define B_PCH_PMC_D3_STS_0_SATA BIT17 // SATA
+#define B_PCH_PMC_D3_STS_0_OTG BIT14 // OTG
+#define B_PCH_PMC_D3_STS_0_LPE BIT13 // LPE
+#define B_PCH_PMC_D3_STS_0_HDA BIT12 // HDA
+#define B_PCH_PMC_D3_STS_0_SCCF2 BIT10 // SCC Function 2
+#define B_PCH_PMC_D3_STS_0_SCCF1 BIT9 // SCC Function 1
+#define B_PCH_PMC_D3_STS_0_SCCF0 BIT8 // SCC Function 0
+#define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
+#define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
+#define B_PCH_PMC_D3_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5
+#define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
+#define B_PCH_PMC_D3_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3
+#define B_PCH_PMC_D3_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2
+#define B_PCH_PMC_D3_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1
+#define B_PCH_PMC_D3_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0
+
+#define R_PCH_PMC_D3_STS_1 0xA4 // D3 Status 1
+#define B_PCH_PMC_D3_STS_1_ISH BIT2 // ISH
+#define B_PCH_PMC_D3_STS_1_SMB BIT0 // SMBus
+#define R_PCH_PMC_D3_STDBY_STS_0 0xA8 // D3 Standby Status 0
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF3 BIT23 // PCIe Function 3
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF2 BIT22 // PCIe Function 2
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF1 BIT21 // PCIe Function 1
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF0 BIT20 // PCIe Function 0
+#define B_PCH_PMC_D3_STDBY_STS_0_SEC BIT19 // SeC
+#define B_PCH_PMC_D3_STDBY_STS_0_USH BIT18 // USH
+#define B_PCH_PMC_D3_STDBY_STS_0_SATA BIT17 // SATA
+#define B_PCH_PMC_D3_STDBY_STS_0_OTG BIT14 // OTG
+#define B_PCH_PMC_D3_STDBY_STS_0_LPE BIT13 // LPE
+#define B_PCH_PMC_D3_STDBY_STS_0_HDA BIT12 // HDA
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF2 BIT10 // SCC Function 2
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF1 BIT9 // SCC Function 1
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF0 BIT8 // SCC Function 0
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0
+
+#define R_PCH_PMC_D3_STDBY_STS_1 0xAC // D3 Standby Status 1
+#define B_PCH_PMC_D3_STDBY_STS_1_ISH BIT2 // ISH
+#define B_PCH_PMC_D3_STDBY_STS_1_SMB BIT0 // SMBus
+
+#define R_PCH_PMC_MTPMC1 0xB0 // Message to PMC 1
+
+#define R_PCH_PMC_MTPMC2 0xB4 // Message to PMC 2
+
+#define R_PCH_PMC_MTPMC3 0xB8 // Message to PMC 3
+
+#define R_PCH_PMC_MTPMC4 0xBC // Message to PMC 4
+
+#define R_PCH_PMC_PME_STS 0xC0 // PME Status 0
+
+#define R_PCH_PMC_GPE_LEVEL_EDGE 0xC4 // GPE Level Edge Mode
+
+#define R_PCH_PMC_GPE_POLARITY 0xC8 // GPE Polarity Mode
+
+#define R_PCH_PMC_LOCK 0xCC // Lock Register
+#define B_PCH_PMC_LOCK_SX_WAKE BIT6
+#define B_PCH_PMC_LOCK_PCIE BIT5
+#define B_PCH_PMC_LOCK_PER_SMI BIT4
+#define B_PCH_PMC_LOCK_FUNC_DIS BIT3
+#define B_PCH_PMC_LOCK_S0IX BIT2
+#define B_PCH_PMC_LOCK_GPIO_ROUT BIT1
+#define B_PCH_PMC_LOCK_PLT_CLK BIT0
+
+#define R_PCH_PMC_PCIE_LTR 0xD0 // PCIE LTR
+
+#define R_PCH_PMC_D3_COLD 0xD4 // D3 Cold
+
+#define R_PCH_PMC_D3_DEFER_0 0xE0 // D3 Defer for PMC FW
+
+#define R_PCH_PMC_D3_DEFER_1 0xE4 // D3 Defer for PMC FW
+
+#define R_PCH_PMC_BIOS_COMM 0xEC // BIOS Communication from PMC
+#define B_PCH_PMC_BIOS_COMM_PMC_FW_UIP BIT31 // PMC Firmware Update In Progress
+#define B_PCH_PMC_BIOS_COMM_BIOS_UPD_REQ BIT15 // BIOS Update Request
+#define B_PCH_PMC_BIOS_COMM_PMU_WAKE_B_DISABLE BIT5 // Disable PMU_WAKE_B
+#define B_PCH_PMC_BIOS_COMM_ISP_PSF0_FD BIT4 // ISP PSF0 Function Disable
+#define B_PCH_PMC_BIOS_COMM_LPE_OSC_FORCE_ON BIT3 // LPE OSC Force On Enable
+#define B_PCH_PMC_BIOS_COMM_SP_PWR_LANE_REQ BIT1 // SSIC PHY Common Power Lane Request Change
+#define B_PCH_PMC_BIOS_COMM_GPIO_RCOMP BIT0 // GPIO RCOMP
+#define B_PCH_PMC_BIOS_COMM_USB2_CPR_POLL_DISABLE BIT7 // iPeak disable
+
+#define R_PCH_PMC_VUART3 0xF8 // Virtual UART 3
+
+//
+// CFIO Register Offsets from IOBASE
+//
+#define R_PCH_CFIO_SOUTHWEST 0x00000 // South West CFIO Base
+#define R_PCH_CFIO_NORTH 0x08000 // North CFIO Base
+#define R_PCH_CFIO_EAST 0x10000 // East CFIO Base
+#define R_PCH_CFIO_SOUTHEAST 0x18000 // South East CFIO Base
+#define R_PCH_CFIO_VIRTUAL 0x20000 // Virtual CFIO Base
+
+#define R_PCH_CFIO_PAD_CONF0 0x00 // CFIO PAD_CONF0
+#define R_PCH_CFIO_PAD_CONF1 0x04 // CFIO PAD_CONF1
+
+#define R_PCH_CFIO_PAD_CTRL0 0x04400 // Pad Control Register 0 Base
+#define B_PCH_CFIO_PAD_CTRL0_INTSEL (BIT31 | BIT30 | BIT29 | BIT28) // Interrupt Select
+#define N_PCH_CFIO_PAD_CTRL0_INTSEL 28
+#define B_PCH_CFIO_PAD_CTRL0_GFCFG (BIT27 | BIT26) // Glitch Filter Config
+#define V_PCH_CFIO_PAD_CTRL0_GFCFG_EDGE_RX (BIT27 | BIT26) // Enable for Edge Detect and RX Data
+#define V_PCH_CFIO_PAD_CTRL0_GFCFG_RX BIT27 // Enable for RX Data Only
+#define V_PCH_CFIO_PAD_CTRL0_GFCFG_EDGE BIT26 // Enable for Edge Detect Only
+#define V_PCH_CFIO_PAD_CTRL0_GFCFG_DIS 0 // Disable (Bypass the Glitch Filter)
+#define B_PCH_CFIO_PAD_CTRL0_RXTXENCFG (BIT25 | BIT24) // RX / TX Enable Config (When GPIO Mode Disabled)
+#define B_PCH_CFIO_PAD_CTRL0_TERM (BIT23 | BIT22 | BIT21 | BIT20) // Termination
+#define V_PCH_CFIO_PAD_CTRL0_TERM_PULLUP BIT23 // Pull Up
+#define V_PCH_CFIO_PAD_CTRL0_TERM_PULLDOWN 0 // Pull Down
+#define V_PCH_CFIO_PAD_CTRL0_TERM_1K_PU BIT22 // 1K Pull Up Only
+#define V_PCH_CFIO_PAD_CTRL0_TERM_5K BIT21 // 5K
+#define V_PCH_CFIO_PAD_CTRL0_TERM_20K BIT20 // 20K
+#define B_PCH_CFIO_PAD_CTRL0_PMODE (BIT19 | BIT18 | BIT17 | BIT16) // Pad Mode
+#define N_PCH_CFIO_PAD_CTRL0_PMODE 16
+#define B_PCH_CFIO_PAD_CTRL0_GPIOEN BIT15 // GPIO Enable
+#define B_PCH_CFIO_PAD_CTRL0_GPIOCFG (BIT10 | BIT9 | BIT8) // GPIO Config
+#define V_PCH_CFIO_PAD_CTRL0_GPIOCFG_HIZ (BIT9 | BIT8) // Hi-Z (TX Disabled and RX Disabled)
+#define V_PCH_CFIO_PAD_CTRL0_GPIOCFG_GPI BIT9 // GPI (TX Disabled and RX Enabled)
+#define V_PCH_CFIO_PAD_CTRL0_GPIOCFG_GPO BIT8 // GPO (TX Enabled and RX Disabled)
+#define V_PCH_CFIO_PAD_CTRL0_GPIOCFG_GPIO 0 // GPIO (TX Enabled and RX Enabled)
+#define B_PCH_CFIO_PAD_CTRL0_GPIOLIGHT BIT7 // GPIO Light (Applies to SouthEast and SouthWest GPIOs only)
+#define B_PCH_CFIO_PAD_CTRL0_GPIOTXSTATE BIT1 // GPIO TX State
+#define B_PCH_CFIO_PAD_CTRL0_GPIORXSTATE BIT0 // GPIO RX State (Current State of the PAD)
+
+#define R_PCH_CFIO_PAD_CTRL1 0x04404 // Pad Control Register 1 Base
+#define B_PCH_CFIO_PAD_CTRL1_CFGLOCK BIT31 // Configuration Lock
+#define B_PCH_CFIO_PAD_CTRL1_PADRSTCFG BIT30 // Pad Reset Config
+#define B_PCH_CFIO_PAD_CTRL1_CFIOPADCFG 0x3FFF0000 // CFIO Pad Configuration
+#define B_PCH_CFIO_PAD_CTRL1_IOSSTATE (BIT15 | BIT14 | BIT13 | BIT12) // IO Standby State
+#define B_PCH_CFIO_PAD_CTRL1_IOSTERM (BIT11 | BIT10) // IO Standby Termination
+#define B_PCH_CFIO_PAD_CTRL1_INVRXTX (BIT7 | BIT6 | BIT5 | BIT4) // Invert RX TX
+#define V_PCH_CFIO_PAD_CTRL1_INVRXTX_TXDATA BIT7 // TX Data
+#define V_PCH_CFIO_PAD_CTRL1_INVRXTX_RXDATA BIT6 // RX Data
+#define V_PCH_CFIO_PAD_CTRL1_INVRXTX_TXEN BIT5 // TX Enable
+#define V_PCH_CFIO_PAD_CTRL1_INVRXTX_RXEN BIT4 // RX Enable
+#define B_PCH_CFIO_PAD_CTRL1_ODEN BIT3 // Open Drain Enable
+#define B_PCH_CFIO_PAD_CTRL1_INTWAKECFG (BIT2 | BIT1 | BIT0) // Interrupt and Wake Configuration
+#define V_PCH_CFIO_PAD_CTRL1_INTWAKECFG_LEVEL BIT2 // Level Interrupt/Wake
+#define V_PCH_CFIO_PAD_CTRL1_INTWAKECFG_FALL_RISE (BIT1 | BIT0) // Falling or Rising Edge Detect Interrupt/Wake
+#define V_PCH_CFIO_PAD_CTRL1_INTWAKECFG_RISE BIT1 // Rising Edge Detect Interrupt/Wake
+#define V_PCH_CFIO_PAD_CTRL1_INTWAKECFG_FALL BIT0 // Falling Edge Detect Interrupt/Wake
+#define V_PCH_CFIO_PAD_CTRL1_INTWAKECFG_DIS 0 // Interrupt/Wake Disable
+
+//
+// Fixed IO Space
+//
+
+//
+// Processor Interface Registers
+//
+#define R_PCH_NMI_SC 0x61 // NMI Status and Control
+#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status
+#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status
+#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 // Timer Counter 2 Status
+#define B_PCH_NMI_SC_REF_TOGGLE BIT4 // Refresh Cycle toggle Status
+#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 // IOCHK NMI Enable
+#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 // SERR# NMI Enable
+#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 // Speaker Data Enable
+#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 // Timer Counter 2 Enable
+
+#define R_PCH_NMI_EN 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_RTC_INDEX
+#define B_PCH_NMI_EN_NMI_EN BIT7 // NMI Enable, must preserve this bit first before writing to IO port 0x70
+
+//
+// RTC Registers
+//
+#define R_PCH_RTC_INDEX 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_NMI_EN
+#define R_PCH_RTC_TARGET 0x71 // Real-Time Clock Target Register
+#define R_PCH_RTC_EXT_INDEX 0x72 // Extended RAM Index Register
+#define R_PCH_RTC_EXT_TARGET 0x73 // Extended RAM Target Register
+#define R_PCH_RTC_INDEX2 0x74 // Real-Time Clock Index Register
+#define R_PCH_RTC_TARGET2 0x75 // Real-Time Clock Target Register
+#define R_PCH_RTC_EXT_INDEX2 0x76 // Extended RAM Index Register
+#define R_PCH_RTC_EXT_TARGET2 0x77 // Extended RAM Target Register
+
+#define R_PCH_RTC_SECONDS 0x00 // Seconds, Range 0..59
+#define R_PCH_RTC_SECONDSALARM 0x01 // Seconds Alarm, Range 0..59
+#define R_PCH_RTC_MINUTES 0x02 // Minutes, Range 0..59
+#define R_PCH_RTC_MINUTESALARM 0x03 // Minutes Alarm, Range 0..59
+#define R_PCH_RTC_HOURS 0x04 // Hours, Range 1..12 or 0..23 Bit 7 is AM/PM
+#define R_PCH_RTC_HOURSALARM 0x05 // Hours Alarm, Range 1..12 or 0..23 Bit 7 is AM/PM
+#define R_PCH_RTC_DAYOFWEEK 0x06 // Day of Week, Range 1..7
+#define R_PCH_RTC_DAYOFMONTH 0x07 // Day of Month, Range 1..31
+#define R_PCH_RTC_MONTH 0x08 // Month, Range 1..12
+#define R_PCH_RTC_YEAR 0x09 // Year, Range 0..99
+
+#define R_PCH_RTC_REGISTERA 0x0A // RTC Register A
+#define B_PCH_RTC_REGISTERA_UIP BIT7 // Update In Progress
+#define B_PCH_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) // Division Chain Select
+#define V_PCH_RTC_REGISTERA_DV_NORM_OP 0x20 // Normal Operation
+#define V_PCH_RTC_REGISTERA_DV_BYP_5 0x30 // Bypass 5 Stages (Test mode only)
+#define V_PCH_RTC_REGISTERA_DV_BYP_10 0x40 // Bypass 10 Stages (Test mode only)
+#define V_PCH_RTC_REGISTERA_DV_BYP_15 0x50 // Bypass 15 Stages (Test mode only)
+#define V_PCH_RTC_REGISTERA_DV_DIV_RST1 0x60 // Divider Reset
+#define V_PCH_RTC_REGISTERA_DV_DIV_RST2 0x70 // Divider Reset
+#define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select
+#define V_PCH_RTC_REGISTERA_RS_INT_NV_TGL 0x00 // Interrupt Never Toggles
+#define V_PCH_RTC_REGISTERA_RS_3P906MS1 0x01 // 3.90625 ms
+#define V_PCH_RTC_REGISTERA_RS_7P812MS1 0x02 // 7.8125 ms
+#define V_PCH_RTC_REGISTERA_RS_122P0US 0x03 // 122.070 us
+#define V_PCH_RTC_REGISTERA_RS_244P1US 0x04 // 244.141 us
+#define V_PCH_RTC_REGISTERA_RS_488P2US 0x05 // 488.281 us
+#define V_PCH_RTC_REGISTERA_RS_976P5US 0x06 // 976.5625 us
+#define V_PCH_RTC_REGISTERA_RS_1P953MS 0x07 // 1.953125 ms
+#define V_PCH_RTC_REGISTERA_RS_3P906MS 0x08 // 3.90625 ms
+#define V_PCH_RTC_REGISTERA_RS_7P812MS 0x09 // 7.8125 ms
+#define V_PCH_RTC_REGISTERA_RS_15P62MS 0x0A // 15.625 ms
+#define V_PCH_RTC_REGISTERA_RS_31P25MS 0x0B // 31.25 ms
+#define V_PCH_RTC_REGISTERA_RS_62P5MS 0x0C // 62.5 ms
+#define V_PCH_RTC_REGISTERA_RS_125MS 0x0D // 125 ms
+#define V_PCH_RTC_REGISTERA_RS_250MS 0x0E // 250 ms
+#define V_PCH_RTC_REGISTERA_RS_500MS 0x0F // 500 ms
+
+#define R_PCH_RTC_REGISTERB 0x0B // RTC Register B
+#define B_PCH_RTC_REGISTERB_SET BIT7 // Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs
+#define B_PCH_RTC_REGISTERB_PIE BIT6 // Periodic Interrupt Enable
+#define B_PCH_RTC_REGISTERB_AIE BIT5 // Alarm Interrupt Enable
+#define B_PCH_RTC_REGISTERB_UIE BIT4 // Update-ended Interrupt Enable
+#define B_PCH_RTC_REGISTERB_SQWE BIT3 // Square Wave Enable (Not implemented)
+#define B_PCH_RTC_REGISTERB_DM BIT2 // Data Mode 1: Binary; 0:BCD
+#define B_PCH_RTC_REGISTERB_HF BIT1 // Hour Format 1: 24 mode; 0: 12 mode.
+#define B_PCH_RTC_REGISTERB_DSE BIT0 // Daylight Savings Enable (Not Implemented)
+
+#define R_PCH_RTC_REGISTERC 0x0C // RTC Register C
+#define B_PCH_RTC_REGISTERC_IRQF BIT7 // Interrupt Request Flag
+#define B_PCH_RTC_REGISTERC_PF BIT6 // Periodic Interrupt Flag
+#define B_PCH_RTC_REGISTERC_AF BIT5 // Alarm Flag
+#define B_PCH_RTC_REGISTERC_UF BIT4 // Update-ended Flag
+#define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define R_PCH_RTC_REGISTERD 0x0D // RTC Register D
+#define B_PCH_RTC_REGISTERD_VRT BIT7 // Valid RAM and Time Bit
+#define B_PCH_RTC_REGISTERD_RESERVED BIT6
+#define B_PCH_RTC_REGISTERD_DA 0x3F // Date Alarm
+
+#define B_PCH_RTC_CENTURY 0x32 // Century Data
+
+//
+// APM Registers
+//
+#define R_PCH_APM_CNT 0xB2 // Advanced Power Management Control Port
+#define R_PCH_APM_STS 0xB3 // Advanced Power Management Status Port
+
+//
+// INIT Register
+//
+#define R_PCH_PORT92 0x92
+#define B_PCH_PORT92_ALT_A20_GATE BIT1 // Alternate A20 Gate
+#define B_PCH_PORT92_INIT_NOW BIT0 // Init Now
+
+//
+// PCU UART
+//
+#define R_PCH_COM1_BASE 0x3F8 // COM1 IO BASE
+
+//
+// Reset Control Register
+//
+#define R_PCH_RST_CNT 0xCF9 // Reset Control
+#define B_PCH_RST_CNT_FULL_RST BIT3
+#define B_PCH_RST_CNT_RST_CPU BIT2
+#define B_PCH_RST_CNT_SYS_RST BIT1
+#define V_PCH_RST_CNT_FULLRESET 0x0E
+#define V_PCH_RST_CNT_HARDRESET 0x06
+#define V_PCH_RST_CNT_SOFTRESET 0x04 // Not supported by CHV
+#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02
+#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00
+
+//
+// Fixed Memory Region
+//
+
+//
+// IO APIC Registers
+//
+#define R_PCH_IO_APIC_INDEX 0xFEC00000 // IOAPIC Index Register, 8bit
+#define R_PCH_IO_APIC_WINDOW 0xFEC00010 // IOAPIC Window Register, 32bit
+#define R_PCH_IO_APIC_EOI 0xFEC00040 // IOAPIC EOI Register, 8bit
+
+#define R_PCH_IO_APIC_ID 0x00 // Identification
+#define B_PCH_IO_APIC_ID_AID (BIT27 | BIT26 | BIT25 | BIT24) // APIC Identification
+
+#define R_PCH_IO_APIC_VS 0x01 // Version
+#define B_PCH_IO_APIC_VS_MRE 0xFF0000 // Maximum Redirection Entries
+#define B_PCH_IO_APIC_VS_PRQ BIT15 // Pin Assertion Register Supported
+#define B_PCH_IO_APIC_VS_VS 0xFF // Version
+
+//
+// HPET Registers
+//
+#define R_PCH_PCH_HPET 0xFED00000 // HPET Base Address
+
+#define R_PCH_PCH_HPET_GCID 0x00 // HPET General Capabilities and ID, 64bit
+#define B_PCH_PCH_HPET_GCID_CTP 0xFFFFFFFF00000000 // Counter Tick Period
+#define B_PCH_PCH_HPET_GCID_VID 0xFFFF0000 // Vendor ID
+#define B_PCH_PCH_HPET_GCID_LRC BIT15 // Legacy Rout Capable
+#define B_PCH_PCH_HPET_GCID_CS BIT13 // Counter Size
+#define B_PCH_PCH_HPET_GCID_NT 0x1F00 // Number of Timers
+#define B_PCH_PCH_HPET_GCID_RID 0xFF // Revision ID
+#define N_PCH_HPET_ADDR_ASEL 12
+
+#define R_PCH_PCH_HPET_GCFG 0x10 // HPET General Configuration
+#define B_PCH_PCH_HPET_GCFG_LRE BIT1 // Legacy Rout Enable
+#define B_PCH_PCH_HPET_GCFG_EN BIT0 // Overall Enable
+
+#define R_PCH_PCH_HPET_GIS 0x20 // HPET General Interrupt Status
+#define B_PCH_PCH_HPET_GIS_T2 BIT2 // Timer 2 Status
+#define B_PCH_PCH_HPET_GIS_T1 BIT1 // Timer 1 Status
+#define B_PCH_PCH_HPET_GIS_T0 BIT0 // Timer 0 Status
+
+#define R_PCH_PCH_HPET_MCV 0xF0 // HPET Main Counter Value, 64bit
+
+#define R_PCH_PCH_HPET_T0C 0x100 // HPET Timer 0 Config and Capabilities
+#define R_PCH_PCH_HPET_T0CV_L 0x108 // HPET Timer 0 Lower Comparator Value
+#define R_PCH_PCH_HPET_T0CV_H 0x10C // HPET Timer 0 Upper Comparator Value
+
+#define R_PCH_PCH_HPET_T1C 0x120 // HPET Timer 1 Config and Capabilities
+#define R_PCH_PCH_HPET_T1CV 0x128 // HPET Timer 1 Comparator Value
+
+#define R_PCH_PCH_HPET_T2C 0x140 // HPET Timer 2 Config and Capabilities
+#define R_PCH_PCH_HPET_T2CV 0x148 // HPET Timer 2 Comparator Value
+
+#define B_PCH_PCH_HPET_TXC_IRC 0xFFFFFFFF00000000 // Interrupt Rout Capability
+#define B_PCH_PCH_HPET_TXC_FID BIT15 // FSB Interrupt Delivery
+#define B_PCH_PCH_HPET_TXC_FE BIT14 // FSB Enable
+#define B_PCH_PCH_HPET_TXC_IR 0x3E00 // Interrupt Rout
+#define B_PCH_PCH_HPET_TXC_T32M BIT8 // Timer 32-bit Mode
+#define B_PCH_PCH_HPET_TXC_TVS BIT6 // Timer Value Set
+#define B_PCH_PCH_HPET_TXC_TS BIT5 // Timer Size
+#define B_PCH_PCH_HPET_TXC_PIC BIT4 // Periodic Interrupt Capable
+#define B_PCH_PCH_HPET_TXC_TYP BIT3 // Timer Type
+#define B_PCH_PCH_HPET_TXC_IE BIT2 // Interrupt Enable
+#define B_PCH_PCH_HPET_TXC_IT BIT1 // Timer Interrupt Type
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsRcrb.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsRcrb.h new file mode 100644 index 0000000000..d1a56badf5 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsRcrb.h @@ -0,0 +1,47 @@ +/** @file
+ Register names for Chipset Configuration Registers
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_RCRB_H_
+#define _PCH_REGS_RCRB_H_
+
+//
+// Chipset Configuration Registers (Memory space)
+// RCBA
+//
+#define R_PCH_RCRB_GCS 0x00 // General Control and Status
+#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
+#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps
+#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI
+#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC
+#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap
+#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSata.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSata.h new file mode 100644 index 0000000000..c6a36f792a --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSata.h @@ -0,0 +1,637 @@ +/** @file
+ Register names for SATA controllers.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_SATA_H_
+#define _PCH_REGS_SATA_H_
+
+//
+// SATA Controller Registers (D19:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_SATA 19
+#define PCI_FUNCTION_NUMBER_PCH_SATA 0
+
+#define R_PCH_SATA_ID 0x00 // Identifiers
+#define B_PCH_SATA_ID_DID 0xFFFF0000 // Device ID
+#define B_PCH_SATA_ID_VID 0x0000FFFF // Vendor ID
+#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define V_PCH_SATA_DEVICE_ID_D_IDE 0x22A0 // Desktop IDE Mode (Ports 0 and 1)
+#define V_PCH_SATA_DEVICE_ID_M_IDE 0x22A1 // Mobile IDE Mode (Ports 0 and 1)
+#define V_PCH_SATA_DEVICE_ID_D_AHCI 0x22A2 // Desktop AHCI Mode (Ports 0 and 1)
+#define V_PCH_SATA_DEVICE_ID_M_AHCI 0x22A3 // Mobile AHCI Mode (Ports 0 and 1)
+#define V_PCH_SATA_DEVICE_ID_D_RAID 0x2822 // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
+#define V_PCH_SATA_DEVICE_ID_M_RAID 0x282A // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
+
+#define R_PCH_SATA_COMMAND 0x04 // Command
+#define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable
+#define B_PCH_SATA_COMMAND_FBE BIT9 // Fast Back-to-back Enable
+#define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable
+#define B_PCH_SATA_COMMAND_WCC BIT7 // Wait Cycle Enable
+#define B_PCH_SATA_COMMAND_PER BIT6 // Parity Error Response Enable
+#define B_PCH_SATA_COMMAND_VPS BIT5 // VGA Palette Snooping Enable
+#define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
+#define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable
+#define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable
+#define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable
+#define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable
+
+#define R_PCH_SATA_PCISTS 0x06 // Device Status
+#define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error
+#define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error
+#define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
+#define B_PCH_SATA_PCISTS_RTA BIT12 // Received Target-Abort Status
+#define B_PCH_SATA_PCISTS_STA BIT11 // Signaled Target-Abort Status
+#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status
+#define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected
+#define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
+#define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status
+
+#define R_PCH_SATA_RID 0x08 // Revision ID (8 bits)
+
+#define R_PCH_SATA_PI_REGISTER 0x09 // Programming Interface (8 bits)
+#define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable
+#define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable
+#define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable
+#define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable
+
+#define R_PCH_SATA_CC 0x0A // Class Code
+#define B_PCH_SATA_CC_BCC 0xFF00 // Base Class Code
+#define B_PCH_SATA_CC_SCC 0x00FF // Sub Class Code
+#define V_PCH_SATA_CC_SCC_IDE 0x01
+#define V_PCH_SATA_CC_SCC_AHCI 0x06
+#define V_PCH_SATA_CC_SCC_RAID 0x04
+
+#define R_PCH_SATA_CLS 0x0C // Cache Line Size (8 bits)
+#define B_PCH_SATA_CLS 0xFF
+
+#define R_PCH_SATA_MLT 0x0D // Master Latency Timer (8 bits)
+#define B_PCH_SATA_MLT 0xFF
+
+#define R_PCH_SATA_HTYPE 0x0E // Header Type
+#define B_PCH_SATA_HTYPE_MFD BIT7 // Multi-function Device
+#define B_PCH_SATA_HTYPE_HL 0x7F // Header Layout
+#define R_PCH_SATA_PCMD_BAR 0x10 // Primary Command Block Base Address
+#define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 // Base Address
+#define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_PCTL_BAR 0x14 // Primary Control Block Base Address
+#define B_PCH_SATA_PCTL_BAR_BA 0x0000FFFC // Base Address
+#define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_SCMD_BAR 0x18 // Secondary Command Block Base Address
+#define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 // Base Address
+#define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_SCTL_BAR 0x1C // Secondary Control Block Base Address
+#define B_PCH_SATA_SCTL_BAR_BA 0x0000FFFC // Base Address
+#define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_LBAR 0x20 // AHCI Index Data Pair Base Address
+#define B_PCH_SATA_LBAR_BA 0x0000FFE0 // Base Address
+#define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_ABAR 0x24 // AHCI Base Address
+#define B_PCH_SATA_ABAR_BA 0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01)
+#define V_PCH_SATA_ABAR_LENGTH 0x800 // AHCI Memory Length (When CC.SCC not equal 0x01)
+#define N_PCH_SATA_ABAR_ALIGNMENT 11 // AHCI Base Address Alignment (When CC.SCC not equal 0x01)
+#define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable
+#define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
+#define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_SATA_SS 0x2C // Sub System Identifiers
+#define B_PCH_SATA_SS_SSID 0xFFFF0000 // Subsystem ID
+#define B_PCH_SATA_SS_SSVID 0x0000FFFF // Subsystem Vendor ID
+
+#define R_PCH_SATA_AHCI_CAP_PTR 0x34 // Capabilities Pointer (8 bits)
+#define B_PCH_SATA_AHCI_CAP_PTR 0xFF
+
+#define R_PCH_SATA_INTR 0x3C // Interrupt Information
+#define B_PCH_SATA_INTR_IPIN 0xFFFF0000 // Interrupt Pin
+#define B_PCH_SATA_INTR_ILINE 0x0000FFFF // Interrupt Line
+
+#define R_PCH_SATA_PID 0x70 // PCI Power Management Capability ID
+#define B_PCH_SATA_PID_NEXT 0xFF00 // Next Capability
+#define V_PCH_SATA_PID_NEXT_0 0xB000
+#define V_PCH_SATA_PID_NEXT_1 0xA800
+#define B_PCH_SATA_PID_CID 0x00FF // Cap ID
+
+#define R_PCH_SATA_PC 0x72 // PCI Power Management Capabilities
+#define S_PCH_SATA_PC 2
+#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) // PME Support
+#define V_PCH_SATA_PC_PME_0 0x0000
+#define V_PCH_SATA_PC_PME_1 0x4000
+#define B_PCH_SATA_PC_D2_SUP BIT10 // D2 Support
+#define B_PCH_SATA_PC_D1_SUP BIT9 // D1 Support
+#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) // Aux Current
+#define B_PCH_SATA_PC_DSI BIT5 // Device Specific Initialization
+#define B_PCH_SATA_PC_PME_CLK BIT3 // PME Clock
+#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) // VS
+
+#define R_PCH_SATA_PMCS 0x74 // PCI Power Management Control and Status
+#define B_PCH_SATA_PMCS_PMES BIT15 // PME Status
+#define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable
+#define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset
+#define V_PCH_SATA_PMCS_NSFRST_1 0x01
+#define V_PCH_SATA_PMCS_NSFRST_0 0x00
+#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State
+#define V_PCH_SATA_PMCS_PS_3 0x03
+#define V_PCH_SATA_PMCS_PS_0 0x00
+
+#define R_PCH_SATA_MID 0x80 // Message Signaled Interrupt Identifier
+#define B_PCH_SATA_MID_NEXT 0xFF00 // Next Pointer
+#define B_PCH_SATA_MID_CID 0x00FF // Capability ID
+
+#define R_PCH_SATA_MC 0x82 // Message Signaled Interrupt Message Control
+#define B_PCH_SATA_MC_C64 BIT7 // 64 Bit Address Capable
+#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) // Multiple Message Enable
+#define V_PCH_SATA_MC_MME_4 0x04
+#define V_PCH_SATA_MC_MME_2 0x02
+#define V_PCH_SATA_MC_MME_1 0x01
+#define V_PCH_SATA_MC_MME_0 0x00
+#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) // Multiple Message Capable
+#define V_PCH_SATA_MC_MMC_4 0x04
+#define V_PCH_SATA_MC_MMC_0 0x00
+#define B_PCH_SATA_MC_MSIE BIT0 // MSI Enable
+#define V_PCH_SATA_MC_MSIE_1 0x01
+#define V_PCH_SATA_MC_MSIE_0 0x00
+
+#define R_PCH_SATA_MA 0x84 // Message Signaled Interrupt Message Address
+#define B_PCH_SATA_MA 0xFFFFFFFC // Address
+
+#define R_PCH_SATA_MD 0x88 // Message Signaled Interrupt Message Data
+#define B_PCH_SATA_MD_MSIMD 0xFFFF // Data
+
+#define R_PCH_SATA_MAP 0x90 // Port Mapping Register
+#define B_PCH_SATA_MAP_SPD (BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
+#define B_PCH_SATA_PORT3_DISABLED BIT11
+#define B_PCH_SATA_PORT2_DISABLED BIT10
+#define B_PCH_SATA_PORT1_DISABLED BIT9
+#define B_PCH_SATA_PORT0_DISABLED BIT8
+#define B_PCH_SATA_MAP_SMS_MASK BIT6 // SATA Mode Select
+#define V_PCH_SATA_MAP_SMS_AHCI 0x00
+#define V_PCH_SATA_MAP_SMS_RAID 0x40
+
+//
+// SATA Workaround Bits
+//
+#define B_PCH_SATA_MAP_SMS_WA_BIT7 BIT7
+#define B_PCH_SATA_MAP_SMS_WA_BIT5 BIT5
+
+#define R_PCH_SATA_PCS 0x92 // Port Control and Status
+#define S_PCH_SATA_PCS 0x2
+#define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode
+#define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
+#define B_PCH_SATA_PCS_PORT4_DET BIT12 // Port 4 Present
+#define B_PCH_SATA_PCS_PORT3_DET BIT11 // Port 3 Present
+#define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present
+#define B_PCH_SATA_PCS_PORT1_DET BIT9 // Port 1 Present
+#define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
+#define B_PCH_SATA_PCS_PORT5_EN BIT5 // Port 5 Enabled
+#define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
+#define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled
+#define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled
+#define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled
+#define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled
+
+#define R_PCH_SATA_TM 0x94 // Test Mode Register
+#define B_PCH_SATA_TM_SNADD BIT31 // Speed Negotiation ALIGN Detection FSM Disable
+#define B_PCH_SATA_TM_PORT5_PCD BIT29 // Port 5 Clock Disable
+#define B_PCH_SATA_TM_PORT4_PCD BIT28 // Port 4 Clock Disable
+#define B_PCH_SATA_TM_PORT3_PCD BIT27 // Port 3 Clock Disable
+#define B_PCH_SATA_TM_PORT2_PCD BIT26 // Port 2 Clock Disable
+#define B_PCH_SATA_TM_PORT1_PCD BIT25 // Port 1 Clock Disable
+#define B_PCH_SATA_TM_PORT0_PCD BIT24 // Port 0 Clock Disable
+#define B_PCH_SATA_TM_SSD BIT23 // SyncFIFO Exposure Disable
+#define B_PCH_SATA_TM_SWTD BIT22 // SRST Watchdog Timer Disable
+#define B_PCH_SATA_TM_SFS BIT20 // Method select to qualify the SyncFIFO space
+#define B_PCH_SATA_TM_SLWS BIT19 // SyncFIFO Low Watermark Selection
+#define B_PCH_SATA_TM_FRRD BIT18 // FIS Retry on RERR Disable
+#define B_PCH_SATA_TM_FFBDC BIT17 // Fail FIS if BSY / DRQ Clear
+#define B_PCH_SATA_TM_WTTM BIT16 // Command FIS Watchdog Timer Test Mode
+#define B_PCH_SATA_TM_BEIE BIT14 // BERT Error Injection Enable
+#define B_PCH_SATA_TM_RSIXE (BIT12 | BIT11 | BIT10) // Relaxed SATA Initialization Extension Enable
+#define B_PCH_SATA_TM_MCO BIT9 // MSI Capability Override
+#define B_PCH_SATA_TM_NQIUFD BIT8 // AHCI Non-Queue Data-In Underflow Detection Enable
+#define B_PCH_SATA_TM_SCTI BIT7 // DMA Stops CI Progress Enable
+#define B_PCH_SATA_TM_PFAD BIT6 // PRD Fetch-Ahead Disable
+#define B_PCH_SATA_TM_CPGD BIT5 // CONT Primitive Generation Disable
+#define B_PCH_SATA_TM_BCUUD BIT4 // AHCI PRD Byte Count Update During AHCI data-In Underflow Disable
+#define B_PCH_SATA_TM_SDFTSEL (BIT3 | BIT2) // Short Data FIS Testmode Select [1:0]
+#define B_PCH_SATA_TM_RRSSEL (BIT1 | BIT0) // Read Request Size Select [1:0]
+
+#define R_PCH_SATA_SATAGC 0x9C // SATA General Configuration
+#define B_PCH_SATA_SATAGC_REGLOCK BIT31 // Register Lock
+#define B_PCH_SATA_SATAGC_WRRSELMPS (BIT14 | BIT13 | BIT12) // Write Request Size Select / Max Payload Size
+#define B_PCH_SATA_SATAGC_URRE BIT9 // Unsupported Request Reporting Enable
+#define B_PCH_SATA_SATAGC_URD BIT8 // Unsupported Request Detected
+#define B_PCH_SATA_SATAGC_AIE BIT7 // Alternate ID Enable
+#define B_PCH_SATA_SATAGC_DEVIDSEL BIT6 // AIE0 DevID Selection
+#define B_PCH_SATA_SATAGC_FLRCSSEL BIT5 // FLR Capability Selection
+#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3) // MXTBA Size Select
+#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) // ABAR Size Select
+
+#define R_PCH_SATA_SIRI 0xA0 // SATA Initialization Register Index
+#define B_PCH_SATA_SIRI_IDX 0xFC // Index
+
+#define R_PCH_SATA_SIRD 0xA4 // SATA Initialization Register Data
+#define B_PCH_SATA_SIRD_DTA 0xFFFFFFFF // Data
+
+#define R_PCH_SATA_CR0 0xA8 // Serial ATA Capability Register 0
+#define B_PCH_SATA_CR0_MAJREV 0x00F00000 // Major Revision
+#define B_PCH_SATA_CR0_MINREV 0x000F0000 // Minor Revision
+#define B_PCH_SATA_CR0_NEXT 0x0000FF00 // Next Capability Pointer
+#define B_PCH_SATA_CR0_CAP 0x000000FF // Capability ID
+
+#define R_PCH_SATA_CR1 0xAC // Serial ATA Capability Register 1
+#define B_PCH_SATA_CR1_BAROFST 0xFFF0 // BAR Offset
+#define B_PCH_SATA_CR1_BARLOC 0x000F // BAR Location
+
+#define R_PCH_SATA_FLR_CID 0xB0 // FLR Capability ID
+#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 // Next Capability Pointer
+#define B_PCH_SATA_FLR_CID 0x00FF // Capability ID
+#define V_PCH_SATA_FLR_CID_1 0x0009
+#define V_PCH_SATA_FLR_CID_0 0x0013
+
+#define R_PCH_SATA_FLR_CLV 0xB2 // FLR Capability Length and Version
+#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 // FLR Capability
+#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 // TXP Capability
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF // Capability Length
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF // Capability Length
+#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006
+
+#define R_PCH_SATA_FLRC 0xB4 // FLR Control
+#define B_PCH_SATA_FLRC_TXP BIT8 // Transactions Pending
+#define B_PCH_SATA_FLRC_INITFLR BIT0 // Initiate FLR
+
+#define R_PCH_SATA_BFCS 0xE0 // BIST FIS Control / Status
+#define B_PCH_SATA_BFCS_P5BFI BIT15 // Port 5 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_P4BFI BIT14 // Port 4 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_P3BFI BIT13 // Port 3 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_P2BFI BIT12 // Port 2 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_BFS BIT11 // BIST FIS Successful
+#define B_PCH_SATA_BFCS_BFF BIT10 // BIST FIS Failed
+#define B_PCH_SATA_BFCS_P1BFI BIT9 // Port 1 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_P0BFI BIT8 // Port 0 BIST FIS Initiate
+#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7
+#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6
+#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5
+#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4
+#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3
+#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2
+
+#define R_PCH_SATA_BFTD1 0xE4 // BIST FIS Transmit Data 1
+#define B_PCH_SATA_BFTD1 0xFFFFFFFF // Data
+
+#define R_PCH_SATA_BFTD2 0xE8 // BIST FIS Transmit Data 2
+#define B_PCH_SATA_BFTD2 0xFFFFFFFF // Data
+
+#define R_PCH_SATA_MFID 0xF8 // Manufacturing ID
+#define B_PCH_SATA_MFID_DID 0x0F000000 // DOT ID
+#define B_PCH_SATA_MFID_SID 0x00FF0000 // Stepping ID
+#define B_PCH_SATA_MFID_MID 0x0000FF00 // Manufacturer ID
+#define B_PCH_SATA_MFID_PID 0x000000FF // Process ID
+
+//
+// Memory AHCI BAR Area Related Registers
+//
+#define R_PCH_SATA_AHCI_CAP 0x0 // HBA Capabilities
+#define B_PCH_SATA_AHCI_CAP_S64A BIT31 // Supports 64-bit Addressing
+#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 // Support Native Command Queuing Acceleration
+#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 // Supports SNotification Register
+#define B_PCH_SATA_AHCI_CAP_SMPS BIT28 // Supports Mechanical Presence (Formerly Interlock Switch)
+#define B_PCH_SATA_AHCI_CAP_SSS BIT27 // Supports Staggered Spin-up
+#define B_PCH_SATA_AHCI_CAP_SALP BIT26 // Supports Aggressive Link Power Management
+#define B_PCH_SATA_AHCI_CAP_SAL BIT25 // Supports Activity LED
+#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 // Supports Command List Override
+#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) // Interface Speed Support
+#define N_PCH_SATA_AHCI_CAP_ISS 20 // Interface Speed Support
+#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 // Gen 3 (6.0 Gbps)
+#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 // Gen 2 (3.0 Gbps)
+#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 // Gen 1 (1.5 Gbps)
+#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 // Supports Non-Zero DMA Offsets
+#define B_PCH_SATA_AHCI_CAP_SAM BIT18 // Supports AHCI mode only
+#define B_PCH_SATA_AHCI_CAP_PMS BIT17 // Supports Port Multiplier
+#define B_PCH_SATA_AHCI_CAP_PMD BIT15 // PIO Multiple DRQ Block
+#define B_PCH_SATA_AHCI_CAP_SSC BIT14 // Slumber Slate Capable
+#define B_PCH_SATA_AHCI_CAP_PSC BIT13 // Partial State Capable
+#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 // Indicating Support for 32 slots
+#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 // Command Completion Coalescing Supported
+#define B_PCH_SATA_AHCI_CAP_EMS BIT6 // Enclosure Management Supported
+#define B_PCH_SATA_AHCI_CAP_SXS BIT5 // Supports External SATA
+#define B_PCH_SATA_AHCI_CAP_NPS 0x001F // Number of Ports
+
+#define R_PCH_SATA_AHCI_GHC 0x04 // Global HBA Control
+#define B_PCH_SATA_AHCI_GHC_AE BIT31 // AHCI Enable
+#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 // MSI Revert to Single Message
+#define B_PCH_SATA_AHCI_GHC_IE BIT1 // Interrupt Enable
+#define B_PCH_SATA_AHCI_GHC_HR BIT0 // HBA Reset
+
+#define R_PCH_SATA_AHCI_IS 0x08 // Interrupt Status Register
+#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 // Interrupt Pending Status Port 5
+#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 // Interrupt Pending Status Port 4
+#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 // Interrupt Pending Status Port 3
+#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 // Interrupt Pending Status Port 2
+#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 // Interrupt Pending Status Port 1
+#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 // Interrupt Pending Status Port 0
+
+#define R_PCH_SATA_AHCI_PI 0x0C // Ports Implemented
+#define B_PCH_SATA_PORT_MASK 0x3F
+#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 // Port 5 Implemented
+#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
+#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
+#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented
+#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
+#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 // Port 0 Implemented
+
+#define R_PCH_SATA_AHCI_VS 0x10 // AHCI Version
+#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 // Major Version Number
+#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF // Minor Version Number
+
+#define R_PCH_SATA_AHCI_EM_LOC 0x1C // Enclosure Management Location
+#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 // Offset
+#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF // Buffer Size
+
+#define R_PCH_SATA_AHCI_EM_CTRL 0x20 // Enclosure Management Control
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_PM BIT27 // Port Multiplier Support
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 // Activity LED Hardware Driven
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 // Transmit Only
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 // Single Message Buffer
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 // SGPIO Enclosure Management Messages
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 // SES-2 Enclosure Management Messages
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 // SAF-TE Enclosure Management Messages
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 // LED Message Types
+#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 // Reset
+#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 // Transmit Message
+#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 // Message Received
+
+#define R_PCH_SATA_AHCI_CAP2 0x24 // HBA Capabilities Extended
+#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 // DEVSLP Entrance from Slumber Only
+#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 // Supports Aggressive DEVSLP Management
+#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 // Supports DEVSLP
+#define B_PCH_SATA_AHCI_CAP2_APST BIT2 // Automatic Partial to Slumber Transitions
+#define B_PCH_SATA_AHCI_CAP2_BOH BIT0 // BIOS / OS Handoff (Not Supported)
+
+#define R_PCH_SATA_AHCI_VSP 0xA0 // Vendor Specific
+#define B_PCH_SATA_AHCI_VSP_SFMS BIT6 // Software Feature Mask Supported
+#define B_PCH_SATA_AHCI_VSP_PFS BIT5 // Premium Features Supported
+#define B_PCH_SATA_AHCI_VSP_PT BIT4 // Platform Type
+#define B_PCH_SATA_AHCI_VSP_SRPIR BIT3 // Supports RAID Platform ID Reporting
+
+#define R_PCH_SATA_AHCI_VSCAP 0xA4 // Vendor Specific Capabilities Register
+#define B_PCH_SATA_AHCI_VSCAP_PNRRO 0xFFFF0000 // PCIe NAND Remapped Register Offset
+#define B_PCH_SATA_AHCI_VSCAP_MSL 0x00000FFE
+#define B_PCH_SATA_AHCI_VSCAP_PNABRE BIT0 // PCIe NAND AHCI BAR Remapped Enable
+
+#define R_PCH_SATA_AHCI_RPID 0xC0 // RAID Platform ID
+#define B_PCH_SATA_AHCI_RPID_OFST 0xFFFF0000 // Offset
+#define B_PCH_SATA_AHCI_RPID_RPID 0x0000FFFF // RAID Platform ID
+
+#define R_PCH_SATA_AHCI_PFB 0xC4 // Premium Feature Block
+#define B_PCH_SATA_AHCI_PFB_SEA BIT1 // Supports Email Alert
+#define B_PCH_SATA_AHCI_PFB_SOI BIT0 // Supports OEM IOCTL
+
+#define R_PCH_SATA_AHCI_SFM 0xC8 // SW Feature Mask
+#define B_PCH_SATA_AHCI_SFM_OUND (BIT11 | BIT10) // OROM UI Normal Delay
+#define B_PCH_SATA_AHCI_SFM_SRT BIT9 // Smart Response Technology
+#define B_PCH_SATA_AHCI_SFM_IROES BIT8 // IRRT Only on ESATA
+#define B_PCH_SATA_AHCI_SFM_LEDL BIT7 // LED Locate
+#define B_PCH_SATA_AHCI_SFM_HDDLK BIT6 // HDD Unlock
+#define B_PCH_SATA_AHCI_SFM_OROMUNB BIT5 // OROM UI and Banner
+#define B_PCH_SATA_AHCI_SFM_IRRT BIT4 // IRRT
+#define B_PCH_SATA_AHCI_SFM_R5E BIT3 // R5 Enable
+#define B_PCH_SATA_AHCI_SFM_R10E BIT2 // R10 Enable
+#define B_PCH_SATA_AHCI_SFM_R1E BIT1 // R1 Enable
+#define B_PCH_SATA_AHCI_SFM_R0E BIT0 // R0 Enable
+#define B_PCH_SATA_AHCI_SFM_LOWBYTES 0x1FF
+
+#define R_PCH_SATA_AHCI_P0CLB 0x100 // Port 0 Command List Base Address
+#define R_PCH_SATA_AHCI_P1CLB 0x180 // Port 1 Command List Base Address
+#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 // Command List Base Address
+
+#define R_PCH_SATA_AHCI_P0CLBU 0x104 // Port 0 Command List Base Address Upper 32-bits
+#define R_PCH_SATA_AHCI_P1CLBU 0x184 // Port 1 Command List Base Address Upper 32-bits
+#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF // Command List Base Address Upper
+
+#define R_PCH_SATA_AHCI_P0FB 0x108 // Port 0 FIS Base Address
+#define R_PCH_SATA_AHCI_P1FB 0x188 // Port 1 FIS Base Address
+#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 // FIS Base Address
+
+#define R_PCH_SATA_AHCI_P0FBU 0x10C // Port 0 FIS Base Address Upper 32-bits
+#define R_PCH_SATA_AHCI_P1FBU 0x18C // Port 1 FIS Base Address Upper 32-bits
+#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF // FIS Base Address Upper
+
+#define R_PCH_SATA_AHCI_P0IS 0x110 // Port 0 Interrupt Status
+#define R_PCH_SATA_AHCI_P1IS 0x190 // Port 1 Interrupt Status
+#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 // Cold Presence Detect Status
+#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 // Task File Error Status
+#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 // Host Bus Fatal Error Status
+#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 // Host Bus Data Error Status
+#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 // Interface Fatal Error Status
+#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 // Interface Non-Fatal Error Status
+#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 // Overflow Status
+#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 // Incorrect Port Multiplier Status
+#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 // PhyRdy Change Status
+#define B_PCH_SATA_AHCI_PXIS_DMPS BIT7 // Device Mechanical Presence Status (Formerly Interlock Switch)
+#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 // Port Connect Change Status
+#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 // Descriptor Processed
+#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 // Unknown FIS Interrupt
+#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 // Set Device Bits Interrupt
+#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 // DMA Setup FIS Interrupt
+#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 // PIO Setup FIS Interrupt
+#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 // Device to Host Register FIS Interrupt
+
+#define R_PCH_SATA_AHCI_P0IE 0x114 // Port 0 Interrupt Enable
+#define R_PCH_SATA_AHCI_P1IE 0x194 // Port 1 Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 // Cold Presence Detect Enable
+#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 // Task File Error Enable
+#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 // Host Bus Fatal Error Enable
+#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 // Host Bus Data Error Enable
+#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 // Interface Fatal Error Enable
+#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 // Interface Non-Fatal Error Enable
+#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 // Overflow Enable
+#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 // Incorrect Port Multiplier Enable
+#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 // PhyRdy Change Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 // Device Mechanical Enable (Formerly Interlock Switch)
+#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 // Port Change Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 // Descriptor Processed Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 // Unknown FIS Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 // Set Device Bits FIS Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 // DMA Setup FIS Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 // PIO Setup FIS Interrupt Enable
+#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 // Device to Host Register FIS Interrupt Enable
+
+#define R_PCH_SATA_AHCI_P0CMD 0x118 // Port 0 Command
+#define R_PCH_SATA_AHCI_P1CMD 0x198 // Port 1 Command
+#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) // Interface Communication Control
+#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT21 | BIT22 | BIT19 | BIT18)
+#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 // Aggressive Slumber Partial
+#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 // Aggressive Link Power Management Enable
+#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 // Drive LED on ATAPI Enable
+#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 // Device is ATAPI
+#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 // Automatic Partial to Slumber Transitions Enable
+#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 // External SATA Port
+#define B_PCH_SATA_AHCI_PxCMD_CPD BIT20 // Cold Presence Detection
+#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 // Mechanical Presence Switch Attached to Port
+#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 // Hot Plug Capable Port
+#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 // Command List Running
+#define B_PCH_SATA_AHCI_PxCMD_FR BIT14 // FIS Receive Running
+#define B_PCH_SATA_AHCI_PxCMD_MPSS BIT13 // Mechanical Presence Switch State (Formerly Interlock Switch)
+#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 // Current Command Slot
+#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4 // FIS Receive Enable
+#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 // Command List Overide
+#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 // Power On Device
+#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 // Spin-Up Device
+#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 // Start
+
+#define R_PCH_SATA_AHCI_P0TFD 0x120 // Port 0 Task File Data
+#define R_PCH_SATA_AHCI_P1TFD 0x1A0 // Port 1 Task File Data
+#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 // Error
+#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF // Status
+#define B_PCH_SATA_AHCI_PXTFD_STS_BSY BIT7 // Status Busy
+#define B_PCH_SATA_AHCI_PXTFD_STS_DRQ BIT3 // Status DRQ
+#define B_PCH_SATA_AHCI_PXTFD_STS_ERR BIT0 // Status Error
+
+#define R_PCH_SATA_AHCI_P0SIG 0x124 // Port 0 Signature
+#define R_PCH_SATA_AHCI_P1SIG 0x1A4 // Port 1 Signature
+#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00
+#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF
+
+#define R_PCH_SATA_AHCI_P0SSTS 0x128 // Port 0 Serial ATA Status
+#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 // Port 1 Serial ATA Status
+#define B_PCH_SATA_AHCI_PXSSTS_IPM 0x00000F00 // Interface Power Management
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600
+#define B_PCH_SATA_AHCI_PXSSTS_SPD 0x000000F0 // Current Interface Speed
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 // Device not present or communication not established
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 // Generation 1 communication rate negotiated
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 // Generation 2 communication rate negotiated
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 // Generation 3 communication rate negotiated
+#define B_PCH_SATA_AHCI_PXSSTS_DET 0x0000000F // Device Detection
+#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 // No device detected and Phy communication not established
+#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 // Device presence detected but Phy communication not established
+#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 // Device presence detected and Phy communication established
+#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 // Phy in offline mode
+
+#define R_PCH_SATA_AHCI_P0SCTL 0x12C // Port 0 Serial ATA Control
+#define R_PCH_SATA_AHCI_P1SCTL 0x1AC // Port 1 Serial ATA Control
+#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 // Interface Power Management Transitions Allowed
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300
+#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 // Highest Allowable Speed
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 // No Speed Restriction
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 // Max Gen 1 Speed
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 // Max Gen 2 Speed
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 // Max Gen 3 Speed
+#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F // Device Detection Initialization
+#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 // No device detection or initialization action requested
+#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 // Perform interface communication initialization sequence to establish communication
+#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 // Disable the Serial ATA interface and put Phy in offline mode
+
+#define R_PCH_SATA_AHCI_P0SERR 0x130 // Port 0 Serial ATA Error
+#define R_PCH_SATA_AHCI_P1SERR 0x1B0 // Port 1 Serial ATA Error
+#define B_PCH_SATA_AHCI_PXSERR_DIAG 0xFFFF0000 // Diagnostics
+#define B_PCH_SATA_AHCI_PXSERR_ERR 0x0000FFFF // Error
+#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26
+#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23
+#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22
+#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21
+#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19
+#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18
+#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17
+#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16
+#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11
+#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10
+#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9
+#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8
+#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1
+#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0
+
+#define R_PCH_SATA_AHCI_P0SACT 0x134 // Port 0 Serial ATA Active
+#define R_PCH_SATA_AHCI_P1SACT 0x1B4 // Port 1 Serial ATA Active
+#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF
+
+#define R_PCH_SATA_AHCI_P0CI 0x138 // Port 0 Commands Issued
+#define R_PCH_SATA_AHCI_P1CI 0x1B8 // Port 1 Commands Issued
+#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF
+
+#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 // Port [0] Device Sleep
+#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 // Port [1] Device Sleep
+#define B_PCH_SATA_AHCI_PXDEVSLP_DM 0x1E000000 // DITO Multiplier
+#define V_PCH_SATA_AHCI_PXDEVSLP_DM_16 0x1E000000
+#define B_PCH_SATA_AHCI_PXDEVSLP_DITO 0x01FF8000 // DEVSLP Idle Timeout
+#define V_PCH_SATA_AHCI_PXDEVSLP_DITO_625 0x01388000
+#define B_PCH_SATA_AHCI_PXDEVSLP_MDAT 0x00007C00 // DEVSLP Minimum Assertion Time
+#define B_PCH_SATA_AHCI_PXDEVSLP_DETO 0x000003FC // DEVSLP Exit Timeout
+#define B_PCH_SATA_AHCI_PXDEVSLP_DSP BIT1 // Device Sleep Present
+#define B_PCH_SATA_AHCI_PXDEVSLP_ADSE BIT0 // Aggressive DEVSLP Enable
+
+#define R_PCH_SATA_AHCI_EM_MF 0x580 // Enclosure Management Message Format
+#define B_PCH_SATA_AHCI_EM_MF_MTYPE 0x0F000000 // Message Type
+#define B_PCH_SATA_AHCI_EM_MF_DSIZE 0x00FF0000 // Data Size
+#define B_PCH_SATA_AHCI_EM_MF_MSIZE 0x0000FF00 // Message Size
+
+#define R_PCH_SATA_AHCI_EM_LED 0x584 // Enclosure Management LED
+#define B_PCH_SATA_AHCI_EM_LED_VAL 0xFFFF0000 // Value
+#define B_PCH_SATA_AHCI_EM_LED_PM 0x0000FF00 // Port Multiplier Information
+#define B_PCH_SATA_AHCI_EM_LED_HBA 0x000000FF // HBA Information
+
+//
+// Macros of capabilities for SATA controller which are used by SATA controller driver
+//
+//
+//
+// Define the individual capabilities of each SATA controller
+//
+#define PCH_SATA_MAX_CONTROLLERS 1 // Max SATA controllers number supported
+#define PCH_SATA_MAX_DEVICES 2 // Max SATA devices number of single SATA channel
+#define PCH_IDE_MAX_CHANNELS 2 // Max IDE channels number of single SATA controller
+#define PCH_IDE_MAX_DEVICES 2 // Max IDE devices number of single SATA channel
+#define PCH_AHCI_MAX_PORTS 2 // Max number of SATA ports
+#define PCH_IDE_MAX_PORTS 2 // Max number of IDE ports
+
+//
+// CFIO SouthWest SATAGP0 is the SATA port 0 reset pin.
+//
+#define R_PCH_CFIO_SATA_GP0_PAD_CFG0 0x5800
+//
+// CFIO SouthWest SATAGP1 is the SATA port 1 reset pin.
+//
+#define R_PCH_CFIO_SATA_GP1_PAD_CFG0 0x5808
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsScc.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsScc.h new file mode 100644 index 0000000000..18341667bd --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsScc.h @@ -0,0 +1,245 @@ +/** @file
+ Register names for SCC module.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_SCC_H_
+#define _PCH_REGS_SCC_H_
+
+//
+// SCC Modules Registers
+//
+
+//
+// SCC SDIO Modules
+// PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0 16
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1 17
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2 18
+#define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO 0
+
+#define R_PCH_SCC_SDIO_DEVVENDID 0x00 // Device ID & Vendor ID
+#define B_PCH_SCC_SDIO_DEVVENDID_DID 0xFFFF0000 // Device ID
+#define B_PCH_SCC_SDIO_DEVVENDID_VID 0x0000FFFF // Vendor ID
+
+#define R_PCH_SCC_SDIO_STSCMD 0x04 // Status & Command
+#define B_PCH_SCC_SDIO_STSCMD_RMA BIT29 // RMA
+#define B_PCH_SCC_SDIO_STSCMD_RCA BIT28 // RCA
+#define B_PCH_SCC_SDIO_STSCMD_CAPLIST BIT20 // Capability List
+#define B_PCH_SCC_SDIO_STSCMD_INTRSTS BIT19 // Interrupt Status
+#define B_PCH_SCC_SDIO_STSCMD_INTRDIS BIT10 // Interrupt Disable
+#define B_PCH_SCC_SDIO_STSCMD_SERREN BIT8 // SERR# Enable
+#define B_PCH_SCC_SDIO_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_SCC_SDIO_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_SCC_SDIO_REVCC 0x08 // Revision ID & Class Code
+#define B_PCH_SCC_SDIO_REVCC_CC 0xFFFFFF00 // Class Code
+#define B_PCH_SCC_SDIO_REVCC_RID 0x000000FF // Revision ID
+
+#define R_PCH_SCC_SDIO_CLHB 0x0C
+#define B_PCH_SCC_SDIO_CLHB_MULFNDEV BIT23 // Multi Function Device
+#define B_PCH_SCC_SDIO_CLHB_HT 0x007F0000 // Header Type
+#define B_PCH_SCC_SDIO_CLHB_LT 0x0000FF00 // Latency Timer
+#define B_PCH_SCC_SDIO_CLHB_CLS 0x000000FF // Cache Line Size
+
+#define R_PCH_SCC_SDIO_BAR 0x10 // BAR
+#define B_PCH_SCC_SDIO_BAR_BA 0xFFFFF000 // Base Address
+#define V_PCH_SCC_SDIO_BAR_SIZE 0x1000
+#define N_PCH_SCC_SDIO_BAR_ALIGNMENT 12
+#define B_PCH_SCC_SDIO_BAR_SI 0x00000FF0 // Size Indicator
+#define B_PCH_SCC_SDIO_BAR_PF BIT3 // Prefetchable
+#define B_PCH_SCC_SDIO_BAR_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_SCC_SDIO_BAR_MS BIT0 // Message Space
+
+#define R_PCH_SCC_SDIO_BAR_HIGH 0x14 // BAR High
+#define B_PCH_SCC_SDIO_BAR_HIGH_BA 0xFFFFFFFF // Base Address
+
+#define R_PCH_SCC_SDIO_BAR1 0x18 // BAR 1
+#define B_PCH_SCC_SDIO_BAR1_BA 0xFFFFF000 // Base Address
+#define V_PCH_SCC_SDIO_BAR1_SIZE 0x1000
+#define B_PCH_SCC_SDIO_BAR1_SI 0x00000FF0 // Size Indicator
+#define B_PCH_SCC_SDIO_BAR1_PF BIT3 // Prefetchable
+#define B_PCH_SCC_SDIO_BAR1_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_SCC_SDIO_BAR1_MS BIT0 // Message Space
+
+#define R_PCH_SCC_SDIO_BAR1_HIGH 0x1C // BAR 1 High
+#define B_PCH_SCC_SDIO_BAR1_HIGH_BA 0xFFFFFFFF // Base Address
+
+#define R_PCH_SCC_SDIO_SSID 0x2C // Sub System ID
+#define B_PCH_SCC_SDIO_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_SCC_SDIO_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_SCC_SDIO_ERBAR 0x30 // Expansion ROM BAR
+#define B_PCH_SCC_SDIO_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
+
+#define R_PCH_SCC_SDIO_CAPPTR 0x34 // Capability Pointer
+#define B_PCH_SCC_SDIO_CAPPTR_CPPWR 0xFF // Capability Pointer Power
+
+#define R_PCH_SCC_SDIO_INTR 0x3C // Interrupt
+#define B_PCH_SCC_SDIO_INTR_ML 0xFF000000 // Max Latency
+#define B_PCH_SCC_SDIO_INTR_MG 0x00FF0000
+#define B_PCH_SCC_SDIO_INTR_IP 0x00000F00 // Interrupt Pin
+#define B_PCH_SCC_SDIO_INTR_IL 0x000000FF // Interrupt Line
+
+#define R_PCH_SCC_SDIO_PCAPID 0x80 // Power Capability ID
+#define B_PCH_SCC_SDIO_PCAPID_PS 0xF8000000 // PME Support
+#define B_PCH_SCC_SDIO_PCAPID_VS 0x00070000 // Version
+#define B_PCH_SCC_SDIO_PCAPID_NC 0x0000FF00 // Next Capability
+#define B_PCH_SCC_SDIO_PCAPID_PC 0x000000FF // Power Capability
+
+#define R_PCH_SCC_SDIO_PCS 0x84 // PME Control Status
+#define B_PCH_SCC_SDIO_PCS_PMESTS BIT15 // PME Status
+#define B_PCH_SCC_SDIO_PCS_PMEEN BIT8 // PME Enable
+#define B_PCH_SCC_SDIO_PCS_NSS BIT3 // No Soft Reset
+#define B_PCH_SCC_SDIO_PCS_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_SCC_SDIO_GEN_REGRW1 0xA0 // General Purpose Read Write Register 1
+
+#define R_PCH_SCC_SDIO_GEN_REGRW2 0xA4 // General Purpose Read Write Register 2
+
+#define R_PCH_SCC_SDIO_GEN_REGRW3 0xA8 // General Purpose Read Write Register 3
+
+#define R_PCH_SCC_SDIO_GEN_REGRW4 0xAC // General Purpose Read Write Register 4
+
+#define R_PCH_SCC_SDIO_MANID 0xF8 // Manufacturer ID
+#define B_PCH_SCC_SDIO_MANID_MANID 0xFFFFFFFF // Manufacturer ID
+
+//
+// SCC SDIO Module
+// MMIO Space Register
+//
+#define R_PCH_SCC_SDIO_MEM_SYS_ADR 0x00 // SDMA System Address
+
+#define R_PCH_SCC_SDIO_MEM_BLK_SIZE 0x04 // Block Size
+
+#define R_PCH_SCC_SDIO_MEM_BLK_COUNT 0x06 // Block Count
+
+#define R_PCH_SCC_SDIO_MEM_ARGUMENT 0x08 // Argument
+
+#define R_PCH_SCC_SDIO_MEM_TX_MODE 0x0C // Transfer Mode
+#define B_PCH_SCC_SDIO_MEM_TX_MODE_BLK_SEL BIT5 // Multi / Single Block Select, 1: Multiple Block; 0: Single Block
+#define B_PCH_SCC_SDIO_MEM_TX_MODE_DATA_TR_DIR BIT4 // Data Transfer Direction Select, 1: Read (Card to Host); 0: Write (Host to Card)
+#define B_PCH_SCC_SDIO_MEM_TX_MODE_AUTO_CMD_EN (BIT3 | BIT2) // Auto Command Function Enable
+#define B_PCH_SCC_SDIO_MEM_TX_MODE_BLK_COUNT_EN BIT1 // Block Count Enable
+#define B_PCH_SCC_SDIO_MEM_TX_MODE_DMA_EN BIT0 // DMA Enable
+
+#define R_PCH_SCC_SDIO_MEM_CMD 0x0E // Command
+#define B_PCH_SCC_SDIO_MEM_CMD_DATA_PR_SEL BIT5 // Data Present Select
+#define B_PCH_SCC_SDIO_MEM_CMD_CMD_INDEX_CHK_EN BIT4 // Command Index Check Enable
+#define B_PCH_SCC_SDIO_MEM_CMD_CMD_CRC_CHK_EN BIT3 // Command CRC Check Enable
+#define B_PCH_SCC_SDIO_MEM_CMD_RTS_MASK (BIT1 | BIT0) // Response Type Select
+#define V_PCH_SCC_SDIO_MEM_CMD_RTS_NO_RESP 0
+#define V_PCH_SCC_SDIO_MEM_CMD_RTS_RESP136 1
+#define V_PCH_SCC_SDIO_MEM_CMD_RTS_RESP48 2
+#define V_PCH_SCC_SDIO_MEM_CMD_RTS_RESP48_CHK 3
+
+#define R_PCH_SCC_SDIO_MEM_RESPONSE0 0x10 // Response 0
+
+#define R_PCH_SCC_SDIO_MEM_BUF_DATA_PORT 0x20 // Buffer Data Port
+
+#define R_PCH_SCC_SDIO_MEM_PRE_STATE 0x24 // Present State
+#define B_PCH_SCC_SDIO_MEM_PRE_STATE_DLSL0 BIT20 // DAT[0] Line Signal Level
+
+#define R_PCH_SCC_SDIO_MEM_HOST_CTL 0x28 // Host Control
+#define B_PCH_SCC_SDIO_MEM_HOST_CTL_CDSS BIT7 // Card Detect Signal Selection
+#define B_PCH_SCC_SDIO_MEM_HOST_CTL_CDTL BIT6 // Card Detect Test Level
+
+#define R_PCH_SCC_SDIO_MEM_PWR_CTL 0x29 // Power Control
+#define B_PCH_SCC_SDIO_MEM_PWR_CTL_SD_VOLSEL (BIT3 | BIT2 | BIT1) // SD Bus Voltage Select
+#define V_PCH_SCC_SDIO_MEM_PWR_CTL_SD_VOLSEL_3P3 (BIT3 | BIT2 | BIT1) // 3.3V
+#define V_PCH_SCC_SDIO_MEM_PWR_CTL_SD_VOLSEL_1P8 (BIT3 | BIT1) // 1.8V
+#define B_PCH_SCC_SDIO_MEM_PWR_CTL_SD_PWR BIT0 // SD Bus Power
+
+#define R_PCH_SCC_SDIO_MEM_CLK_CTL 0x2C // Clock Control
+
+#define R_PCH_SCC_SDIO_MEM_TIMEOUT_CTL 0x2E // Timeout Control
+#define B_PCH_SCC_SDIO_MEM_TIMEOUT_CTL_DTCV 0x0F // Data Timeout Counter Value
+
+#define R_PCH_SCC_SDIO_MEM_SW_RST 0x2F // Software Reset
+#define B_PCH_SCC_SDIO_MEM_SW_RST_SW_RST_DAT_LN BIT2 // Software Reset For DAT Line
+#define B_PCH_SCC_SDIO_MEM_SW_RST_SW_RST_CMD_LN BIT1 // Software Reset For CMD Line
+#define B_PCH_SCC_SDIO_MEM_SW_RST_SW_RST_ALL BIT0 // Software Reset For All
+
+#define R_PCH_SCC_SDIO_MEM_NINTSTS 0x30 // Normal Interrupt Status
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_MASK 0xFFFF
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_CLEAR_MASK 0x60FF
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_BUF_RD_RDY BIT5 // Buffer Read Ready
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_DMA_INT BIT3 // DMA Interrupt
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_TX_COMP BIT1 // Transfer Complete
+#define B_PCH_SCC_SDIO_MEM_NINTSTS_CMD_COMP BIT0 // Command Complete
+
+#define R_PCH_SCC_SDIO_MEM_ERINTSTS 0x32 // Error Interrupt Status
+#define B_PCH_SCC_SDIO_MEM_ERINTSTS_MASK 0x13FF
+#define B_PCH_SCC_SDIO_MEM_ERINTSTS_CLEAR_MASK 0x13FF
+
+#define R_PCH_SCC_SDIO_MEM_NINTEN 0x34 // Normal Interrupt Status Enable
+#define B_PCH_SCC_SDIO_MEM_NINTEN_MASK 0x7FFF
+
+#define R_PCH_SCC_SDIO_MEM_ERINTEN 0x36 // Error Interrupt Status Enable
+#define B_PCH_SCC_SDIO_MEM_ERINTEN_MASK 0x13FF
+
+#define R_PCH_SCC_SDIO_MEM_NINTSIGNEN 0x38 // Normal Interrupt Signal Enable
+#define B_PCH_SCC_SDIO_MEM_NINTSIGNEN_MASK 0x7FFF
+
+#define R_PCH_SCC_SDIO_MEM_ERINTSIGNEN 0x3A // Error Interrupt Signal Enable
+#define B_PCH_SCC_SDIO_MEM_ERINTSIGNEN_MASK 0x13FF
+
+#define R_PCH_SCC_SDIO_MEM_CESHC2 0x3C // Auto CMD12 Error Status Register & Host Control 2
+#define B_PCH_SCC_SDIO_MEM_CESHC2_ASYNC_INT BIT30 // Asynchronous Interrupt Enable
+#define B_PCH_SCC_SDIO_MEM_CESHC2_MODE_MASK (BIT18 | BIT17 | BIT16)
+#define V_PCH_SCC_SDIO_MEM_CESHC2_MODE_HS400 (5 << 16)
+#define V_PCH_SCC_SDIO_MEM_CESHC2_MODE_SDR104 (3 << 16)
+
+#define R_PCH_SCC_SDIO_MEM_CAP 0x40 // Capabilities
+#define B_PCH_SCC_SDIO_MEM_CAP_BASE_CLK_FREQ 0xFF00 // Base Clock Frequency
+
+#define R_PCH_SCC_SDIO_MEM_CAP2 0x44 // Capabilities 2
+#define B_PCH_SCC_SDIO_MEM_CAP2_HS400_SUPPORT BIT31
+#define B_PCH_SCC_SDIO_MEM_CAP2_SDR104_SUPPORT BIT1
+///
+/// SCC Private Space
+///
+#define PCH_SCC_EP_PORT_ID 0x63 // SCC EP Private Space PortID
+#define PCH_SCC_EP_PRIVATE_READ_OPCODE 0x06 // CUnit to SCC EP Private Space Read Opcode
+#define PCH_SCC_EP_PRIVATE_WRITE_OPCODE 0x07 // CUnit to SCC EP Private Space Write Opcode
+
+#define R_PCH_SCC_EP_PCICFGCTR1 0x500 // PCI Configuration Control 1 - eMMC
+#define B_PCH_SCC_EP_PCICFGCTR1_ACPI_INT_EN1 BIT1 // ACPI Interrupt Enable
+#define B_PCH_SCC_EP_PCICFGCTR1_PCI_CFG_DIS1 BIT0 // PCI Configuration Space Disable
+
+#define R_PCH_SCC_EP_PCICFGCTR2 0x504 // PCI Configuration Control 2 - SD Card
+#define B_PCH_SCC_EP_PCICFGCTR2_ACPI_INT_EN1 BIT1 // ACPI Interrupt Enable
+#define B_PCH_SCC_EP_PCICFGCTR2_PCI_CFG_DIS1 BIT0 // PCI Configuration Space Disable
+
+#define R_PCH_SCC_EP_PCICFGCTR3 0x508 // PCI Configuration Control 3 - SDIO
+#define B_PCH_SCC_EP_PCICFGCTR3_ACPI_INT_EN1 BIT1 // ACPI Interrupt Enable
+#define B_PCH_SCC_EP_PCICFGCTR3_PCI_CFG_DIS1 BIT0 // PCI Configuration Space Disable
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSmbus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSmbus.h new file mode 100644 index 0000000000..4b522e1f40 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSmbus.h @@ -0,0 +1,229 @@ +/** @file
+ Register names for PCH Smbus Device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_SMBUS_H_
+#define _PCH_REGS_SMBUS_H_
+
+//
+// SMBus Controller Registers (D31:F3)
+//
+#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
+#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3
+
+#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID
+#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
+
+#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID
+#define V_PCH_SMBUS_DEVICE_ID 0x2292
+
+#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt
+#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable
+#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
+#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable
+#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable
+
+#define R_PCH_SMBUS_PCISTS 0x06 // Configuration status register
+#define B_PCH_SMBUS_PCISTS_DPE BIT15 // Detect Parity Error - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_SSE BIT14 // Signaled System Error - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_RMA BIT13 // Received Master Abort - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_RTA BIT12 // Received Target Abort - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_STA BIT11 // Signaled Target Abort - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_DEVT (BIT10 | BIT9) // Devsel Timing Status
+#define B_PCH_SMBUS_PCISTS_DPED BIT8 // Data Parity Error Detected - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_FB2BC BIT7 // Fast Back To Back Capable - reserved as '1'
+#define B_PCH_SMBUS_PCISTS_UDF BIT6 // User Defined Features - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_66MHZ_CAP BIT5 // 66 MHz Capable - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_CAP_LIST BIT4 // Capabilities List Indicator - reserved as '0'
+#define B_PCH_SMBUS_PCISTS_INTS BIT3 // Interrupt Status
+
+#define R_PCH_SMBUS_RID 0x08 // Revision ID
+#define B_PCH_SMBUS_RID 0xFF // Revision ID
+
+#define R_PCH_SMBUS_PRGIF 0x09 // Programming Interface
+#define B_PCH_SMBUS_PRGIF 0xFF // Programming Interface
+
+#define R_PCH_SMBUS_SCC 0x0A // Sub Class Code
+#define V_PCH_SMBUS_SCC 0x05 // A value of 05h indicates that this device is a SM Bus serial controller
+
+#define R_PCH_SMBUS_BCC 0x0B // Base Class Code
+#define V_PCH_SMBUS_BCC 0x0C // A value of 0Ch indicates that this device is a serial controller
+
+#define R_PCH_SMBUS_BAR0 0x10 // The memory bar low
+#define B_PCH_SMBUS_BAR0_BAR 0xFFFFFFE0 // Base Address
+#define B_PCH_SMBUS_BAR0_PREF BIT3 // Hardwired to 0. Indicated that SMBMBAR is not prefetchable
+#define B_PCH_SMBUS_BAR0_ADDRNG (BIT2 | BIT1)
+#define B_PCH_SMBUS_BAR0_MSI BIT0 // Memory Space Indicator
+
+#define R_PCH_SMBUS_BAR1 0x14 // The memory bar high
+#define B_PCH_SMBUS_BAR1_BAR 0xFFFFFFFF // Base Address
+
+#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar
+#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address
+#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator
+
+#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID
+#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID
+
+#define R_PCH_SMBUS_SID 0x2E // Subsystem ID
+#define B_PCH_SMBUS_SID 0xFFFF // Subsystem ID
+
+#define R_PCH_SMBUS_INT_LN 0x3C // Interrupt Line
+#define B_PCH_SMBUS_INT_LN 0xFF // Interrupt Line
+
+#define R_PCH_SMBUS_INT_PN 0x3D // Interrupt Pin
+#define B_PCH_SMBUS_INT_PN 0xFF // Interrupt Pin
+
+#define R_PCH_SMBUS_HOSTC 0x40 // Host Configuration Register
+#define B_PCH_SMBUS_HOSTC_SPD_WD BIT4 // SPD Write Disable
+#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 // Soft SMBus Reset
+#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 // I2C Enable Bit
+#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 // SMI Enable Bit
+#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 // Host Controller Enable Bit
+
+#define R_PCH_SMBUS_CAPID 0x50 // Power Management Capability ID
+#define B_PCH_SMBUS_CAPID_NIP 0xFF00 // Next Item Pointer
+#define B_PCH_SMBUS_CAPID_CID 0x00FF // Capability Identifier
+
+#define R_PCH_SMBUS_PC 0x52 // Power Management Capabilities
+#define B_PCH_SMBUS_PC_PMES 0xF800 // PME Support
+#define B_PCH_SMBUS_PC_D2S BIT10 // D2 Support
+#define B_PCH_SMBUS_PC_D1S BIT9 // D1 Support
+#define B_PCH_SMBUS_PC_AC (BIT8 | BIT7 | BIT6) // Aux Current
+#define B_PCH_SMBUS_PC_DSI BIT5 // DSI
+#define B_PCH_SMBUS_PC_PMEC BIT3 // PME Clock
+#define B_PCH_SMBUS_PC_VS (BIT2 | BIT1 | BIT0) // Version
+
+#define R_PCH_SMBUS_PMCSR 0x54 // Power Management Control / Status Register
+#define B_PCH_SMBUS_PMCSR_PMES BIT15 // PME Status
+#define B_PCH_SMBUS_PMCSR_DSCALE (BIT14 | BIT13) // Data Scale
+#define B_PCH_SMBUS_PMCSR_DSELECT 0x1E00 // Data Select
+#define B_PCH_SMBUS_PMCSR_PMEE BIT8 // PME Enable
+#define B_PCH_SMBUS_PMCSR_NSR BIT3 // No Soft Reset
+#define B_PCH_SMBUS_PMCSR_PS (BIT1 | BIT0) // Power State
+
+#define R_PCH_SMBUS_IOSF_ERR_CTRL 0xF0 // IOSF Error Control
+#define B_PCH_SMBUS_IOSF_ERR_CTRL_URD BIT0 // Unsupported Request Detected
+
+#define R_PCH_SMBUS_MANID 0xF8 // Manufacturer's ID Register
+#define B_PCH_SMBUS_MANID_DOTID 0x0F000000 // DOT ID
+#define B_PCH_SMBUS_MANID_SID 0x00FF0000 // Stepping ID
+#define B_PCH_SMBUS_MANID_MID 0x0000FF00 // Manufacturer ID
+#define B_PCH_SMBUS_MANID_PPID 0x000000FF // Process ID
+
+//
+// SMBus I/O Registers
+//
+#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W
+#define B_PCH_SMBUS_HSTS_ALL 0xFF
+#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status
+#define B_PCH_SMBUS_IUS BIT6 // In Use Status
+#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert
+#define B_PCH_SMBUS_FAIL BIT4 // Failed
+#define B_PCH_SMBUS_BERR BIT3 // Bus Error
+#define B_PCH_SMBUS_DERR BIT2 // Device Error
+#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
+#define B_PCH_SMBUS_INTR BIT1 // Interrupt
+#define B_PCH_SMBUS_HBSY BIT0 // Host Busy
+
+#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W
+#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable
+#define B_PCH_SMBUS_START BIT6 // Start
+#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte
+#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command
+#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process
+#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read
+#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block
+#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call
+#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data
+#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data
+#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte
+#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick
+#define B_PCH_SMBUS_KILL BIT1 // Kill
+#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable
+
+#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W
+#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted
+
+#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
+#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave
+#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write
+#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read
+#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write
+
+#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W
+#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W
+#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W
+#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W
+
+#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W
+#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)
+
+#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W
+
+#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC
+#define B_PCH_SMBUS_CRCE BIT0 // CRC Error
+
+#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W
+#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer
+#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC
+
+#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W
+#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
+#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported
+#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported
+
+#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W
+#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
+#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status
+#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status
+
+#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC
+#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status
+
+#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W
+#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
+#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
+#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable
+
+#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO
+#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address
+
+#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO
+#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSpi.h new file mode 100644 index 0000000000..52d26be29c --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsSpi.h @@ -0,0 +1,358 @@ +/** @file
+ Register names for PCH SPI device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_SPI_H_
+#define _PCH_REGS_SPI_H_
+
+//
+// SPI Host Interface Registers
+//
+#define R_PCH_SPI_BFPR 0x00 // BIOS Flash Primary Region Register (32bits)
+#define B_PCH_SPI_BFPR_PRL 0x7FFF0000 // BIOS Flash Primary Region Limit
+#define B_PCH_SPI_BFPR_PRB 0x7FFF // BIOS Flash Primary Region Base
+
+#define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits)
+#define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
+#define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid
+#define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
+#define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress
+#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size
+#define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes
+#define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes
+#define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes
+#define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes
+#define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log
+#define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error
+#define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done
+
+#define R_PCH_SPI_HSFC 0x06 // Hardware Sequencing Flash Control Register (16bits)
+#define B_PCH_SPI_HSFC_FSMIE BIT15 // Flash SPI SMI# Enable
+#define B_PCH_SPI_HSFC_FDBC_MASK 0x3F00 // Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define B_PCH_SPI_HSFC_FCYCLE_MASK 0x0006 // Flash Cycle.
+#define V_PCH_SPI_HSFC_FCYCLE_READ 0 // Flash Cycle Read
+#define V_PCH_SPI_HSFC_FCYCLE_WRITE 2 // Flash Cycle Write
+#define V_PCH_SPI_HSFC_FCYCLE_ERASE 3 // Flash Cycle Block Erase
+#define B_PCH_SPI_HSFC_FCYCLE_FGO BIT0 // Flash Cycle Go.
+
+#define R_PCH_SPI_FADDR 0x08 // SPI Flash Address
+#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF // SPI Flash Address Mask (0~26bit)
+
+#define R_PCH_SPI_FDATA00 0x10 // SPI Data 00 (32 bits)
+#define R_PCH_SPI_FDATA01 0x14 // SPI Data 01
+#define R_PCH_SPI_FDATA02 0x18 // SPI Data 02
+#define R_PCH_SPI_FDATA03 0x1C // SPI Data 03
+#define R_PCH_SPI_FDATA04 0x20 // SPI Data 04
+#define R_PCH_SPI_FDATA05 0x24 // SPI Data 05
+#define R_PCH_SPI_FDATA06 0x28 // SPI Data 06
+#define R_PCH_SPI_FDATA07 0x2C // SPI Data 07
+#define R_PCH_SPI_FDATA08 0x30 // SPI Data 08
+#define R_PCH_SPI_FDATA09 0x34 // SPI Data 09
+#define R_PCH_SPI_FDATA10 0x38 // SPI Data 10
+#define R_PCH_SPI_FDATA11 0x3C // SPI Data 11
+#define R_PCH_SPI_FDATA12 0x40 // SPI Data 12
+#define R_PCH_SPI_FDATA13 0x44 // SPI Data 13
+#define R_PCH_SPI_FDATA14 0x48 // SPI Data 14
+#define R_PCH_SPI_FDATA15 0x4C // SPI Data 15
+
+#define R_PCH_SPI_FRAP 0x50 // SPI Flash Regions Access Permissions Register
+#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 // Master Write Access Grant MASK
+#define B_PCH_SPI_FRAP_BMWAG_SEC BIT26 // Master Write Access Grant for SEC
+#define B_PCH_SPI_FRAP_BMWAG_BIOS BIT25 // Master Write Access Grant for Host CPU/BIOS
+#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 // Master Read Access Grant Grant MASK
+#define B_PCH_SPI_FRAP_BMRAG_SEC BIT18 // Master Read Access Grant for SEC
+#define B_PCH_SPI_FRAP_BMRAG_BIOS BIT17 // Master Read Access Grant for Host CPU/BIOS
+#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 // BIOS Region Write Access MASK
+#define B_PCH_SPI_FRAP_BRWA_SEC BIT10 // Region Write Access for Region2 SEC
+#define B_PCH_SPI_FRAP_BRWA_BIOS BIT9 // Region Write Access for Region1 BIOS
+#define B_PCH_SPI_FRAP_BRWA_FLASHD BIT8 // Region Write Access for Region0 Flash Descriptor
+#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF // BIOS Region Read Access MASK
+#define B_PCH_SPI_FRAP_BRRA_SEC BIT2 // Region Read Access for Region2 SEC
+#define B_PCH_SPI_FRAP_BRRA_BIOS BIT1 // Region Read Access for Region1 BIOS
+#define B_PCH_SPI_FRAP_BRRA_FLASHD BIT0 // Region Read Access for Region0 Flash Descriptor
+
+#define R_PCH_SPI_FREG0_FLASHD 0x54 // Flash Region 0 (Flash Descriptor) (32bits)
+#define B_PCH_SPI_FREG0_LIMIT_MASK 0x7FFF0000 // Size, [30:16] here represents limit[26:12]
+#define B_PCH_SPI_FREG0_BASE_MASK 0x00007FFF // Base, [14:0] here represents base [26:12]
+
+#define R_PCH_SPI_FREG1_BIOS 0x58 // Flash Region 1 (BIOS) (32bits)
+#define B_PCH_SPI_FREG1_LIMIT_MASK 0x7FFF0000 // Size, [30:16] here represents limit[26:12]
+#define B_PCH_SPI_FREG1_BASE_MASK 0x00007FFF // Base, [14:0] here represents base [26:12]
+
+#define R_PCH_SPI_FREG2_SEC 0x5C // Flash Region 2 (SEC) (32bits)
+#define B_PCH_SPI_FREG2_LIMIT_MASK 0x7FFF0000 // Size, [30:16] here represents limit[26:12]
+#define B_PCH_SPI_FREG2_BASE_MASK 0x00007FFF // Base, [14:0] here represents base [26:12]
+
+#define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 // Flash Region 4 (Platform Data) (32bits)
+#define B_PCH_SPI_FREG4_LIMIT_MASK 0x7FFF0000 // Size, [30:16] here represents limit[26:12]
+#define B_PCH_SPI_FREG4_BASE_MASK 0x00007FFF // Base, [14:0] here represents base [26:12]
+
+#define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register
+#define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR0_PRL_MASK 0x7FFF0000 // Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
+#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR0_PRB_MASK 0x00007FFF // Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
+
+#define R_PCH_SPI_PR1 0x78 // Protected Region 1 Register
+#define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR1_PRL_MASK 0x7FFF0000 // Protected Range Limit Mask
+#define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR1_PRB_MASK 0x00007FFF // Protected Range Base Mask
+
+#define R_PCH_SPI_PR2 0x7C // Protected Region 2 Register
+#define B_PCH_SPI_PR2_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR2_PRL_MASK 0x7FFF0000 // Protected Range Limit Mask
+#define B_PCH_SPI_PR2_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR2_PRB_MASK 0x00007FFF // Protected Range Base Mask
+
+#define R_PCH_SPI_PR3 0x80 // Protected Region 3 Register
+#define B_PCH_SPI_PR3_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR3_PRL_MASK 0x7FFF0000 // Protected Range Limit Mask
+#define B_PCH_SPI_PR3_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR3_PRB_MASK 0x00007FFF // Protected Range Base Mask
+
+#define R_PCH_SPI_PR4 0x84 // Protected Region 4 Register
+#define B_PCH_SPI_PR4_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR4_PRL_MASK 0x7FFF0000 // Protected Range Limit Mask
+#define B_PCH_SPI_PR4_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR4_PRB_MASK 0x00007FFF // Protected Range Base Mask
+
+#define R_PCH_SPI_SSFCS 0x90 // Software Sequencing Flash Control Status Register
+#define B_PCH_SPI_SSFCS_SCF_MASK (BIT26 | BIT25 | BIT24) // SPI Cycle Frequency
+#define V_PCH_SPI_SSFCS_SCF_20MHZ 0 // SPI Cycle Frequency = 20MHz
+#define V_PCH_SPI_SSFCS_SCF_33MHZ 1 // SPI Cycle Frequency = 33MHz
+#define V_PCH_SPI_SSFCS_SCF_50MHZ 4 // SPI Cycle Frequency = 50MHz
+#define B_PCH_SPI_SSFCS_SME BIT23 // SPI SMI# Enable
+#define B_PCH_SPI_SSFCS_DC BIT22 // SPI Data Cycle
+#define B_PCH_SPI_SSFCS_DBC_MASK 0x3F0000 // SPI Data Byte Count (value here + 1 = count)
+#define B_PCH_SPI_SSFCS_COP 0x7000 // Cycle Opcode Pointer
+#define B_PCH_SPI_SSFCS_SPOP BIT11 // Sequence Prefix Opcode Pointer
+#define B_PCH_SPI_SSFCS_ACS BIT10 // Atomic Cycle Sequence
+#define B_PCH_SPI_SSFCS_SCGO BIT9 // SPI Cycle Go
+#define B_PCH_SPI_SSFCS_FRS BIT7 // Fast Read Supported
+#define B_PCH_SPI_SSFCS_DOFRS BIT6 // Dual Output Fast Read Supported
+#define B_PCH_SPI_SSFCS_AEL BIT4 // Access Error Log
+#define B_PCH_SPI_SSFCS_FCERR BIT3 // Flash Cycle Error
+#define B_PCH_SPI_SSFCS_CDS BIT2 // Cycle Done Status
+#define B_PCH_SPI_SSFCS_SCIP BIT0 // SPI Cycle in Progress
+
+#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)
+#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
+#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
+
+#define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration
+#define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
+#define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
+#define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) // Opcode Type 5 Mask
+#define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask
+#define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) // Opcode Type 3 Mask
+#define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
+#define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask
+#define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask
+#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address
+#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address
+#define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type
+#define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type
+
+#define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits)
+#define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits)
+
+#define R_PCH_SPI_LOCK 0xA4 // Individual Lock
+#define B_PCH_SPI_LOCK_OPMENULOCKDN BIT9 // OPMENU Lock Down
+#define B_PCH_SPI_LOCK_OPTYPELOCKDN BIT8 // OPTYPE Lock Down
+#define B_PCH_SPI_LOCK_PREOPLOCKDN BIT7 // PREOP Lock Down
+#define B_PCH_SPI_LOCK_FREQLOCKDN BIT6 // SCF Lock Down
+#define B_PCH_SPI_LOCK_PR3LOCKDN BIT5 // PR3 Lock Down
+#define B_PCH_SPI_LOCK_PR2LOCKDN BIT4 // PR2 Lock Down
+#define B_PCH_SPI_LOCK_PR1LOCKDN BIT3 // PR1 Lock Down
+#define B_PCH_SPI_LOCK_PR0LOCKDN BIT2 // PR0 Lock Down
+#define B_PCH_SPI_LOCK_BMRAGLOCKDN BIT1 // BMRAG Lock Down
+#define B_PCH_SPI_LOCK_BMWAGLOCKDN BIT0 // BMWAG Lock Down
+
+#define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits)
+#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
+#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map
+#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component
+#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region
+#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master
+#define V_PCH_SPI_FDOC_FDSS_STRP 0x4000 // Soft Straps
+#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index
+
+#define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits)
+
+#define R_PCH_SPI_AFC 0xC0 // Additional Flash Control Register
+#define B_PCH_SPI_AFC_RRWSP (BIT7 | BIT6 | BIT5 | BIT4) // Reserved RW Scratch Pad
+#define B_PCH_SPI_AFC_SPFP BIT3 // Stop Prefetch on Flush Pending
+#define B_PCH_SPI_AFC_INF_DCGE (BIT2 | BIT1) // Flash Controller Interface Dynamic Clock Gating Enable
+#define B_PCH_SPI_AFC_CORE_DCGE BIT0 // Flash Core Dynamic Clock Gating Enable
+
+#define R_PCH_SPI_VSCC0 0xC4 // Lower Vendor Specific Component Capabilities Register (32 bits)
+#define B_PCH_SPI_VSCC0_CPPTV BIT31 // Component Property Parameter Table Valid
+#define B_PCH_SPI_VSCC0_VCL BIT23 // Vendor Component Lock
+#define B_PCH_SPI_VSCC0_CAP_MASK 0x0000FFFF // Capabilities Mask
+#define B_PCH_SPI_VSCC0_EO_MASK 0x0000FF00 // Erase Opcode
+#define B_PCH_SPI_VSCC0_QER (BIT7 | BIT6 | BIT5) // Quad Enable Requirements
+#define B_PCH_SPI_VSCC0_WEWS BIT4 // Write Enable on Write Status
+#define B_PCH_SPI_VSCC0_WSR BIT3 // Write Status Required
+#define B_PCH_SPI_VSCC0_WG_64B BIT2 // Write Granularity, 0: 1 Byte; 1: 64 Bytes
+#define B_PCH_SPI_VSCC0_BSES_MASK (BIT1 | BIT0) // Block/Sector Erase Size
+#define V_PCH_SPI_VSCC0_BSES_256B 0x0 // Block/Sector Erase Size = 256 Bytes
+#define V_PCH_SPI_VSCC0_BSES_4K 0x1 // Block/Sector Erase Size = 4K Bytes
+#define V_PCH_SPI_VSCC0_BSES_8K 0x2 // Block/Sector Erase Size = 8K Bytes
+#define V_PCH_SPI_VSCC0_BSES_64K 0x3 // Block/Sector Erase Size = 64K Bytes
+
+#define R_PCH_SPI_VSCC1 0xC8 // Upper Vendor Specific Component Capabilities Register (32 bits)
+#define B_PCH_SPI_VSCC1_CPPTV BIT31 // Component Property Parameter Table Valid
+#define B_PCH_SPI_VSCC1_CAP_MASK 0x0000FFFF // Capabilities Mask
+#define B_PCH_SPI_VSCC1_EO_MASK 0x0000FF00 // Erase Opcode
+#define B_PCH_SPI_VSCC1_QER (BIT7 | BIT6 | BIT5) // Quad Enable Requirements
+#define B_PCH_SPI_VSCC1_WEWS BIT4 // Write Enable on Write Status
+#define B_PCH_SPI_VSCC1_WSR BIT3 // Write Status Required
+#define B_PCH_SPI_VSCC1_WG_64B BIT2 // Write Granularity, 0: 1 Byte; 1: 64 Bytes
+#define B_PCH_SPI_VSCC1_BSES_MASK (BIT1 | BIT0) // Block/Sector Erase Size
+#define V_PCH_SPI_VSCC1_BSES_256B 0x0 // Block/Sector Erase Size = 256 Bytes
+#define V_PCH_SPI_VSCC1_BSES_4K 0x1 // Block/Sector Erase Size = 4K Bytes
+#define V_PCH_SPI_VSCC1_BSES_8K 0x2 // Block/Sector Erase Size = 8K Bytes
+#define V_PCH_SPI_VSCC1_BSES_64K 0x3 // Block/Sector Erase Size = 64K Bytes
+
+#define R_PCH_SPI_PTINX 0xCC // Parameter Table Index
+#define B_PCH_SPI_PTINX_SPT (BIT15 | BIT14) // Supported Parameter Table
+#define N_PCH_SPI_PTINX_SPT 14
+#define V_PCH_SPI_PTINX_SPT_CPT0 0x0 // Component 0 Property Parameter Table
+#define V_PCH_SPI_PTINX_SPT_CPT1 0x1 // Component 1 Property Parameter Table
+#define B_PCH_SPI_PTINX_HORD (BIT13 | BIT12) // Header or Data
+#define N_PCH_SPI_PTINX_HORD 12
+#define V_PCH_SPI_PTINX_HORD_SFDP 0x0 // SFDP Header
+#define V_PCH_SPI_PTINX_HORD_PT 0x1 // Parameter Table Header
+#define V_PCH_SPI_PTINX_HORD_DATA 0x2 // Data
+#define B_PCH_SPI_PTINX_PTDWI 0xFFC // Parameter Table DW Index
+
+#define R_PCH_SPI_PTDATA 0xD0 // Parameter Table Data
+
+#define R_PCH_SPI_FPB 0xD4 // Flash Partition Boundary
+#define B_PCH_SPI_FPB_FPBA_MASK 0x00001FFF // Flash Partition Boundary Address Mask, reflecting FPBA[24:12]
+
+#define R_PCH_SPI_SCS 0xF8 // SMI Control Status Register
+#define S_PCH_SPI_SCS 1
+#define B_PCH_SPI_SCS_SMIWPEN BIT7 // SMI WPD Enable
+#define B_PCH_SPI_SCS_SMIWPST BIT6 // SMI WPD Status
+#define N_PCH_SPI_SCS_SMIWPEN 7
+#define N_PCH_SPI_SCS_SMIWPST 6
+
+#define R_PCH_SPI_BCR 0xFC // BIOS Control Register
+#define S_PCH_SPI_BCR 1
+#define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable
+#define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
+#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable
+#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable
+#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable
+#define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)
+#define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD)
+#define N_PCH_SPI_BCR_BLE 1
+#define N_PCH_SPI_BCR_BIOSWE 0
+
+#define R_PCH_SPI_TCGC 0x100 // Trunk Clock Gating Control
+#define B_PCH_SPI_TCGC_FCGDIS BIT10 // Functional Clock Gating Disable
+#define B_PCH_SPI_TCGC_SBCGCDEF BIT9 // Sideband Control Gating Clock Defeature
+#define B_PCH_SPI_TCGC_SBCGEN BIT8 // Sideband Control Gating Clock Enable
+#define B_PCH_SPI_TCGC_SBCGCNT 0xFF // Sideband Control Gating Clock Counter
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature
+#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
+
+#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04 // Flash MAP 0
+#define B_PCH_SPI_FDBAR_NR 0x07000000 // Number Of Regions
+#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 // Flash Region Base Address
+#define B_PCH_SPI_FDBAR_NC 0x00000300 // Number Of Components
+#define V_PCH_SPI_FDBAR_NC_2 0x00000100
+#define V_PCH_SPI_FDBAR_NC_1 0x00000000
+#define N_PCH_SPI_FDBAR_NC 0x08 // Number Of Components
+#define B_PCH_SPI_FDBAR_FCBA 0x000000FF // Flash Component Base Address
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_PCH_SPI_FCBA_FLCOMP 0x00 // Flash Components Register
+#define B_PCH_SPI_FLCOMP_DOFRS BIT30 // Dual Output Fast Read Support
+#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) // Read ID and Read Status Clock Frequency
+#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) // Write and Erase Clock Frequency
+#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) // Fast Read Clock Frequency
+#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 // Fast Read Support.
+#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) // Read Clock Frequency.
+#define V_PCH_SPI_FLCOMP_FREQ_20MHZ 0x00
+#define B_PCH_SPI_FLCOMP_COMP2_MASK 0x38 // Flash Component 2 Density
+#define V_PCH_SPI_FLCOMP_COMP2_512KB 0x00
+#define V_PCH_SPI_FLCOMP_COMP2_1MB 0x08
+#define V_PCH_SPI_FLCOMP_COMP2_2MB 0x10
+#define V_PCH_SPI_FLCOMP_COMP2_4MB 0x18
+#define V_PCH_SPI_FLCOMP_COMP2_8MB 0x20
+#define V_PCH_SPI_FLCOMP_COMP2_16MB 0x28
+#define B_PCH_SPI_FLCOMP_COMP1_MASK 0x07 // Flash Component 1 Density
+#define V_PCH_SPI_FLCOMP_COMP1_512KB 0x00
+#define V_PCH_SPI_FLCOMP_COMP1_1MB 0x01
+#define V_PCH_SPI_FLCOMP_COMP1_2MB 0x02
+#define V_PCH_SPI_FLCOMP_COMP1_4MB 0x03
+#define V_PCH_SPI_FLCOMP_COMP1_8MB 0x04
+#define V_PCH_SPI_FLCOMP_COMP1_16MB 0x05
+#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000
+
+//
+// Flash Soft Strap Base Address (FISBA) from Flash Region 0
+//
+
+
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_PCH_SPI_FLASH_UMAP1 0xEFC // Flash Upper Map 1
+#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 // VSCC Table Length
+#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF // VSCC Table Base Address
+
+#define R_PCH_SPI_VTBA_JID0 0x00 // JEDEC-ID 0 Register
+#define S_PCH_SPI_VTBA_JID0 4
+#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000 // SPI Component Device ID 1
+#define N_PCH_SPI_VTBA_JID0_DID1 0x10
+#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00 // SPI Component Device ID 0
+#define N_PCH_SPI_VTBA_JID0_DID0 0x08
+#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF // SPI Component Vendor ID
+
+#define R_PCH_SPI_VTBA_VSCC0 0x04 // Vendor Specific Component Capabilities 0
+#define S_PCH_SPI_VTBA_VSCC0 4
+#define B_PCH_SPI_VTBA_VSCC0_CAPS 0x0000FFFF
+#define B_PCH_SPI_VTBA_VSCC0_EO 0x0000FF00 // Erase Opcode
+#define B_PCH_SPI_VTBA_VSCC0_WEWS BIT4 // Write Enable on Write Status
+#define B_PCH_SPI_VTBA_VSCC0_WSR BIT3 // Write Status Required
+#define B_PCH_SPI_VTBA_VSCC0_WG BIT2 // Write Granularity
+#define B_PCH_SPI_VTBA_VSCC0_BES (BIT1 | BIT0) // Block / Sector Erase Size
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsUsb.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsUsb.h new file mode 100644 index 0000000000..55b14671af --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/PchRegs/PchRegsUsb.h @@ -0,0 +1,409 @@ +/** @file
+ Register names for PCH USB devices.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, PCH registers are denoted by "_PCH_" in register names
+ - Registers / bits that are different between PCH generations are denoted by
+ "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CHV_"
+ - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_REGS_USB_H_
+#define _PCH_REGS_USB_H_
+
+//
+// USB Definitions
+//
+#define PCH_USB_MAX_PHYSICAL_PORTS 5
+#define PCH_HSIC_MAX_PORTS 2
+#define PCH_SSIC_MAX_PORTS 2
+#define PCH_XHCI_MAX_USB3_PORTS 4
+
+
+//
+// USB3 (XHCI) related definitions
+//
+typedef enum {
+ PchXhci1 = 0,
+ PchXhciControllerMax
+} PCH_USB30_CONTROLLER_TYPE;
+
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+//
+// XHCI PCI Config Space registers
+//
+#define R_PCH_XHCI_VENDOR_ID 0x00 // Vendor ID
+#define B_PCH_XHCI_VENDOR_ID 0xFFFF
+
+#define R_PCH_XHCI_DEVICE_ID 0x02 // Device ID
+#define B_PCH_XHCI_DEVICE_ID 0xFFFF
+#define V_PCH_XHCI_DEVICE_ID_0 0x22B5
+
+#define R_PCH_XHCI_COMMAND_REGISTER 0x04 // Command
+#define B_PCH_XHCI_COMMAND_ID BIT10 // Interrupt Disable
+#define B_PCH_XHCI_COMMAND_FBE BIT9 // Fast Back to Back Enable
+#define B_PCH_XHCI_COMMAND_SERR BIT8 // SERR# Enable
+#define B_PCH_XHCI_COMMAND_WCC BIT7 // Wait Cycle Control
+#define B_PCH_XHCI_COMMAND_PER BIT6 // Parity Error Response
+#define B_PCH_XHCI_COMMAND_VPS BIT5 // VGA Palette Snoop
+#define B_PCH_XHCI_COMMAND_MWI BIT4 // Memory Write Invalidate
+#define B_PCH_XHCI_COMMAND_SCE BIT3 // Special Cycle Enable
+#define B_PCH_XHCI_COMMAND_BME BIT2 // Bus Master Enable
+#define B_PCH_XHCI_COMMAND_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_XHCI_MEM_BASE 0x10 // Memory Base Address
+#define B_PCH_XHCI_MEM_BASE_BA 0xFFFFFFFFFFFF0000 // Base Address
+#define V_PCH_XHCI_MEM_LENGTH 0x10000 // 64 KB of Memory Length
+#define N_PCH_XHCI_MEM_ALIGN 16 // Memory Space Alignment
+#define B_PCH_XHCI_MEM_BASE_PREF BIT3 // Prefetchable
+#define B_PCH_XHCI_MEM_BASE_TYPE (BIT2 | BIT1) // Type
+#define B_PCH_XHCI_MEM_BASE_RTE BIT0 // Resource Type Indicator
+
+#define R_PCH_XHCI_SVID 0x2C
+#define B_PCH_XHCI_SVID 0xFFFF
+
+#define R_PCH_XHCI_SID 0x2E
+#define B_PCH_XHCI_SID 0xFFFF
+
+#define R_PCH_XHCI_XHCC1 0x40 // XHC System Bus Configuration 1
+#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 // Access Control
+#define B_PCH_XHCI_XHCC1_RMTASERR BIT24
+#define B_PCH_XHCI_XHCC1_URD BIT23
+#define B_PCH_XHCI_XHCC1_URRE BIT22
+#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0
+#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21)
+#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19)
+#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 // XHC Initiated L1 Enable
+#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 // D3 Initiated L1 Enable
+#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) // Periodic Complete Pre Wake Time
+#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 // SW Assisted xHC Idle
+#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) // L23 to Host Reset Acknowledge Wait Count
+#define V_PCH_XHCI_XHCC1_L23HRAWC_DIS 0
+#define V_PCH_XHCI_XHCC1_L23HRAWC_128 (BIT8)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_256 (BIT9)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_512 (BIT9 | BIT8)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_1024 (BIT10)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_2048 (BIT10 | BIT8)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_4096 (BIT10 | BIT9)
+#define V_PCH_XHCI_XHCC1_L23HRAWC_131072 (BIT10 | BIT9 | BIT8)
+#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) // Upstream Type Arbiter Grant Count Posted
+#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) // Upstream Type Arbiter Grant Count Non Posted
+#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) // Upstream Type Arbiter Grant Count Completion
+#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) // Upstream Type Arbiter Grant Count
+
+#define R_PCH_XHCI_XHCC2 0x44 // XHC System Bus Configuration 2
+#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 // OC Configuration Done
+#define B_PCH_XHCI_XHCC2_DREQBCC BIT25 // DMA Request Boundary Crossing Control
+#define B_PCH_XHCI_XHCC2_IDMARRSC (BIT24 | BIT23 | BIT22) // IDMA Read Request Size Control
+#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT21 // XHC Upstream Read Relaxed Ordering Enable
+#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT20 // IOSF Sideband Register Access Disable
+#define B_PCH_XHCI_XHCC2_UNPPA 0xFC000 // Upstream Non-Posted Pre-Allocation
+#define B_PCH_XHCI_XHCC2_SWAXHCIP (BIT13 | BIT12) // SW Assisted xHC Idle Policy
+#define B_PCH_XHCI_XHCC2_RAWDD BIT11 // MMIO Read After MMIO Write Delay Disable
+#define B_PCH_XHCI_XHCC2_WAWDE BIT10 // MMIO Write After MMIO Write Delay Enable
+#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) // SW Assisted Cx Inhibit
+#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) // SW Assisted DMI L1 Inhibit
+#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) // L1 Force P2 clock Gating Wait Count
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_DIS 0
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_128 (BIT3)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_256 (BIT4)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_512 (BIT4 | BIT3)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_1024 (BIT5)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_2048 (BIT5 | BIT3)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_4096 (BIT5 | BIT4)
+#define V_PCH_XHCI_XHCC2_L1FP2CGWC_131072 (BIT5 | BIT4 | BIT3)
+#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) // Read Request Size Control
+#define V_PCH_XHCI_XHCC2_RDREQSZCTRL_128 0
+#define V_PCH_XHCI_XHCC2_RDREQSZCTRL_256 (BIT0)
+#define V_PCH_XHCI_XHCC2_RDREQSZCTRL_512 (BIT1)
+#define V_PCH_XHCI_XHCC2_RDREQSZCTRL_64 (BIT2 | BIT1 | BIT0)
+
+#define R_PCH_XHCI_AUDSYNC 0x58 // Audio Time Synchronization
+#define B_PCH_XHCI_AUDSYNC_CMF1 0x3FFF0000
+#define B_PCH_XHCI_AUDSYNC_CMFB 0x1FFF
+
+#define R_PCH_XHCI_USB_RELNUM 0x60 // Serial Bus Release Number
+#define B_PCH_XHCI_USB_RELNUM 0xFF
+
+#define R_PCH_XHCI_FL_ADJ 0x61 // Frame Length Adjustment
+#define B_PCH_XHCI_FL_ADJ 0x3F
+
+#define R_PCH_XHCI_PWR_CAPID 0x70 // PCI Power Management Capability ID
+#define B_PCH_XHCI_PWR_CAPID 0xFF
+
+#define R_PCH_XHCI_NXT_PTR1 0x71 // Next Item Pointer #1
+#define B_PCH_XHCI_NXT_PTR1 0xFF
+
+#define R_PCH_XHCI_PWR_CAP 0x72 // Power Management Capabilities
+#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800
+#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10
+#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9
+#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6)
+#define B_PCH_XHCI_PWR_CAP_DSI BIT5
+#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3
+#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0)
+
+#define R_PCH_XHCI_PWR_CNTL_STS 0x74 // Power Management Control/Status
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
+#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State
+#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
+
+#define R_PCH_XHCI_FUS 0x94 // Fuse and Strap
+#define B_PCH_XHCI_FUS_USH_DEVID (BIT13 | BIT12 | BIT11) // USH Device ID
+#define B_PCH_XHCI_FUS_XDD_EN BIT10 // Debug Device Enable
+#define B_PCH_XHCI_FUS_SRAMPWRGTDIS BIT9 // SRAM Power Gating Disable
+#define B_PCH_XHCI_FUS_USB2PLLSDIS BIT8 // USB2 PLL Shutdown Disable
+#define B_PCH_XHCI_FUS_USBIOPMDIS BIT7 // USB I/O Power Management Disable
+#define B_PCH_XHCI_FUS_XHCDCGDIS BIT6 // XHC Dynamic Clock Gating Disable
+#define B_PCH_XHCI_FUS_USBR BIT5 // USBr Disable
+#define V_PCH_XHCI_FUS_USBR_EN 0
+#define V_PCH_XHCI_FUS_USBR_DIS BIT5
+#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) // SS Port Count
+#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3)
+#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4)
+#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3)
+#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) // HS Port Count
+#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1)
+#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2)
+#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1)
+#define V_PCH_XHCI_FUS_SSPRTCNT_00B_CNT 6
+#define V_PCH_XHCI_FUS_SSPRTCNT_01B_CNT 4
+#define V_PCH_XHCI_FUS_SSPRTCNT_10B_CNT 2
+#define V_PCH_XHCI_FUS_SSPRTCNT_11B_CNT 0
+#define V_PCH_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F
+#define V_PCH_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F
+#define V_PCH_XHCI_FUS_SSPRTCNT_10B_MASK 0x03
+#define V_PCH_XHCI_FUS_SSPRTCNT_11B_MASK 0x00
+#define V_PCH_XHCI_FUS_HSPRTCNT_00B_CNT 14
+#define V_PCH_XHCI_FUS_HSPRTCNT_01B_CNT 12
+#define V_PCH_XHCI_FUS_HSPRTCNT_10B_CNT 10
+#define V_PCH_XHCI_FUS_HSPRTCNT_11B_CNT 8
+#define V_PCH_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF
+#define V_PCH_XHCI_FUS_HSPRTCNT_01B_MASK 0x0FFF
+#define V_PCH_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF
+#define V_PCH_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF
+#define B_PCH_XHCI_FUS_XHCFD BIT0 // XHCI Function Disable
+
+#define R_PCH_XHCI_U2OCM1 0xB0 // XHCI USB2 Overcurrent Pin Mapping 1
+#define B_PCH_XHCI_U2OCM1_PORT_MAP 0x1F
+
+#define R_PCH_XHCI_U2OCM2 0xB4 // XHCI USB2 Overcurrent Pin Mapping 2
+#define B_PCH_XHCI_U2OCM2_PORT_MAP 0x1F
+
+#define R_PCH_XHCI_U3OCM1 0xD0 // XHCI USB3 Overcurrent Pin Mapping 1
+#define B_PCH_XHCI_U3OCM1_PORT_MAP 0x0F
+
+#define R_PCH_XHCI_U3OCM2 0xD4 // XHCI USB3 Overcurrent Pin Mapping 2
+#define B_PCH_XHCI_U3OCM2_PORT_MAP 0x0F
+
+//
+// xHCI MMIO registers
+//
+
+//
+// 0x00 - 0x1F - Capability Registers
+//
+#define R_PCH_XHCI_CAPLENGTH 0x00 // Capability Registers Length
+
+#define R_PCH_XHCI_HCIVERSION 0x02 // Host Controller Interface Version Number
+
+#define R_PCH_XHCI_HCSPARAMS1 0x04 // Structural Parameters 1
+#define B_PCH_XHCI_HCSPARAMS1_MAXPORTS 0xFF000000 // Number of Ports
+#define B_PCH_XHCI_HCSPARAMS1_MAXINTRS 0x7FF00 // Number of Interrupters
+#define B_PCH_XHCI_HCSPARAMS1_MAXSLOTS 0xFF // Number of Device Slots
+
+#define R_PCH_XHCI_HCSPARAMS2 0x08 // Structural Parameters 2
+#define B_PCH_XHCI_HCSPARAMS2_MSB 0xF8000000 // Max Scratchpad Buffers
+#define B_PCH_XHCI_HCSPARAMS2_ERSTMAX 0xF0 // Event Ring Segment Table Max
+#define B_PCH_XHCI_HCSPARAMS2_IST 0x0F // Isochronous Scheduling Threshold
+
+#define R_PCH_XHCI_HCSPARAMS3 0x0C // Structural Parameters 3
+#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 // U2 Device Exit Latency
+#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x000000FF // U1 Device Exit Latency
+
+#define R_PCH_XHCI_HCCPARAMS 0x10 // Capability Parameters
+#define B_PCH_XHCI_HCCPARAMS_XECP 0xFFFF0000 // xHCI Extended Capabilities Pointer
+#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE (BIT15 | BIT14 | BIT13 | BIT12) // Maximum Primary Stream Array Size
+#define B_PCH_XHCI_HCCPARAMS_CFC BIT11 // Contiguous Frame ID Capability
+#define B_PCH_XHCI_HCCPARAMS_SEC BIT10 // Stopped EDLTA Capability
+#define B_PCH_XHCI_HCCPARAMS_SPC BIT9 // Stopped Short Packet Capability
+#define B_PCH_XHCI_HCCPARAMS_PAE BIT8 // Parst All Event Data
+#define B_PCH_XHCI_HCCPARAMS_NSS BIT7 // No Secondary SID Support
+#define B_PCH_XHCI_HCCPARAMS_LTC BIT6 // Latency Tolerance Messaging Capability
+#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 // Light HC Reset Capability
+#define B_PCH_XHCI_HCCPARAMS_PIND BIT4 // Port Indicators
+#define B_PCH_XHCI_HCCPARAMS_PPC BIT3 // Port Power Control
+#define B_PCH_XHCI_HCCPARAMS_CSZ BIT2 // Context Size
+#define B_PCH_XHCI_HCCPARAMS_BNC BIT1 // BW Negotiation Capability
+#define B_PCH_XHCI_HCCPARAMS_AC64 BIT0 // 64-bit Addressing Capability
+
+#define R_PCH_XHCI_DBOFF 0x14 // Doorbell Offset
+#define B_PCH_XHCI_DBOFF_DBAO 0xFFFFFFFC // Doorbell Array Offset
+
+#define R_PCH_XHCI_RTSOFF 0x18 // Runtime Register Space Offset
+#define B_PCH_XHCI_RTSOFF_RTRSO 0xFFFFFFE0 // Runtime Register Space Offset
+
+//
+// 0x80 - 0xBF - Operational Registers
+//
+#define R_PCH_XHCI_USBCMD 0x80 // USB Command
+#define B_PCH_XHCI_USBCMD_EU3S BIT11 // Enable U3 MFINDEX Stop
+#define B_PCH_XHCI_USBCMD_EWE BIT10 // Enable Wrap Event
+#define B_PCH_XHCI_USBCMD_CRS BIT9 // Controller Restore State
+#define B_PCH_XHCI_USBCMD_CSS BIT8 // Controller Save State
+#define B_PCH_XHCI_USBCMD_LHCRST BIT7 // Light Host Controller Reset
+#define B_PCH_XHCI_USBCMD_HSEE BIT3 // Host System Error Enable
+#define B_PCH_XHCI_USBCMD_INTE BIT2 // Interrupter Enable
+#define B_PCH_XHCI_USBCMD_HCRST BIT1 // Host Controller Reset
+#define B_PCH_XHCI_USBCMD_RS BIT0 // Run/Stop
+
+#define R_PCH_XHCI_USBSTS 0x84 // USB Status
+#define B_PCH_XHCI_USBSTS_HCE BIT12 // Host Controller Error
+#define B_PCH_XHCI_USBSTS_CNR BIT11 // Controller Not Ready
+#define B_PCH_XHCI_USBSTS_SRE BIT10 // Save / Restore Error
+#define B_PCH_XHCI_USBSTS_RSS BIT9 // Restore State Status
+#define B_PCH_XHCI_USBSTS_SSS BIT8 // Save State Status
+#define B_PCH_XHCI_USBSTS_PCD BIT4 // Port Change Detect
+#define B_PCH_XHCI_USBSTS_EINT BIT3 // Event Interrupt
+#define B_PCH_XHCI_USBSTS_HSE BIT2 // Host System Error
+#define B_PCH_XHCI_USBSTS_HCH BIT0 // HC Halted
+
+//
+// 0x480 - 0x54F - Port Status and Control Registers
+//
+#define R_PCH_XHCI_PORTSC01USB2 0x480
+#define R_PCH_XHCI_PORTSC02USB2 0x490
+#define R_PCH_XHCI_PORTSC03USB2 0x4A0
+#define R_PCH_XHCI_PORTSC04USB2 0x4B0
+#define R_PCH_XHCI_PORTSC05USB2 0x4C0
+#define R_PCH_XHCI_PORTSC06USB2 0x4D0
+#define R_PCH_XHCI_PORTSC07USB2 0x4E0
+#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 // Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_DR BIT30 // Device Removable
+#define B_PCH_XHCI_PORTSCXUSB2_WOE BIT27 // Wake on Over-Current Enable
+#define B_PCH_XHCI_PORTSCXUSB2_WDE BIT26 // Wake on Disconnect Enable
+#define B_PCH_XHCI_PORTSCXUSB2_WCE BIT25 // Wake on Connect Enable
+#define B_PCH_XHCI_PORTSCXUSB2_CAS BIT24 // Cold Attach Status
+#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 // Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 // Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 // Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 // Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 // Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 // Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 // Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 // Port Link State Write Strobe
+#define B_PCH_XHCI_PORTSCXUSB2_PIC (BIT15 | BIT14) // Port Indicator Control
+#define B_PCH_XHCI_PORTSCXUSB2_PS (BIT13 | BIT12 | BIT11 | BIT10) // Port Speed
+#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 // Port Power
+#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT8 | BIT7 | BIT6 | BIT5) // Port Link State
+#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 // Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_OCA BIT3 // Over-Current Active
+#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 // Port Enabled Disabled
+#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 // Current Connect Status
+
+#define R_PCH_XHCI_PORTSC08USB3 0x4F0
+#define R_PCH_XHCI_PORTSC09USB3 0x500
+#define R_PCH_XHCI_PORTSC10USB3 0x510
+#define R_PCH_XHCI_PORTSC11USB3 0x520
+#define R_PCH_XHCI_PORTSC12USB3 0x530
+#define R_PCH_XHCI_PORTSC13USB3 0x540
+#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 // Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 // Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 // Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 // Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 // Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 // Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 // Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 // Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 // Port Power
+#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 // Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 // Port Enabled / Disabled
+
+#define R_PCH_XHCI_USB2PDO 0x84F8 // USB2 Port Disable Override
+#define B_PCH_XHCI_USB2PDO_MASK 0x7F
+#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0
+
+#define R_PCH_XHCI_USB3PDO 0x84FC // USB3 Port Disable Override
+#define B_PCH_XHCI_USB3PDO_MASK 0x3F
+#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0
+
+//
+// USB3 OTG PCI Config Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_OTG 22
+#define PCI_FUNCTION_NUMBER_PCH_OTG 0
+
+#define R_PCH_OTG_DEVVENDID 0x00 // Vendor ID
+#define V_PCH_USB_DEVVENDID_VID V_PCH_INTEL_VENDOR_ID
+
+#define R_PCH_OTG_STSCMD 0x04 // Command Status
+#define B_PCH_OTG_STSCMD_INTR_DIS BIT10 // Interrupt Disable
+#define B_PCH_OTG_STSCMD_BME BIT2 // Bus Master Enable
+#define B_PCH_OTG_STSCMD_MSE BIT1 // Memory Space Enable
+
+#define R_PCH_OTG_BAR0 0x10 // BAR 0
+#define B_PCH_OTG_BAR0_BA 0xFFE00000 // Base Address
+#define V_PCH_OTG_BAR0_SIZE 0x200000
+#define N_PCH_OTG_BAR0_ALIGNMENT 21
+#define B_PCH_OTG_BAR0_PREF BIT3 // Prefetchable
+#define B_PCH_OTG_BAR0_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_OTG_BAR0_SPTYP BIT0 // Space Type (Memory)
+
+#define R_PCH_OTG_BAR1 0x18 // BAR 1
+#define B_PCH_OTG_BAR1_BA 0xFFFFF000 // Base Address
+#define B_PCH_OTG_BAR1_PREF BIT3 // Prefetchable
+#define B_PCH_OTG_BAR1_ADDRNG (BIT2 | BIT1) // Address Range
+#define B_PCH_OTG_BAR1_SPTYP BIT0 // Space Type (Memory)
+#define V_PCH_OTG_BAR1_SIZE (1 << 12)
+
+#define R_PCH_OTG_SSID 0x2C // Sub System ID
+#define B_PCH_OTG_SSID_SID 0xFFFF0000 // Sub System ID
+#define B_PCH_OTG_SSID_SVID 0x0000FFFF // Sub System Vendor ID
+
+#define R_PCH_OTG_PMECTLSTS 0x84 // PME Control Status
+#define B_PCH_OTG_PMECTLSTS_POWERSTATE (BIT1 | BIT0) // Power State
+
+#define R_PCH_OTG_GEN_REGRW1 0xA0
+#define B_PCH_OTG_GEN_REGRW1_PPSR (BIT1 | BIT0) // PM Power State Request
+
+#define R_PCH_OTG_GEN_INPUT_REGRW 0xC0
+#define B_PCH_OTG_GEN_INPUT_REGRW_CPSU3 (BIT11 | BIT10) // Current Power State u3pmu
+#define B_PCH_OTG_GEN_INPUT_REGRW_CPSU2 (BIT9 | BIT8) // Current Power State u2pmu
+
+
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/DeviceRecoveryModulePei.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/DeviceRecoveryModulePei.h new file mode 100644 index 0000000000..dc51d95424 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/DeviceRecoveryModulePei.h @@ -0,0 +1,144 @@ +/** @file
+ This file declares the Device Recovery Module PPI.
+
+ The interface of this PPI does the following:
+ - Reports the number of recovery DXE capsules that exist on the associated device(s)
+ - Finds the requested firmware binary capsule
+ - Loads that capsule into memory
+
+ A device can be either a group of devices, such as a block device, or an individual device.
+ The module determines the internal search order, with capsule number 1 as the highest load
+ priority and number N as the lowest priority.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_DEVICE_RECOVERY_MODULE_PPI_H_
+#define _PEI_DEVICE_RECOVERY_MODULE_PPI_H_
+
+#define EFI_PEI_DEVICE_RECOVERY_MODULE_PPI_GUID \
+ { \
+ 0x0DE2CE25, 0x446A, 0x45a7, {0xBF, 0xC9, 0x37, 0xDA, 0x26, 0x34, 0x4B, 0x37 } \
+ }
+
+typedef struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI;
+
+/**
+ Returns the number of DXE capsules residing on the device.
+
+ This function searches for DXE capsules from the associated device and returns
+ the number and maximum size in bytes of the capsules discovered. Entry 1 is
+ assumed to be the highest load priority and entry N is assumed to be the lowest
+ priority.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[out] NumberRecoveryCapsules Pointer to a caller-allocated UINTN. On
+ output, *NumberRecoveryCapsules contains
+ the number of recovery capsule images
+ available for retrieval from this PEIM
+ instance.
+
+ @retval EFI_SUCCESS One or more capsules were discovered.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ OUT UINTN *NumberRecoveryCapsules,
+ IN CHAR16 *FileName
+ );
+
+/**
+ Returns the size and type of the requested recovery capsule.
+
+ This function gets the size and type of the capsule specified by CapsuleInstance.
+
+ @param[in] PeiServices General-purpose services that are available to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[in] CapsuleInstance Specifies for which capsule instance to retrieve
+ the information. This parameter must be between
+ one and the value returned by GetNumberRecoveryCapsules()
+ in NumberRecoveryCapsules.
+ @param[out] Size A pointer to a caller-allocated UINTN in which
+ the size of the requested recovery module is
+ returned.
+ @param[out] CapsuleType A pointer to a caller-allocated EFI_GUID in which
+ the type of the requested recovery capsule is
+ returned. The semantic meaning of the value
+ returned is defined by the implementation.
+
+ @retval EFI_SUCCESS One or more capsules were discovered.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ IN UINTN CapsuleInstance,
+ OUT UINTN *Size,
+ OUT EFI_GUID *CapsuleType,
+ IN CHAR16 *FileName
+ );
+
+/**
+ Loads a DXE capsule from some media into memory.
+
+ This function, by whatever mechanism, retrieves a DXE capsule from some device
+ and loads it into memory. Note that the published interface is device neutral.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[in] CapsuleInstance Specifies which capsule instance to retrieve.
+ @param[out] Buffer Specifies a caller-allocated buffer in which
+ the requested recovery capsule will be returned.
+
+ @retval EFI_SUCCESS The capsule was loaded correctly.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A requested recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ IN UINTN CapsuleInstance,
+ OUT VOID *Buffer,
+ IN CHAR16 *FileName
+ );
+
+//
+// Presents a standard interface to EFI_PEI_DEVICE_RECOVERY_MODULE_PPI,
+// regardless of the underlying device(s).
+//
+struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI {
+ EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules; ///< Returns the number of DXE capsules residing on the device.
+ EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo; ///< Returns the size and type of the requested recovery capsule.
+ EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE capsule from some media into memory.
+};
+
+extern EFI_GUID gEfiPeiDeviceRecoveryModulePpiGuid;
+
+#endif /* _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ */
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchInit.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchInit.h new file mode 100644 index 0000000000..ca955bdec4 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchInit.h @@ -0,0 +1,58 @@ +/** @file
+ This file defines the PCH Init PPI
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_INIT_H_
+#define _PCH_INIT_H_
+
+#include <Protocol/PchPlatformPolicy.h>
+
+extern EFI_GUID gPchInitPpiGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_INIT_PPI PCH_INIT_PPI;
+
+/**
+ The function performing USB init in PEI phase. This could be used by USB recovery
+ or debug features that need USB initialization during PEI phase.
+ Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize
+ has been done and PchUsbPolicyPpi has been installed.
+
+ @param[in] PeiServices General purpose services available to every PEIM
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval Others All other error conditions encountered result in an ASSERT.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_USB_INIT) (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+///
+/// PCH_INIT_PPI Structure Definition
+///
+struct _PCH_INIT_PPI {
+ ///
+ /// The function performs USB init in PEI phase. This could be used by USB recovery
+ /// or debug function that USB initialization needs to be done in PEI phase.
+ /// Note: Before executing this function, please be sure that PCH_PLATFORM_POLICY_PPI
+ /// and PCH_USB_POLICY_PPI have been installed.
+ ///
+ PCH_USB_INIT UsbInit;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchPlatformPolicy.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchPlatformPolicy.h new file mode 100644 index 0000000000..ca889b8f32 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchPlatformPolicy.h @@ -0,0 +1,360 @@ +/** @file
+ PCH policy PPI produced by a platform driver specifying various
+ expected PCH settings. This PPI is consumed by the PCH PEI modules.
+
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCH_PLATFORM_POLICY_H_
+#define PCH_PLATFORM_POLICY_H_
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+
+#include "PchRegs.h"
+
+extern EFI_GUID gPchPlatformPolicyPpiGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
+
+///
+/// PPI revision number
+/// Any backwards compatible changes to this PPI will result in an update in the revision number
+/// Major changes will require publication of a new PPI
+///
+/// Revision 1: Original version
+///
+#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1
+//
+// Generic definitions for device enabling/disabling used by PCH code.
+//
+#define PCH_DEVICE_ENABLE 1
+#define PCH_DEVICE_DISABLE 0
+
+//
+// ---------------------------- HPET Config -----------------------------
+//
+typedef struct {
+ BOOLEAN Enable; ///< Determines if enable HPET function
+ UINT32 Base; ///< The HPET base address
+} PCH_HPET_CONFIG;
+
+#ifdef SATA_SUPPORT
+
+///
+/// ---------------------------- SATA Config -----------------------------
+///
+typedef enum {
+ PchSataModeIde = 0,
+ PchSataModeAhci = 1,
+ PchSataModeRaid = 2,
+ PchSataModeMax
+} PCH_SATA_MODE;
+
+typedef enum {
+ PchSataSpeedGen1 = 1,
+ PchSataSpeedGen2,
+ PchSataSpeedGen3
+} PCH_SATA_SPEED;
+
+typedef struct {
+ UINT8 MechSw : 1; /// 0: Disable; 1: Enable
+ UINT8 External : 1; /// 0: Disable; 1: Enable
+ UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device
+ UINT8 Rsvdbits : 5; /// Reserved fields for future expansion w/o protocol change
+} PCH_SATA_PORT_SETTINGS_PEI;
+
+typedef struct {
+ PCH_SATA_PORT_SETTINGS_PEI PortSettings[PCH_AHCI_MAX_PORTS];
+ UINT8 SalpSupport : 1; ///< 0: Disable; 1: Enable Aggressive Link Power Management
+ UINT8 TestMode : 1; ///< 0: Disable; 1: Allow entrance to the PCH SATA test modes
+ UINT8 Rsvdbits : 6; ///< Reserved fields for future expansion w/o protocol change
+ PCH_SATA_MODE SataMode;
+ PCH_SATA_SPEED SpeedSupport; ///< Indicates the maximum speed the SATA controller can support
+ ///< 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s (Gen 2); 3h: 6 Gb/s (Gen 3)
+} PCH_SATA_CONFIG_PEI;
+#endif
+
+#ifdef PCIESC_SUPPORT
+//
+// ---------------------------- PCI Express Config -----------------------------
+//
+typedef enum {
+ PchPcieAuto,
+ PchPcieGen1,
+ PchPcieGen2
+} PCH_PCIE_SPEED;
+///
+/// Refer to PCH EDS for the PCH implementation values corresponding
+/// to below PCI-E spec defined ranges
+///
+typedef enum {
+ PchPcieL1SubstatesDisabledPei,
+ PchPcieL1SubstatesL1_1Pei,
+ PchPcieL1SubstatesL1_2Pei,
+ PchPcieL1SubstatesL1_1_2Pei,
+ PchPcieL1SubstatesMaxPei
+} PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL_PEI;
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabledPei,
+ PchPcieAspmL0sPei,
+ PchPcieAspmL1Pei,
+ PchPcieAspmL0sL1Pei,
+ PchPcieAspmAutoConfigPei,
+ PchPcieAspmMaxPei
+} PCH_PCI_EXPRESS_ASPM_CONTROL_PEI;
+
+typedef enum {
+ PchPcieCompletionTO_DefaultPei,
+ PchPcieCompletionTO_50_100usPei,
+ PchPcieCompletionTO_1_10msPei,
+ PchPcieCompletionTO_16_55msPei,
+ PchPcieCompletionTO_65_210msPei,
+ PchPcieCompletionTO_260_900msPei,
+ PchPcieCompletionTO_1_3P5sPei,
+ PchPcieCompletionTO_4_13sPei,
+ PchPcieCompletionTO_17_64sPei,
+ PchPcieCompletionTO_DisabledPei
+} PCH_PCIE_COMPLETION_TIMEOUT_PEI;
+
+typedef struct {
+ UINT8 Enable : 1; ///< Root Port enabling, 0: Disable; 1: Enable.
+ UINT8 Hide : 1; ///< Whether or not to hide the configuration space of this port.
+ UINT8 SlotImplemented : 1; ///< Indicates whether the root port is connected to a slot.
+ UINT8 HotPlug : 1; ///< Indicate whether the root port is hot plug available.
+ UINT8 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled.
+ UINT8 ExtSync : 1; ///< Indicate whether the extended synch is enabled.
+ UINT8 Rsvdbits : 2;
+ //
+ // Error handlings
+ //
+ UINT8 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled.
+ UINT8 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled.
+ UINT8 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled.
+ UINT8 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled.
+ UINT8 PmeInterrupt : 1; ///< Indicate whether the PME Interrupt is enabled.
+ UINT8 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled.
+ UINT8 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled.
+ UINT8 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled.
+
+ UINT8 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled
+ UINT8 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled.
+ UINT8 NonCommonClockSscMode : 1; ///< Indicate whether the root port assumed to be operating in non-common clock mode with SSC enabled.
+ UINT8 Reserved : 5; ///< Reserved fields for future expansion w/o protocol change
+
+ UINT8 FunctionNumber; ///< The function number this root port is mapped to
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port.
+ UINT8 DetectTime; ///< The DetectTime will be utilized to decide how much time we want to poll to detect PCIe device, The unit is millisecond.
+ PCH_PCIE_COMPLETION_TIMEOUT_PEI CompletionTimeout; ///< The completion timeout configuration of the root port
+ PCH_PCI_EXPRESS_ASPM_CONTROL_PEI Aspm; ///< The ASPM configuration of the root port
+ PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL_PEI L1Substates; ///< The L1 Substates configuration of the root port
+ UINT8 TxEqdeEmphSelection; ///< When the Link is operating at 5.0 GT/s speed, select the level of de-emphasis for an Upstream component.
+} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG_PEI;
+
+typedef struct {
+ ///
+ ///< Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2.
+ ///
+ PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Temp Bus Number range available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempRootPortBusNumMin;
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCH_PCI_EXPRESS_ROOT_PORT_CONFIG_PEI RootPort[PCH_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Temp Bus Number range available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempRootPortBusNumMax;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules.
+ ///
+ UINT8 RootPortClockGating : 1;
+ UINT8 Rsvdbits : 7; ///< Reserved fields for future expansion w/o protocol change
+} PCH_PCIE_CONFIG;
+
+//
+// --------------------------- Power Optimizer Config ------------------------------
+//
+typedef struct {
+ UINT8 LtrEnable :1; ///< Latency Tolerance Reporting Mechanism.
+ UINT8 ObffEnable :1; ///< Pcie end point Optimized Buffer Flush/Fill (OBFF) capability for the root port.
+} PCH_PCIE_PWR_OPT_PEI;
+
+typedef struct {
+ UINT16 VendorId; ///< PCI configuration space offset 0
+ UINT16 DeviceId; ///< PCI configuration space offset 2
+ UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings
+/**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+**/
+ UINT16 SnoopLatency;
+/**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+**/
+ UINT16 NonSnoopLatency;
+} PCH_PCIE_DEVICE_LTR_OVERRIDE_PEI;
+
+typedef struct {
+ UINT8 NumOfDevLtrOverride; ///< Number of Pci Express card listed in LTR override table
+ PCH_PCIE_DEVICE_LTR_OVERRIDE_PEI *DevLtrOverride; ///< Pointer to Pci Express devices LTR override table
+ PCH_PCIE_PWR_OPT_PEI PchPwrOptPcie[PCH_PCIE_MAX_ROOT_PORTS]; ///< related configuration for PCIE ports power optimization.
+} PCH_PCIE_PWR_OPT_CONFIG;
+#endif
+
+//
+// ---------------------------- IO APIC Config -----------------------------
+//
+typedef struct {
+ UINT8 IoApicId; ///< This member determines IOAPIC ID.
+} PCH_IOAPIC_CONFIG;
+
+//
+// ------------------------------ USB Config -------------------------------
+//
+typedef enum {
+ SsicHsRate_A = 0,
+ SsicHsRate_B = 1
+} PCH_SSIC_HS_RATE;
+
+typedef enum {
+ SsicLaneHs_G1 = 0,
+ SsicLaneHs_G2 = 1,
+ SsicLaneHs_G3 = 2
+} PCH_SSIC_LANE_HS;
+
+typedef enum {
+ PchUsb2PhyPgDisabled = 0,
+ PchUsb2PhyPgEnabled = 1,
+ PchUsbPhyPgAuto = 2
+} PCH_USB2_PHY_PG;
+
+//
+// ---------------------------- PCH Platform Data -----------------------------
+//
+typedef struct {
+ UINT8 SmmBwp : 1; ///< 0: Clear SMM_BWP bit; 1: Set SMM_BWP bit.
+ UINT8 Rsvdbits : 7;
+ UINT32 TempMemBaseAddr; ///< Temporary Memory Base Address for PCI devices to be
+ ///< used to initialize MMIO registers. Minimum size is
+ ///< 64KB bytes
+ UINT8 SsicEnable; ///< Enable / Disable SSIC initialization
+ PCH_SSIC_HS_RATE SsicHsRate; ///< SSIC HS Rate
+ UINT8 SsicInitSequence; ///< Sequence 1 / Sequence 2
+ PCH_SSIC_LANE_HS SsicLaneHs[PCH_SSIC_MAX_PORTS]; ///< SSIC Lane HS Gear
+ UINT8 SsicPortEnable[PCH_SSIC_MAX_PORTS]; ///< SSIC Port Enable, 0: Disable; 1: Enable.
+ UINT8 HsicPortEnable[PCH_HSIC_MAX_PORTS]; ///< HSIC Port Enable, 0: Disable; 1: Enable.
+ PCH_USB2_PHY_PG Usb2PhyPgEnabled; ///< USB2 PHY Power Gating Enable, 0: Disable; 1: Enable; 2: Auto.
+ UINT8 PerPortPeTxiSet[PCH_USB_MAX_PHYSICAL_PORTS]; ///< Value of USB2 PHY PERPORTPETXISET Register, USB2_PER_PORT_PPX [13:11]
+ UINT8 PerPortTxiSet[PCH_USB_MAX_PHYSICAL_PORTS]; ///< Value of USB2 PHY PERPORTTXISET Register, USB2_PER_PORT_PPX [10:8]
+ UINT8 IUsbTxEmphasisEn[PCH_USB_MAX_PHYSICAL_PORTS]; ///< Value of USB2 PHY IUSBTXEMPHASISEN Register, USB2_PER_PORT_2_PPX [24:23]
+ UINT8 PerPortTxPeHalf[PCH_USB_MAX_PHYSICAL_PORTS]; ///< Value of USB2 PHY PERPORTTXPEHALF Register, USB2_PER_PORT_PPX [14]
+ UINT8 Ow2tapgen2deemph3p5[PCH_XHCI_MAX_USB3_PORTS]; ///< Value of USB3 PHY ow2tapgen2deemph3p5 Register, TX_DWORD4[15:8]
+} PCH_PLATFORM_DATA;
+
+///
+/// ---------------------------- PCH SSC Settings -----------------------------
+///
+typedef struct {
+ UINT8 Usb3ClkSsc; /// Enable Spread for USB3 clocks. 0: Disable; 1: Enable
+ UINT8 DispClkSsc; /// Enable Spread for Display clocks. 0: Disable; 1: Enable
+ UINT8 SataClkSsc; /// Enable Spread for SATA clocks. 0: Disable; 1: Enable
+} PCH_SSC_SETTINGS;
+
+///
+/// ------------ General PCH Platform Policy PPI definition ------------
+///
+struct _PCH_PLATFORM_POLICY_PPI {
+ ///
+ /// This member specifies the revision of the PCH policy PPI. This field is used to
+ /// indicate backwards compatible changes to the protocol. Platform code that produces
+ /// this PPI must fill with the correct revision value for the PCH reference code
+ /// to correctly interpret the content of the PPI fields.
+ ///
+ UINT8 Revision;
+ UINT8 BusNumber; ///< Bus Number of the PCH device.
+ UINT32 SpiBase; ///< SPI Base Address.
+ UINT32 PmcBase; ///< PMC Base Address.
+ UINT32 IoBase; ///< IO Base Address.
+ UINT32 IlbBase; ///< Intel Legacy Block Base Address.
+ UINT32 Rcba; ///< Root Complex Base Address.
+ UINT32 MphyBase; ///< MPHY Base Address.
+ UINT32 PunitBase; ///< PUNIT Base Address.
+ UINT16 AcpiBase; ///< ACPI I/O Base address.
+ PCH_HPET_CONFIG *HpetConfig;
+#ifdef SATA_SUPPORT
+ PCH_SATA_CONFIG_PEI *SataConfig;
+#endif
+#ifdef PCIESC_SUPPORT
+ ///
+ /// This member describes PCI Express controller's related configuration.
+ ///
+ PCH_PCIE_CONFIG *PcieConfig;
+ ///
+ /// This member describes the Power Optimizer configuration.
+ ///
+ PCH_PCIE_PWR_OPT_CONFIG *PwrOptConfig;
+#endif
+ PCH_IOAPIC_CONFIG *IoApicConfig;
+ PCH_PLATFORM_DATA *PlatformData;
+ ///
+ /// This member describes the PCH SSC Settings
+ ///
+ PCH_SSC_SETTINGS *PchSscSettings;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchUsbPolicy.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchUsbPolicy.h new file mode 100644 index 0000000000..50906257dc --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PchUsbPolicy.h @@ -0,0 +1,80 @@ +/** @file
+ PCH Usb policy PPI produced by a platform driver specifying
+ various expected PCH Usb settings. This PPI is consumed by the
+ PCH PEI drivers.
+
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_USB_POLICY_H_
+#define _PCH_USB_POLICY_H_
+
+///
+/// PCH Usb policy provided by platform for PEI phase
+///
+
+#include <PiPei.h>
+
+#include "PchRegs.h"
+#include <Protocol/PchPlatformPolicy.h>
+
+extern EFI_GUID gPchUsbPolicyPpiGuid;
+
+typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI;
+
+///
+/// PPI revision number
+/// Any backwards compatible changes to this PPI will result in an update in the revision number
+/// Major changes will require publication of a new PPI
+///
+/// Revision 1: Original version
+///
+#define PCH_USB_POLICY_PPI_REVISION_1 1
+
+//
+// Generic definitions for device enabling/disabling used by PCH code.
+//
+#define PCH_DEVICE_ENABLE 1
+#define PCH_DEVICE_DISABLE 0
+
+#define XHCI_MODE 1
+
+///
+/// PCH Usb policy PPI produced by a platform driver specifying various expected
+/// PCH Usb settings that would be used by PCH_INIT_PPI.UsbInit () and USB PEI module.
+/// This PPI needs to be installed before calling PCH_INIT_PPI.UsbInit ().
+///
+struct _PCH_USB_POLICY_PPI {
+ ///
+ /// This member specifies the revision of the PEI PCH USB Policy PPI.
+ /// This field is used to indicate backwards compatible changes to the protocol.
+ /// Platform code that produces this PPI must fill with the correct revision value
+ /// for the PCH reference code to correctly interpret the content of the PPI fields.
+ ///
+ UINT8 Revision;
+ ///
+ /// This member describes USB controller's related configuration.
+ ///
+ PCH_USB_CONFIG *UsbConfig;
+ ///
+ /// This member decides which USB controller needs to be initialed and allocated
+ /// resource in Pei Phase. It will be referred by USB PEI module.
+ ///
+ UINT8 Mode;
+ ///
+ /// This member describes XHCI memory base address. USB PEI module will refer to
+ /// this field to program memory base address of the XHCI controller.
+ ///
+ UINTN XhciMemBaseAddr;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PeiBlockIo.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PeiBlockIo.h new file mode 100644 index 0000000000..b73bd52093 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/PeiBlockIo.h @@ -0,0 +1,227 @@ +/** @file
+ Block IO protocol as defined in the UEFI 2.0 specification.
+
+ The Block IO protocol is used to abstract block devices like hard drives,
+ DVD-ROMs and floppy drives.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PEI_BLOCK_IO_H__
+#define __PEI_BLOCK_IO_H__
+
+typedef struct _PEI_BLOCK_IO_PPI PEI_BLOCK_IO_PPI;
+
+/**
+ Reset the Block Device.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] ExtendedVerification Driver may perform diagnostics on reset.
+
+ @retval EFI_SUCCESS The device was reset.
+ @retval EFI_DEVICE_ERROR The device is not functioning properly and could
+ not be reset.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_BLOCK_RESET) (
+ IN PEI_BLOCK_IO_PPI *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+/**
+ Read BufferSize bytes from Lba into Buffer.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] MediaId Id of the media, changes every time the media is replaced.
+ @param[in] Lba The starting Logical Block Address to read from
+ @param[in] BufferSize Size of Buffer, must be a multiple of device block size.
+ @param[in] Buffer A pointer to the destination buffer for the data. The caller is
+ responsible for either having implicit or explicit ownership of the buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the read.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId does not matched the current device.
+ @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_BLOCK_READ) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BLOCK_IO_PPI *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Write BufferSize bytes from Lba into Buffer.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] MediaId The media ID that the write request is for.
+ @param[in] Lba The starting logical block address to be written. The caller is
+ responsible for writing to only legitimate locations.
+ @param[in] BufferSize Size of Buffer, must be a multiple of device block size.
+ @param[in] Buffer A pointer to the source buffer for the data.
+
+ @retval EFI_SUCCESS The data was written correctly to the device.
+ @retval EFI_WRITE_PROTECTED The device can not be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
+ @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_BLOCK_WRITE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BLOCK_IO_PPI *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Flush the Block Device.
+
+ @param[in] This Indicates a pointer to the calling context.
+
+ @retval EFI_SUCCESS All outstanding data was written to the device
+ @retval EFI_DEVICE_ERROR The device reported an error while writting back the data
+ @retval EFI_NO_MEDIA There is no media in the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_BLOCK_FLUSH) (
+ IN PEI_BLOCK_IO_PPI *This
+ );
+
+/**
+ Block IO read only mode data and updated only via members of BlockIO
+**/
+typedef struct {
+ ///
+ /// The curent media Id. If the media changes, this value is changed.
+ ///
+ UINT32 MediaId;
+
+ ///
+ /// TRUE if the media is removable; otherwise, FALSE.
+ ///
+ BOOLEAN RemovableMedia;
+
+ ///
+ /// TRUE if there is a media currently present in the device;
+ /// othersise, FALSE. THis field shows the media present status
+ /// as of the most recent ReadBlocks() or WriteBlocks() call.
+ ///
+ BOOLEAN MediaPresent;
+
+ ///
+ /// TRUE if LBA 0 is the first block of a partition; otherwise
+ /// FALSE. For media with only one partition this would be TRUE.
+ ///
+ BOOLEAN LogicalPartition;
+
+ ///
+ /// TRUE if the media is marked read-only otherwise, FALSE.
+ /// This field shows the read-only status as of the most recent WriteBlocks () call.
+ ///
+ BOOLEAN ReadOnly;
+
+ ///
+ /// TRUE if the WriteBlock () function caches write data.
+ ///
+ BOOLEAN WriteCaching;
+
+ ///
+ /// The intrinsic block size of the device. If the media changes, then
+ /// this field is updated.
+ ///
+ UINT32 BlockSize;
+
+ ///
+ /// Supplies the alignment requirement for any buffer to read or write block(s).
+ ///
+ UINT32 IoAlign;
+
+ ///
+ /// The last logical block address on the device.
+ /// If the media changes, then this field is updated.
+ ///
+ EFI_LBA LastBlock;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
+ /// a physical block boundary.
+ ///
+ EFI_LBA LowestAlignedLba;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
+ /// per physical block.
+ ///
+ UINT32 LogicalBlocksPerPhysicalBlock;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length
+ /// granularity as a number of logical blocks.
+ ///
+ UINT32 OptimalTransferLengthGranularity;
+} PEI_BLOCK_IO_MEDIA;
+
+#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031
+
+///
+/// Revision defined in EFI1.1.
+///
+#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
+
+///
+/// This protocol provides control over block devices.
+///
+struct _PEI_BLOCK_IO_PPI {
+ ///
+ /// The revision to which the block IO interface adheres. All future
+ /// revisions must be backwards compatible. If a future version is not
+ /// back wards compatible, it is not the same GUID.
+ ///
+ UINT64 Revision;
+ ///
+ /// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.
+ ///
+ PEI_BLOCK_IO_MEDIA *Media;
+ PEI_BLOCK_RESET Reset;
+ PEI_BLOCK_READ ReadBlocks;
+ PEI_BLOCK_WRITE WriteBlocks;
+ PEI_BLOCK_FLUSH FlushBlocks;
+};
+
+//extern EFI_GUID gEfiBlockIoProtocolGuid;
+extern EFI_GUID gPeiBlockIoPpiGuid;
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Sdhc.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Sdhc.h new file mode 100644 index 0000000000..c7feffffb7 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Sdhc.h @@ -0,0 +1,311 @@ +/**@file
+ This file defines the EFI SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SDHC_H_
+#define _PEI_SDHC_H_
+
+typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;
+
+#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
+
+typedef enum {
+ ResponseNo = 0,
+ ResponseR1,
+ ResponseR1b,
+ ResponseR2,
+ ResponseR3,
+ ResponseR4,
+ ResponseR5,
+ ResponseR5b,
+ ResponseR6,
+ ResponseR7
+} RESPONSE_TYPE;
+
+typedef enum {
+ NoData = 0,
+ InData,
+ OutData
+} TRANSFER_TYPE;
+
+typedef enum {
+ Reset_Auto = 0,
+ Reset_DAT,
+ Reset_CMD,
+ Reset_DAT_CMD,
+ Reset_All
+} RESET_TYPE;
+
+typedef enum {
+ SDMA = 0,
+ ADMA2,
+ PIO
+} DMA_MOD;
+
+typedef struct {
+ UINT32 HighSpeedSupport: 1; //High speed supported
+ UINT32 V18Support: 1; //1.8V supported
+ UINT32 V30Support: 1; //3.0V supported
+ UINT32 V33Support: 1; //3.3V supported
+ UINT32 Reserved0: 4;
+ UINT32 BusWidth4: 1; // 4 bit width
+ UINT32 BusWidth8: 1; // 8 bit width
+ UINT32 Reserved1: 6;
+ UINT32 SDMASupport: 1;
+ UINT32 ADMA2Support: 1;
+ UINT32 DmaMode: 2;
+ UINT32 Reserved2: 12;
+ UINT32 BoundarySize;
+} HOST_CAPABILITY;
+
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
+#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
+#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
+
+//
+//MMIO Registers definition for MMC/SDIO controller
+//
+#define MMIO_DMAADR 0x00
+#define MMIO_BLKSZ 0x04
+#define MMIO_BLKCNT 0x06
+#define MMIO_CMDARG 0x08
+#define MMIO_XFRMODE 0x0C
+#define MMIO_SDCMD 0x0E
+#define MMIO_RESP 0x10
+#define MMIO_BUFDATA 0x20
+#define MMIO_PSTATE 0x24
+#define MMIO_HOSTCTL 0x28
+#define MMIO_PWRCTL 0x29
+#define MMIO_BLKGAPCTL 0x2A
+#define MMIO_WAKECTL 0x2B
+#define MMIO_CLKCTL 0x2C
+#define MMIO_TOCTL 0x2E
+#define MMIO_SWRST 0x2F
+#define MMIO_NINTSTS 0x30
+#define MMIO_ERINTSTS 0x32
+#define MMIO_NINTEN 0x34
+#define MMIO_ERINTEN 0x36
+#define MMIO_NINTSIGEN 0x38
+#define MMIO_ERINTSIGEN 0x3A
+#define MMIO_AC12ERRSTS 0x3C
+#define MMIO_HOST_CTL2 0x3E
+#define MMIO_CAP 0x40
+#define MMIO_CAP2 0x44
+#define MMIO_MCCAP 0x48
+#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50
+#define MMIO_FORCEEVENTERRINTSTAT 0x52
+#define MMIO_ADMAERRSTAT 0x54
+#define MMIO_ADMASYSADDR 0x58
+#define MMIO_PRESETVALUE0 0x60
+#define MMIO_PRESETVALUE1 0x64
+#define MMIO_PRESETVALUE2 0x68
+#define MMIO_PRESETVALUE3 0x6C
+#define MMIO_BOOTTIMEOUTCTRL 0x70
+#define MMIO_DEBUGSEL 0x74
+#define MMIO_SHAREDBUS 0xE0
+#define MMIO_SPIINTSUP 0xF0
+#define MMIO_SLTINTSTS 0xFC
+#define MMIO_CTRLRVER 0xFE
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData OPTIONAL
+ );
+
+/**
+ Set max clock frequency of the host, the actual frequency
+ may not be the same as MaxFrequency. It depends on
+ the max frequency the host can support, divider, and host
+ speed mode.
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] MaxFrequency - Max frequency in HZ
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT32 MaxFrequency
+ );
+
+/**
+ Set bus width of the host
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] BusWidth - Bus width in 1, 4, 8 bits
+
+ @retval EFI_SUCCESS
+ @retval EFI_INVALID_PARAMETER
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT32 BusWidth
+ );
+
+/**
+ Set Host mode in DDR
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] SetHostDdrMode - True for DDR Mode set, false for normal mode
+
+ @retval EFI_SUCCESS
+ @retval EFI_INVALID_PARAMETER
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT32 DdrMode
+ );
+
+/**
+ Set voltage which could supported by the host.
+ Support 0(Power off the host), 1.8V, 3.0V, 3.3V
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] Voltage - Units in 0.1 V
+
+ @retval EFI_SUCCESS
+ @retval EFI_INVALID_PARAMETER
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT32 Voltage
+ );
+
+/**
+ Reset the host
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] ResetAll - TRUE to reset all
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN RESET_TYPE ResetType
+ );
+
+/**
+ Reset the host
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] Enable - TRUE to enable, FALSE to disable
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN BOOLEAN Enable
+ );
+
+/**
+ Find whether these is a card inserted into the slot. If so
+ init the host. If not, return EFI_NOT_FOUND.
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (
+ IN PEI_SD_CONTROLLER_PPI *This
+ );
+
+/**
+ Set the Block length
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] BlockLength - card supports block length
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (
+ IN PEI_SD_CONTROLLER_PPI *This,
+ IN UINT32 BlockLength
+ );
+
+/**
+ Set the Block length
+
+ @param[in] This - Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] BlockLength - card supports block length
+
+ @retval EFI_SUCCESS
+ @retval EFI_TIMEOUT
+
+**/
+
+typedef EFI_STATUS
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(
+ IN PEI_SD_CONTROLLER_PPI *This
+ );
+
+//
+// Interface structure for the EFI SD Host I/O Protocol
+//
+struct _PEI_SD_CONTROLLER_PPI {
+ UINT32 Revision;
+ HOST_CAPABILITY HostCapability;
+ EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand;
+ EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency;
+ EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth;
+ EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage;
+ EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
+ EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost;
+ EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
+ EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
+ EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength;
+ EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice;
+ };
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPeiSdhcPpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/SmbusPolicy.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/SmbusPolicy.h new file mode 100644 index 0000000000..26fd24d988 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/SmbusPolicy.h @@ -0,0 +1,30 @@ +/** @file
+ Smbus Policy PPI as defined in EFI 2.0
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SMBUS_POLICY_PPI_H
+#define _PEI_SMBUS_POLICY_PPI_H
+
+typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI;
+
+typedef struct _PEI_SMBUS_POLICY_PPI {
+ UINTN BaseAddress;
+ UINT32 PciAddress;
+ UINT8 NumRsvdAddress;
+ UINT8 *RsvdAddress;
+} PEI_SMBUS_POLICY_PPI;
+
+extern EFI_GUID gPeiSmbusPolicyPpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Spi.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Spi.h new file mode 100644 index 0000000000..890e8e5e14 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Ppi/Spi.h @@ -0,0 +1,34 @@ +/** @file
+ This file defines the EFI SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SPI_H_
+#define _PEI_SPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPeiSpiPpiGuid;
+
+//
+// Reuse the EFI_SPI_PROTOCOL definitions
+// This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+// as it uses EDKII Glue Lib to do IO accesses
+//
+typedef EFI_SPI_PROTOCOL PEI_SPI_PPI;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/ActiveBios.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/ActiveBios.h new file mode 100644 index 0000000000..46ee5eec7e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/ActiveBios.h @@ -0,0 +1,111 @@ +/** @file
+ This protocol is used to report and control what BIOS is mapped to the
+ BIOS address space anchored at 4GB boundary.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_
+#define _EFI_ACTIVE_BIOS_PROTOCOL_H_
+
+extern EFI_GUID gEfiActiveBiosProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL;
+
+///
+/// Protocol definitions
+///
+typedef enum {
+ ActiveBiosStateSpi,
+ ActiveBiosStateLpc,
+ ActiveBiosStateMax
+} EFI_ACTIVE_BIOS_STATE;
+
+/**
+ Change the current active BIOS settings to the requested state.
+ The caller is responsible for requesting a supported state from
+ the EFI_ACTIVE_BIOS_STATE selections.
+ This will fail if someone has locked the interface and the correct key is
+ not provided.
+
+ @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
+ @param[in] DesiredState The requested state to configure the system for.
+ @param[in] Key If the interface is locked, Key must be the Key
+ returned from the LockState function call.
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_ACCESS_DENIED The interface is currently locked.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) (
+ IN EFI_ACTIVE_BIOS_PROTOCOL * This,
+ IN EFI_ACTIVE_BIOS_STATE DesiredState,
+ IN UINTN Key
+ );
+
+/**
+ Lock the current active BIOS state from further changes. This allows a
+ caller to implement a critical section. This is optionally supported
+ functionality. Size conscious implementations may choose to require
+ callers cooperate without support from this protocol.
+
+ @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
+ @param[in] Lock TRUE to lock the current state, FALSE to unlock.
+ @param[in,out] Key If Lock is TRUE, then a key will be returned. If
+ Lock is FALSE, the key returned from the prior call
+ to lock the protocol must be provided to unlock the
+ protocol. The value of Key is undefined except that
+ it cannot be 0.
+
+ @retval EFI_SUCCESS Command succeed.
+ @exception EFI_UNSUPPORTED The function is not supported.
+ @retval EFI_ACCESS_DENIED The interface is currently locked.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) (
+ IN EFI_ACTIVE_BIOS_PROTOCOL * This,
+ IN BOOLEAN Lock,
+ IN OUT UINTN *Key
+ );
+
+///
+/// Protocol definition
+///
+/// Note that some functions are optional. This means that they may be NULL.
+/// Caller is required to verify that an optional function is defined by checking
+/// that the value is not NULL.
+///
+/// This protocol allows the PCH to be configured to map the top 16 MB of memory
+/// below 4 GB to different buses, LPC or SPI. The State reflects the current
+/// setting. SetState() allows consumers to request a new state, and LockState()
+/// allows consumers to prevent other consumers from changing the state. It is the
+/// caller's responsibility to configure and lock the desired state to prevent issues
+/// resulting from other consumers changing the state.
+///
+struct _EFI_ACTIVE_BIOS_PROTOCOL {
+ EFI_ACTIVE_BIOS_STATE State; ///< The current state mapping that is selected.
+ EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; ///< Change the current state to the requested state mapping.
+ EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; ///< Lock the current state mapping to prevent changes to the current state.
+};
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gEfiActiveBiosProtocolGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h new file mode 100644 index 0000000000..8a9eaec566 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h @@ -0,0 +1,29 @@ +/** @file
+ Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EMMC_CARD_INFO_H_
+#define _EMMC_CARD_INFO_H_
+
+typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL;
+
+//
+// EMMC Card info Structures
+//
+struct _EFI_EMMC_CARD_INFO_PROTOCOL{
+ CARD_DATA *CardData;
+};
+
+extern EFI_GUID gEfiEmmcCardInfoProtocolGuid;
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/I2cBus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/I2cBus.h new file mode 100644 index 0000000000..befacce4de --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/I2cBus.h @@ -0,0 +1,169 @@ +/** @file
+ I2C bus interface
+ This layer provides I/O access to an I2C device.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __I2C_BUS_H__
+#define __I2C_BUS_H__
+
+#include <Protocol/I2cHost.h>
+
+///
+/// I2C bus protocol
+///
+typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL;
+
+/**
+ Perform an I2C operation on the device
+
+ This routine must be called at or below TPL_NOTIFY. For synchronous
+ requests this routine must be called at or below TPL_CALLBACK.
+
+ N.B. The typical consumers of this API are the third party I2C
+ drivers. Extreme care must be taken by other consumers of this
+ API to prevent confusing the third party I2C drivers due to a
+ state change at the I2C device which the third party I2C drivers
+ did not initiate. I2C platform drivers may use this API within
+ these guidelines.
+
+ This routine queues an operation to the I2C controller for execution
+ on the I2C bus.
+
+ As an upper layer driver writer, the following need to be provided
+ to the platform vendor:
+
+ 1. ACPI CID value or string - this is used to connect the upper layer
+ driver to the device.
+ 2. Slave address array guidance when the I2C device uses more than one
+ slave address. This is used to access the blocks of hardware within
+ the I2C device.
+
+ @param[in] This Address of an EFI_I2C_BUS_PROTOCOL
+ structure
+ @param[in] SlaveAddressIndex Index into an array of slave addresses for
+ the I2C device. The values in the array are
+ specified by the board designer, with the
+ I2C device driver writer providing the slave
+ address order.
+
+ For devices that have a single slave address,
+ this value must be zero. If the I2C device
+ uses more than one slave address then the third
+ party (upper level) I2C driver writer needs to
+ specify the order of entries in the slave address
+ array.
+
+ \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"
+ section in I2cMaster.h.
+ @param[in] Event Event to set for asynchronous operations,
+ NULL for synchronous operations
+ @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
+ structure describing the I2C operation
+ @param[out] I2cStatus Optional buffer to receive the I2C operation
+ completion status
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_ABORTED The request did not complete because the driver
+ was shutdown.
+ @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value
+ @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
+ @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
+ This could indicate the slave device is not present.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL
+ @retval EFI_INVALID_PARAMETER TPL is too high
+ @retval EFI_NO_RESPONSE The I2C device is not responding to the
+ slave address. EFI_DEVICE_ERROR may also be
+ returned if the controller can not distinguish
+ when the NACK occurred.
+ @retval EFI_NOT_FOUND I2C slave address exceeds maximum address
+ @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
+ the event and then read status pointed to by
+ the request packet.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
+ @retval EFI_TIMEOUT The transaction did not complete within an internally
+ specified timeout period.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_BUS_START_REQUEST) (
+ IN CONST EFI_I2C_BUS_PROTOCOL *This,
+ IN UINTN SlaveAddressIndex,
+ IN EFI_EVENT Event OPTIONAL,
+ IN CONST EFI_I2C_STACK_REQUEST_PACKET *RequestPacket,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ );
+
+///
+/// The I2C bus protocol enables access to a specific device on the I2C bus.
+///
+/// Each I2C device is described as an ACPI node (HID, UID and CID) within the
+/// platform layer. The I2C bus protocol enumerates the I2C devices in the
+/// platform and creates a unique handle and device path for each I2C device.
+///
+/// I2C slave addressing is abstracted to validate addresses and limit operation
+/// to the specified I2C device. The third party providing the I2C device support
+/// provides an ordered list of slave addresses for the I2C device to the team
+/// building the platform layer. The platform team must preserve the order of the
+/// supplied list. SlaveAddressCount is the number of entries in this list or
+/// array within the platform layer. The third party device support references
+/// a slave address using an index into the list or array in the range of zero
+/// to SlaveAddressCount - 1.
+///
+struct _EFI_I2C_BUS_PROTOCOL {
+ ///
+ /// Start an I2C operation on the bus
+ ///
+ EFI_I2C_BUS_START_REQUEST StartRequest;
+
+ ///
+ /// The maximum number of slave addresses for the I2C device. The caller may
+ /// validate this value as a check on the platform layer's configuration. Slave
+ /// address selection uses an index value in the range of zero to SlaveAddressCount - 1.
+ ///
+ UINTN SlaveAddressCount;
+
+ ///
+ /// Hardware revision - Matches the ACPI _HRV value
+ ///
+ /// The HardwareRevision value allows a single driver to support multiple hardware
+ /// revisions and implement the necessary workarounds for limitations within the
+ /// hardware.
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// The maximum number of bytes the I2C host controller
+ /// is able to receive from the I2C bus.
+ ///
+ UINT32 MaximumReceiveBytes;
+
+ ///
+ /// The maximum number of bytes the I2C host controller
+ /// is able to send on the I2C bus.
+ ///
+ UINT32 MaximumTransmitBytes;
+
+ ///
+ /// The maximum number of bytes in the I2C bus transaction.
+ ///
+ UINT32 MaximumTotalBytes;
+};
+
+///
+/// GUID for the I2C bus protocol
+///
+extern EFI_GUID gEfiI2cBusProtocolGuid;
+
+#endif // __I2C_BUS_H__
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/MmioDevice.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/MmioDevice.h new file mode 100644 index 0000000000..96e1892bd5 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/MmioDevice.h @@ -0,0 +1,91 @@ +/** @file
+ MMIO device protocol as defined in the UEFI 2.x.x specification.
+
+ The MMIO device protocol defines a memory mapped I/O device
+ for use by the system.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __MMIO_DEVICE_H__
+#define __MMIO_DEVICE_H__
+
+///
+/// Protocol to define for the MMIO device
+//
+typedef struct {
+ ///
+ /// Address of a GUID
+ ///
+ EFI_GUID *Guid;
+
+ ///
+ /// Context for the protocol
+ ///
+ VOID *Context;
+} EFI_MMIO_DEVICE_PROTOCOL_ITEM;
+
+typedef struct _EFI_MMIO_DEVICE_PROTOCOL EFI_MMIO_DEVICE_PROTOCOL;
+
+///
+/// The MMIO device protocol defines a memory mapped I/O device
+/// for use by the system.
+///
+struct _EFI_MMIO_DEVICE_PROTOCOL {
+ ///
+ /// Pointer to an ACPI_EXTENDED_HID_DEVICE_PATH structure
+ /// containing HID/HidStr and CID/CidStr values.
+ ///
+ /// See the note below associated with the UnitIdentification
+ /// field.
+ ///
+ CONST ACPI_EXTENDED_HID_DEVICE_PATH *AcpiPath;
+
+ ///
+ /// Allow the use of a shared template for the AcpiPath.
+ ///
+ /// If this value is non-zero UID value then the AcpiPath must
+ /// be a template which contains only the HID/HidStr and CID/CidStr
+ /// values. The UID/UidStr values in the AcpiPath must be zero!
+ //
+ /// If this value is zero then the AcpiPath is not shared and
+ /// must contain either a non-zero UID value or a UidStr value.
+ ///
+ UINT32 UnitIdentification;
+
+ ///
+ /// Hardware revision - ACPI _HRV value
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// Pointer to a data structure containing the controller
+ /// resources and configuration. At a minimum this points
+ /// to an EFI_PHYSICAL_ADDRESS for the base address of the
+ /// MMIO device.
+ ///
+ CONST VOID *DriverResources;
+
+ ///
+ /// Number of protocols in the array
+ ///
+ UINTN ProtocolCount;
+
+ ///
+ /// List of protocols to define
+ ///
+ CONST EFI_MMIO_DEVICE_PROTOCOL_ITEM *ProtocolArray;
+};
+
+extern EFI_GUID gEfiMmioDeviceProtocolGuid;
+
+#endif // __MMIO_DEVICE_H__
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchExtendedReset.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchExtendedReset.h new file mode 100644 index 0000000000..10a3c93b77 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchExtendedReset.h @@ -0,0 +1,67 @@ +/** @file
+ PCH Extended Reset Protocol
+
+ Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_PCH_EXTENDED_RESET_H_
+#define _EFI_PCH_EXTENDED_RESET_H_
+
+extern EFI_GUID gEfiPchExtendedResetProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_PCH_EXTENDED_RESET_PROTOCOL EFI_PCH_EXTENDED_RESET_PROTOCOL;
+
+//
+// Related Definitions
+//
+//
+// PCH Extended Reset Types
+//
+typedef struct {
+ UINT8 PowerCycle : 1; // 0: Disabled*; 1: Enabled
+ UINT8 GlobalReset : 1; // 0: Disabled*; 1: Enabled
+ UINT8 SusPwrDnAck : 1; // 0: Do Nothing;
+ // 1: GPIO[30](SUS_PWR_DN_ACK) level is set low prior to Global Reset(for systems with an embedded controller)
+ UINT8 RsvdBits : 5; // Reserved fields for future expansion w/o protocol change
+} PCH_EXTENDED_RESET_TYPES;
+
+//
+// Member functions
+//
+
+/**
+ Execute Pch Extended Reset from the host controller.
+
+ @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
+ @param[in] PchExtendedResetTypes Pch Extended Reset Types which includes PowerCycle, Globalreset.
+
+ Does not return if the reset takes place.
+ @retval EFI_INVALID_PARAMETER If ResetType is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PCH_EXTENDED_RESET) (
+ IN EFI_PCH_EXTENDED_RESET_PROTOCOL * This,
+ IN PCH_EXTENDED_RESET_TYPES PchExtendedResetTypes
+ );
+
+//
+// Interface structure for the Pch Extended Reset Protocol
+//
+struct _EFI_PCH_EXTENDED_RESET_PROTOCOL {
+ EFI_PCH_EXTENDED_RESET Reset;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchInfo.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchInfo.h new file mode 100644 index 0000000000..cea25fcf2d --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchInfo.h @@ -0,0 +1,69 @@ +/** @file
+ This file defines the PCH Info Protocol.
+
+ Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_INFO_H_
+#define _PCH_INFO_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiPchInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL;
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+/// Revision 1: Original version
+///
+#define PCH_INFO_PROTOCOL_REVISION_1 1
+
+///
+/// RCVersion[7:0] is the release number.
+/// For example:
+/// PchFramework 0.6.0-01 should be 00 06 00 01 (0x00060001)
+/// PchFramework 0.6.2 should be 00 06 02 00 (0x00060200)
+///
+#define PCH_RC_VERSION 0x00090000
+
+///
+/// Protocol definition
+///
+/// This protocol is used to provide the information of PCH controller.
+///
+struct _EFI_PCH_INFO_PROTOCOL {
+ ///
+ /// This member specifies the revision of the PCH Info protocol. This field is used
+ /// to indicate backwards compatible changes to the protocol. Platform code that
+ /// consumes this protocol must read the correct revision value to correctly interpret
+ /// the content of the protocol fields.
+ ///
+ UINT8 Revision;
+ ///
+ /// The actual bus number of the PCH devices.
+ ///
+ UINT8 BusNumber;
+ ///
+ /// The reference code package release number
+ ///
+ UINT32 RCVersion;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchPlatformPolicy.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchPlatformPolicy.h new file mode 100644 index 0000000000..cbbf80123e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchPlatformPolicy.h @@ -0,0 +1,636 @@ +/** @file
+ PCH policy protocol produced by a platform driver specifying various
+ expected PCH settings. This protocol is consumed by the PCH drivers.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PLATFORM_POLICY_H_
+#define _PCH_PLATFORM_POLICY_H_
+
+//
+#include "PchRegs.h"
+#include "Uefi.h"
+
+extern EFI_GUID gDxePchPlatformPolicyProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL;
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+
+///
+/// Revision 1: Original version
+///
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1
+
+///
+/// Generic definitions for device enabling/disabling used by PCH code.
+///
+#define PCH_DEVICE_ENABLE 1
+#define PCH_DEVICE_DISABLE 0
+
+///
+/// SW SMI values which are used by PCH Platform Policy Protocol
+///
+#define SW_SMI_BIOS_LOCK 0xA9
+#ifdef PCIESC_SUPPORT
+#define SW_SMI_PCIE_ASPM_OVERRIDE 0xAA
+#endif
+
+///
+/// Pnp Mode Definitions
+///
+typedef enum {
+ PchPnpDisabled = 0,
+ PchPnpPower = 1,
+ PchPnpPerformance = 2,
+ PchPnpPowerPerformance = 3,
+ PchPnpModeMax
+} PCH_PNP_MODE;
+
+///
+/// Device Operating Mode
+///
+typedef enum {
+ PchDisabled = 0,
+ PchPciMode = 1,
+ PchAcpiMode = 2,
+ PchDevModeMax
+} PCH_DEV_MODE;
+
+///
+/// Platform Clocks Operating Mode
+///
+typedef enum {
+ PchPltClkDynamic = 0,
+ PchPltClkForceOn = 1,
+ PchPltClkForceOff = 2,
+ PchPltClkMaxMode = 3
+} PCH_PLTCLK_MODE;
+
+///
+/// SCC eMMC Driver Operating Mode
+///
+typedef enum {
+ PchSccEmmcModeAuto = 0,
+ PchSccEmmcMode52MHz = 1,
+ PchSccEmmcMode26MHz = 2,
+ PchSccEmmcModeBasic = 3
+} PCH_SCC_EMMC_MODE;
+
+///
+/// ---------------------------- Device Enabling ------------------------------
+///
+/// PCH Device enablings
+///
+typedef struct {
+ UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto
+ UINT8 Sata : 1; /// 0: Disable; 1: Enable
+ UINT8 Smbus : 1; /// 0: Disable; 1: Enable
+ UINT8 RsvdBits : 4; /// Reserved fields for future expansion w/o protocol change
+ PCH_PLTCLK_MODE PlatformClock[6]; /// 0: Dynamic; 1: Force On; 2: Force Off
+ PCH_DEV_MODE IshEnabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE LpeEnabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+} PCH_DEVICE_ENABLING;
+
+///
+/// ---------------------------- USB Config -----------------------------
+///
+///
+/// Overcurrent pins
+///
+typedef enum {
+ PchUsbOverCurrentPin0 = 0,
+ PchUsbOverCurrentPin1,
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinMax
+} PCH_USB_OVERCURRENT_PIN;
+
+typedef struct {
+ UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled
+ UINT8 Rsvdbits : 7;
+} PCH_USB_PORT_SETTINGS;
+
+typedef struct {
+ PCH_DEV_MODE Enable; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+} PCH_USBOTG_CONTROLLER_SETTINGS;
+
+#define PCH_XHCI_MODE_OFF 0
+#define PCH_XHCI_MODE_ON 1
+
+typedef struct {
+ UINT8 Mode : 1; /// 0: Disable; 1: Enable
+ UINT8 Rsvdbits : 7;
+} PCH_USB30_CONTROLLER_SETTINGS;
+
+typedef struct {
+ UINT8 SsicEnable;
+ PCH_USB_PORT_SETTINGS Usb20PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];
+ PCH_USB_PORT_SETTINGS Usb30PortSettings[PCH_XHCI_MAX_USB3_PORTS];
+ PCH_USB_PORT_SETTINGS HsicPortSettings[PCH_HSIC_MAX_PORTS];
+ PCH_USB_PORT_SETTINGS SsicPortSettings[PCH_SSIC_MAX_PORTS];
+ PCH_USB30_CONTROLLER_SETTINGS Usb30Settings;
+ PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;
+ PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];
+ PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];
+} PCH_USB_CONFIG;
+
+//
+// ---------------------------- PCI Express Config ----------------------
+//
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCI_EXPRESS_ASPM_CONTROL;
+
+///
+/// Refer to PCH EDS for the PCH implementation values corresponding
+/// to below PCI-E spec defined ranges
+///
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_2,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL;
+
+typedef enum {
+ PchPcieCompletionTO_Default,
+ PchPcieCompletionTO_50_100us,
+ PchPcieCompletionTO_1_10ms,
+ PchPcieCompletionTO_16_55ms,
+ PchPcieCompletionTO_65_210ms,
+ PchPcieCompletionTO_260_900ms,
+ PchPcieCompletionTO_1_3P5s,
+ PchPcieCompletionTO_4_13s,
+ PchPcieCompletionTO_17_64s,
+ PchPcieCompletionTO_Disabled
+} PCH_PCIE_COMPLETION_TIMEOUT;
+
+typedef enum {
+ PchPcieOverrideDisabled = 0x00,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03
+} PCH_PCI_EXPRESS_ASPM_OVERRIDE_CONFIG;
+
+typedef struct {
+ UINT8 Enable : 1; ///< Root Port enabling, 0: Disable; 1: Enable.
+ UINT8 Hide : 1; ///< Whether or not to hide the configuration space of this port.
+ UINT8 SlotImplemented : 1; ///< Indicates whether the root port is connected to a slot.
+ UINT8 HotPlug : 1; ///< Indicate whether the root port is hot plug available.
+ UINT8 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled.
+ UINT8 ExtSync : 1; ///< Indicate whether the extended synch is enabled.
+ UINT8 Rsvdbits : 2;
+ //
+ // Error handlings
+ //
+ UINT8 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled.
+ UINT8 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled.
+ UINT8 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled.
+ UINT8 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled.
+ UINT8 PmeInterrupt : 1; ///< Indicate whether the PME Interrupt is enabled.
+ UINT8 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled.
+ UINT8 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled.
+ UINT8 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled.
+
+ UINT8 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled
+ UINT8 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled.
+ UINT8 NonCommonClockSscMode : 1; ///< Indicate whether the root port assumed to be operating in non-common clock mode with SSC enabled.
+ UINT8 Reserved : 5; ///< Reserved fields for future expansion w/o protocol change
+
+ UINT8 FunctionNumber; ///< The function number this root port is mapped to
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port.
+ PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout; ///< The completion timeout configuration of the root port
+ PCH_PCI_EXPRESS_ASPM_CONTROL Aspm; ///< The ASPM configuration of the root port
+ PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1Substates; ///< The L1 Substates configuration of the root port
+ UINT8 TxEqdeEmphSelection; ///< When the Link is operating at 5.0 GT/s speed, select the level of de-emphasis for an Upstream component.
+} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;
+
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm; ///< The override ASPM setting from End point
+ PCH_PCI_EXPRESS_ASPM_OVERRIDE_CONFIG OverrideConfig; ///< The override configuration. e.g. 0x0 means this subset is applicable to L1L2 override only.
+ UINT16 L1SubstatesCapOffset; ///< The L1Substates Capability Offset
+ UINT32 L1SubstatesCapMask; ///< The L1Substates Capability Mask
+} PCH_PCIE_DEVICE_ASPM_OVERRIDE;
+
+#ifdef PCIESC_SUPPORT
+///
+/// The PCH_PCI_EXPRESS_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+///
+typedef struct {
+ ///
+ /// Temp Bus Number range available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempRootPortBusNumMin;
+ ///
+ /// Temp Bus Number range available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempRootPortBusNumMax;
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 NumOfDevAspmOverride; ///< Number of Pci Express card Aspm setting override
+ PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; ///< The Pointer which is point to Pci Express card Aspm setting override
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules.
+ ///
+ UINT8 RootPortClockGating : 1;
+ UINT8 Rsvdbits : 7; ///< Reserved fields for future expansion w/o protocol change
+ //
+ // PCI Express S0ix Config
+ //
+ UINT8 D0S0IxPolicy;
+ UINT8 ClkReqEnable;
+ UINT8 ClkReq;
+ UINT8 LtrLatencyScale;
+ UINT8 LtrLatencyValue;
+} PCH_PCI_EXPRESS_CONFIG;
+#endif
+
+//
+// --------------------------- Power Optimizer Config ------------------------------
+//
+typedef struct {
+ UINT8 LtrEnable :1; ///< Latency Tolerance Reporting Mechanism.
+ UINT8 ObffEnable :1; ///< Pcie end point Optimized Buffer Flush/Fill (OBFF) capability for the root port.
+} PCH_PCIE_PWR_OPT;
+
+typedef struct {
+ UINT16 VendorId; ///< PCI configuration space offset 0
+ UINT16 DeviceId; ///< PCI configuration space offset 2
+ UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings
+/**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+**/
+ UINT16 SnoopLatency;
+/**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+**/
+ UINT16 NonSnoopLatency;
+} PCH_PCIE_DEVICE_LTR_OVERRIDE;
+
+#ifdef SATA_SUPPORT
+
+///
+/// ---------------------------- SATA Config -----------------------------
+///
+typedef enum {
+ PchSataSpeedSupportGen1 = 1,
+ PchSataSpeedSupportGen2,
+ PchSataSpeedSupportGen3
+} PCH_SATA_SPEED_SUPPORT;
+
+typedef struct {
+ UINT8 Enable : 1; /// 0: Disable; 1: Enable
+ UINT8 HotPlug : 1; /// 0: Disable; 1: Enable
+ UINT8 MechSw : 1; /// 0: Disable; 1: Enable
+ UINT8 External : 1; /// 0: Disable; 1: Enable
+ UINT8 DevSlp : 1; /// 0: Disable; 1: Enable DevSlp on the port
+ UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change
+} PCH_SATA_PORT_SETTINGS;
+
+typedef struct {
+ PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS];
+ UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable
+ UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0
+ UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1
+ UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10
+ UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5
+ UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology
+ UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER
+ UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled
+
+ UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
+ UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports
+ UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes
+ UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support
+ /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s (Gen 2); 3h: 6 Gb/s (Gen 3)
+
+ UINT8 Rsvdbits : 1; // Reserved fields for future expansion w/o protocol change
+} PCH_SATA_CONFIG;
+#endif
+
+///
+/// --------------------------- AZALIA Config ------------------------------
+///
+typedef struct {
+ UINT32 VendorDeviceId;
+ UINT16 SubSystemId;
+ UINT8 RevisionId; /// 0xFF applies to all steppings
+ UINT8 FrontPanelSupport;
+ UINT16 NumberOfRearJacks;
+ UINT16 NumberOfFrontJacks;
+} PCH_AZALIA_VERB_TABLE_HEADER;
+
+typedef struct {
+ PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;
+ UINT32 *VerbTableData;
+} PCH_AZALIA_VERB_TABLE;
+
+typedef struct {
+ UINT8 Pme : 1; /// 0: Disable; 1: Enable
+ UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported
+ UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached
+ UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable
+ UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable
+ UINT8 Rsvdbits : 3;
+ UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform
+ PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)
+ UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds
+} PCH_AZALIA_CONFIG;
+
+///
+/// --------------------------- Smbus Config ------------------------------
+///
+typedef struct {
+ UINT8 NumRsvdSmbusAddresses;
+ UINT8 *RsvdSmbusAddressTable;
+} PCH_SMBUS_CONFIG;
+
+///
+/// --------------------------- Miscellaneous PM Config ------------------------------
+///
+typedef struct {
+ UINT8 PmeB0S5Dis : 1;
+ UINT8 Rsvdbits : 7;
+} PCH_WAKE_CONFIG;
+
+typedef enum {
+ PchSlpS360us,
+ PchSlpS31ms,
+ PchSlpS350ms,
+ PchSlpS32s
+} PCH_SLP_S3_MIN_ASSERT;
+
+typedef enum {
+ PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table
+ PchSlpS41s,
+ PchSlpS42s,
+ PchSlpS43s,
+ PchSlpS44s
+} PCH_SLP_S4_MIN_ASSERT;
+
+typedef struct {
+ ///
+ /// Specify Wake Policy
+ ///
+ PCH_WAKE_CONFIG WakeConfig;
+ ///
+ /// SLP_XX Minimum Assertion Width Policy
+ ///
+ PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert;
+ PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert;
+ UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up
+ UINT8 Rsvdbits : 7;
+ UINT8 ConfigureCfioOnSx;
+ UINT8 *CfioTable;
+ UINT8 CfioEntries;
+} PCH_MISC_PM_CONFIG;
+
+///
+/// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----
+///
+typedef struct {
+ UINT16 SubSystemVendorId;
+ UINT16 SubSystemId;
+} PCH_DEFAULT_SVID_SID;
+
+///
+/// --------------------------- Lock Down Config ------------------------------
+///
+typedef struct {
+ UINT8 GlobalSmi : 1;
+ UINT8 BiosInterface : 1;
+ UINT8 RtcLock : 1;
+ UINT8 BiosLock : 1;
+ UINT8 Rsvdbits : 4;
+ UINT8 PchBiosLockSwSmiNumber;
+} PCH_LOCK_DOWN_CONFIG;
+
+//
+// --------------------------- Serial IRQ Config ------------------------------
+//
+typedef enum {
+ PchQuietMode,
+ PchContinuousMode
+} PCH_SIRQ_MODE;
+///
+/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode
+///
+
+typedef struct {
+ BOOLEAN SirqEnable; /// Determines if enable Serial IRQ
+ PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select
+} PCH_LPC_SIRQ_CONFIG;
+
+#ifdef PCIESC_SUPPORT
+///
+/// --------------------------- Power Optimizer Config ------------------------------
+///
+typedef struct {
+ UINT8 NumOfDevLtrOverride; ///< Number of Pci Express card listed in LTR override table
+ PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; ///< Pointer to Pci Express devices LTR override table
+ PCH_PCIE_PWR_OPT PchPwrOptPcie[PCH_PCIE_MAX_ROOT_PORTS]; ///< related configuration for PCIE ports power optimization.
+} PCH_PWR_OPT_CONFIG;
+#endif
+
+///
+/// --------------------- Low Power Input Output Config ------------------------
+///
+typedef struct {
+ PCH_DEV_MODE Dma0Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Dma1Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C0Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C1Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C2Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C3Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C4Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C5Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE I2C6Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Pwm0Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Pwm1Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Hsuart0Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Hsuart1Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Spi1Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Spi2Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE Spi3Enabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+} PCH_LPSS_CONFIG;
+
+///
+/// ----------------------------- SCC Config --------------------------------
+///
+typedef struct {
+ PCH_DEV_MODE eMMCEnabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE SdioEnabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_DEV_MODE SdcardEnabled; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
+ PCH_SCC_EMMC_MODE EmmcDriverMode; /// Determine the operating mode of eMMC driver
+ UINT32 SccEmmcDllTuningRequired : 1; /// Determine if DLL Training is required, set to FALSE if Tuning Data is valid
+ UINT32 SccEmmcRxDllTuningEnabled : 1; /// Determine if Rx DLL Tuning should be enabled
+ UINT32 SccEmmcTxDllTuningEnabled : 1; /// Determine if Tx DLL Tuning should be enabled
+ UINT32 SccEmmcRxDllDataValid : 1; /// Set if Rx DLL Tuning Data Valid
+ UINT32 SccEmmcTxDllDataValid : 1; /// Set if Tx DLL Tuning Data Valid
+ UINT32 SccEmmcRxStrobeDllValue : 7; /// Rx Strobe Delay Line Value
+ UINT32 SccEmmcTxDataDllValue : 7; /// Tx Data Delay Line Value
+ UINT32 RsvdBits : 13;
+} PCH_SCC_CONFIG;
+
+///
+/// ------------ General PCH Platform Policy protocol definition ------------
+///
+struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {
+ ///
+ /// This member specifies the revision of the PCH Policy protocol.
+ /// This field is used to indicate backwards compatible changes to the protocol.
+ /// Platform code that produces this protocol must fill with the correct revision
+ /// value for the PCH reference code to correctly interpret the content of the
+ /// protocol fields.
+ ///
+ UINT8 Revision;
+ ///
+ /// This member describes the desired bus number of the PCH controller.
+ ///
+ UINT8 BusNumber;
+ ///
+ /// This member describes which PCH devices should be enabled or disabled.
+ ///
+ PCH_DEVICE_ENABLING *DeviceEnabling;
+ ///
+ /// This member describes USB controller's related configuration.
+ ///
+ PCH_USB_CONFIG *UsbConfig;
+ ///
+ /// This member describes PCI Express controller's related configuration.
+ ///
+#ifdef PCIESC_SUPPORT
+ PCH_PCI_EXPRESS_CONFIG *PciExpressConfig;
+#endif
+
+ ///
+ /// This member describes SATA controller's related configuration.
+ ///
+#ifdef SATA_SUPPORT
+ PCH_SATA_CONFIG *SataConfig;
+#endif
+ ///
+ /// This member describes the Intel HD Audio (Azalia) related configuration.
+ ///
+ PCH_AZALIA_CONFIG *AzaliaConfig;
+ ///
+ /// This member describes SMBus related configuration.
+ ///
+ PCH_SMBUS_CONFIG *SmbusConfig;
+ ///
+ /// This member describes miscellaneous platform power management configurations.
+ ///
+ PCH_MISC_PM_CONFIG *MiscPmConfig;
+ ///
+ /// This member describes default SVID and Sid for PCH devices.
+ ///
+ PCH_DEFAULT_SVID_SID *DefaultSvidSid;
+ ///
+ /// This member describes LockDown related configuration.
+ ///
+ PCH_LOCK_DOWN_CONFIG *LockDownConfig;
+ ///
+ /// This member describes the expected configuration of the PCH for Serial IRQ.
+ ///
+ PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
+#ifdef PCIESC_SUPPORT
+ ///
+ /// This member describes the Power Optimizer configuration.
+ ///
+ PCH_PWR_OPT_CONFIG *PwrOptConfig;
+ ///
+ /// This member describes the SwSmi value for override PCIe ASPM table.
+ ///
+ UINT8 PchPcieAspmSwSmiNumber;
+#endif
+ ///
+ /// This member describes the Low Power Sub-System related configuration
+ ///
+ PCH_LPSS_CONFIG *LpssConfig;
+ ///
+ /// This member describes the Storage Control Cluster related configuration
+ ///
+ PCH_SCC_CONFIG *SccConfig;
+ ///
+ /// This member describes the PnP Settings related configuration
+ ///
+ PCH_PNP_MODE PnpSettings;
+ ///
+ /// This member describes the S0iX related configuration
+ ///
+ UINT8 S0ixSupport;
+ ///
+ /// This member describes the Hardware Reduced Mode related configuration
+ ///
+ UINT8 AcpiHwRed;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchReset.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..dd036c66ff --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchReset.h @@ -0,0 +1,106 @@ +/** @file
+ PCH Reset Protocol
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_RESET_H_
+#define _PCH_RESET_H_
+
+#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData"
+extern EFI_GUID gEfiCapsuleVendorGuid;
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchResetProtocolGuid;
+extern EFI_GUID gPchResetCallbackProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL;
+
+typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL;
+
+//
+// Related Definitions
+//
+///
+/// PCH Reset Types
+///
+typedef enum {
+ ColdReset,
+ WarmReset,
+ ShutdownReset,
+ PowerCycleReset,
+ GlobalReset,
+ GlobalResetWithEc
+} PCH_RESET_TYPE;
+
+//
+// Member functions
+//
+/**
+ Execute Pch Reset from the host controller.
+
+ @param[in] This Pointer to the PCH_RESET_PROTOCOL instance.
+ @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,
+ PowerCycleReset, GlobalReset, GlobalResetWithEc
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER If ResetType is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET) (
+ IN PCH_RESET_PROTOCOL * This,
+ IN PCH_RESET_TYPE PchResetType
+ );
+
+/**
+ Execute call back function for Pch Reset.
+
+ @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset.
+
+ @retval EFI_SUCCESS The callback function has been done successfully
+ @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of
+ callback protocol is installed.
+ @retval Others Do not do any reset from PCH
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET_CALLBACK) (
+ IN PCH_RESET_TYPE PchResetType
+ );
+
+///
+/// Interface structure for the Pch Reset Protocol
+///
+struct _PCH_RESET_PROTOCOL {
+ PCH_RESET Reset;
+};
+
+///
+/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition
+///
+/// This protocol is used to execute PCH Reset from the host controller.
+/// The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface
+/// for DXE and PEI environments, respectively. If other drivers need to run their
+/// callback function right before issuing the reset, they can install PCH Reset
+/// Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that.
+///
+struct _PCH_RESET_CALLBACK_PROTOCOL {
+ PCH_RESET_CALLBACK ResetCallback;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchSccTuning.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchSccTuning.h new file mode 100644 index 0000000000..d44ee325c7 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/PchSccTuning.h @@ -0,0 +1,74 @@ +/** @file
+ PCH SCC Tuning Protocol
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SCC_TUNING_PROTOCOL_H_
+#define _PCH_SCC_TUNING_PROTOCOL_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define PCH_SCC_TUNING_PROTOCOL_REVISION 1
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSccTuningProtocolGuid;
+
+//
+// Forward declaration for PCH_EMMC_TUNING_PROTOCOL
+//
+typedef struct _PCH_EMMC_TUNING_PROTOCOL PCH_EMMC_TUNING_PROTOCOL;
+///
+/// This structure describes the required Emmc info for HS400 tuning
+///
+typedef struct {
+ EFI_HANDLE PartitionHandle; ///< eMMC partition handle for block read/write
+ EFI_LBA Lba; ///< Logical Block Address for HS400 Tuning block read/write
+ UINT32 RelativeDevAddress; ///< Device system address, dynamically assigned by the host during initialization.
+ UINT8 HS200BusWidth; ///< The value to be programmed for BUS_WIDTH[183] byte
+} EMMC_INFO;
+
+///
+/// This structure describes the return value after DLL tuning
+///
+typedef struct {
+ UINT8 RxDllDataValid; ///< Set if Rx DLL Tuning Data is valid
+ UINT8 TxDllDataValid; ///< Set if Tx DLL Tuning Data is valid
+ UINT8 RxStrobeDllValue; ///< Rx Strobe Delay Line Value
+ UINT8 TxDataDllValue; ///< Tx Data Delay Line value
+} EMMC_TUNING_DATA;
+
+///
+/// EMMC HS200/HS400 TUNING INTERFACE
+///
+
+typedef EFI_STATUS (EFIAPI *EMMC_TUNE) (
+ IN PCH_EMMC_TUNING_PROTOCOL *This, ///< This pointer to PCH_EMMC_TUNING_PROTOCOL
+ //
+ // Revision parameter is used to verify the layout of EMMC_INFO and TUNINGDATA.
+ // If the revision is not matched, means the revision of EMMC_INFO and TUNINGDATA is not matched.
+ // And function will return immediately.
+ //
+ IN UINT8 Revision,
+ IN EMMC_INFO *EmmcInfo, ///< Pointer to EMMC_INFO
+ OUT EMMC_TUNING_DATA *EmmcTuningData ///< Pointer to EMMC_TUNING_DATA
+);
+
+///
+/// PCH EMMC TUNING PROTOCOL INTERFACE
+///
+struct _PCH_EMMC_TUNING_PROTOCOL {
+ EMMC_TUNE EmmcTune; ///< Emmc Hs400 Tuning Interface
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SdHostIo.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SdHostIo.h new file mode 100644 index 0000000000..822dec4add --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SdHostIo.h @@ -0,0 +1,368 @@ +/** @file
+ Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SD_HOST_IO_H
+#define _SD_HOST_IO_H
+
+typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL;
+
+//
+// TODO: Move to Pci22.h
+//
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
+#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
+#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
+
+//
+// TODO: Retire
+//
+#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
+
+//
+// TODO: Do these belong in an Industry Standard include file?
+//
+// MMIO Registers definition for MMC/SDIO controller
+//
+#define MMIO_DMAADR 0x00
+#define MMIO_BLKSZ 0x04
+#define MMIO_BLKCNT 0x06
+#define MMIO_CMDARG 0x08
+#define MMIO_XFRMODE 0x0C
+#define MMIO_SDCMD 0x0E
+#define MMIO_RESP 0x10
+#define MMIO_BUFDATA 0x20
+#define MMIO_PSTATE 0x24
+#define MMIO_HOSTCTL 0x28
+#define MMIO_PWRCTL 0x29
+#define MMIO_BLKGAPCTL 0x2A
+#define MMIO_WAKECTL 0x2B
+#define MMIO_CLKCTL 0x2C
+#define MMIO_TOCTL 0x2E
+#define MMIO_SWRST 0x2F
+#define MMIO_NINTSTS 0x30
+#define MMIO_ERINTSTS 0x32
+#define MMIO_NINTEN 0x34
+#define MMIO_ERINTEN 0x36
+#define MMIO_NINTSIGEN 0x38
+#define MMIO_ERINTSIGEN 0x3A
+#define MMIO_AC12ERRSTS 0x3C
+#define MMIO_HOST_CTL2 0x3E
+#define MMIO_CAP 0x40
+#define MMIO_CAP2 0x44
+#define MMIO_MCCAP 0x48
+#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50
+#define MMIO_FORCEEVENTERRINTSTAT 0x52
+#define MMIO_ADMAERRSTAT 0x54
+#define MMIO_ADMASYSADDR 0x58
+#define MMIO_PRESETVALUE0 0x60
+#define MMIO_PRESETVALUE1 0x64
+#define MMIO_PRESETVALUE2 0x68
+#define MMIO_PRESETVALUE3 0x6C
+#define MMIO_BOOTTIMEOUTCTRL 0x70
+#define MMIO_DEBUGSEL 0x74
+#define MMIO_SHAREDBUS 0xE0
+#define MMIO_SPIINTSUP 0xF0
+#define MMIO_SLTINTSTS 0xFC
+#define MMIO_CTRLRVER 0xFE
+
+typedef enum {
+ ResponseNo = 0,
+ ResponseR1,
+ ResponseR1b,
+ ResponseR2,
+ ResponseR3,
+ ResponseR4,
+ ResponseR5,
+ ResponseR5b,
+ ResponseR6,
+ ResponseR7
+} RESPONSE_TYPE;
+
+typedef enum {
+ NoData = 0,
+ InData,
+ OutData
+} TRANSFER_TYPE;
+
+typedef enum {
+ Reset_Auto = 0,
+ Reset_DAT,
+ Reset_CMD,
+ Reset_DAT_CMD,
+ Reset_All,
+ Reset_HW
+} RESET_TYPE;
+
+typedef enum {
+ SDMA = 0,
+ ADMA2,
+ PIO
+} DMA_MOD;
+
+typedef struct {
+ UINT32 HighSpeedSupport: 1; // High speed supported
+ UINT32 V18Support: 1; // 1.8V supported
+ UINT32 V30Support: 1; // 3.0V supported
+ UINT32 V33Support: 1; // 3.3V supported
+ UINT32 SDR50Support: 1;
+ UINT32 SDR104Support: 1;
+ UINT32 DDR50Support: 1;
+ UINT32 Reserved0: 1;
+ UINT32 BusWidth4: 1; // 4 bit width
+ UINT32 BusWidth8: 1; // 8 bit width
+ UINT32 Reserved1: 6;
+ UINT32 SDMASupport: 1;
+ UINT32 ADMA2Support: 1;
+ UINT32 DmaMode: 2;
+ UINT32 ReTuneTimer: 4;
+ UINT32 ReTuneMode: 2;
+ UINT32 Reserved2: 6;
+ UINT32 BoundarySize;
+} HOST_CAPABILITY;
+
+/**
+ The main function used to send the command to the card inserted into the SD/MMC host
+ slot. It will assemble the arguments to set the command register and wait for the command
+ and transfer completed until timeout. Then it will read the response register to fill
+ the ResponseData.
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] CommandIndex The command index to set the command index field of command register
+ @param[in] Argument Command argument to set the argument field of command register
+ @param[in] DataType TRANSFER_TYPE, indicates no data, data in or data out
+ @param[in] Buffer Contains the data read from / write to the device
+ @param[in] BufferSize The size of the buffer
+ @param[in] ResponseType RESPONSE_TYPE
+ @param[in] TimeOut Time out value in 1 ms unit
+ @param[in] ResponseData Depending on the ResponseType, such as CSD or card status
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_OUT_OF_RESOURCES A resource has run out.
+ @retval EFI_TIMEOUT The timeout time expired.
+ @retval EFI_DEVICE_ERROR The physical device reported an error while attempting the operation
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT16 CommandIndex,
+ IN UINT32 Argument,
+ IN TRANSFER_TYPE DataType,
+ IN UINT8 *Buffer, OPTIONAL
+ IN UINT32 BufferSize,
+ IN RESPONSE_TYPE ResponseType,
+ IN UINT32 TimeOut,
+ OUT UINT32 *ResponseData OPTIONAL
+ );
+
+/**
+ Set max clock frequency of the host, the actual frequency may not be the same
+ as MaxFrequency. It depends on the max frequency the host can support, divider,
+ and host speed mode.
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] MaxFrequency Max frequency in HZ
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_TIMEOUT The timeout time expired.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 MaxFrequency
+ );
+
+/**
+ Set bus width of the host
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] BusWidth Bus width in 1, 4, 8 bits
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 BusWidth
+ );
+
+/**
+ Set voltage which could supported by the host.
+ Support 0(Power off the host), 1.8V, 3.0V, 3.3V
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] Voltage Units in 0.1 V
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 Voltage
+ );
+
+/**
+ Set Host High Speed
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] HighSpeed True for High Speed Mode set, false for normal mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 HighSpeed
+ );
+
+/**
+ Set Host DDR Mode
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] DdrMode True for DDR Mode set, false for normal mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 DdrMode
+ );
+
+/**
+ Set Host SDR Mode
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] DdrMode True for SDR Mode set, false for normal mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 SdrMode
+ );
+
+/**
+ Reset the host
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] ResetAll TRUE to reset all
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_TIMEOUT The timeout time expired.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN RESET_TYPE ResetType
+ );
+
+/**
+ Enable Auto Stop Command
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] Enable TRUE to enable Auto Stop Command
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_TIMEOUT The timeout time expired.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN BOOLEAN Enable
+ );
+
+/**
+ Find whether these is a card inserted into the slot. If so
+ init the host. If not, return EFI_NOT_FOUND.
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_NOT_FOUND The item was not found.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This
+ );
+
+/**
+ Set the Block length
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+ @param[in] BlockLength Card supported block length
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_TIMEOUT The timeout time expired.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (
+ IN EFI_SD_HOST_IO_PROTOCOL *This,
+ IN UINT32 BlockLength
+ );
+
+/**
+ Setup Device for card initialization
+
+ @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)(
+ IN EFI_SD_HOST_IO_PROTOCOL *This
+ );
+
+//
+// Interface structure for the EFI SD Host I/O Protocol
+//
+struct _EFI_SD_HOST_IO_PROTOCOL {
+ UINT32 Revision;
+ HOST_CAPABILITY HostCapability;
+ EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand;
+ EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency;
+ EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth;
+ EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage;
+ EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
+ EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE SetHostSdrMode;
+ EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost;
+ EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
+ EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
+ EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength;
+ EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice;
+ EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode;
+};
+
+extern EFI_GUID gEfiSdHostIoProtocolGuid;
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h new file mode 100644 index 0000000000..3743596976 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h @@ -0,0 +1,148 @@ +/** @file
+ SmmIchnDispatch Extended Protocol
+
+ Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_
+#define _EFI_SMM_ICHN_DISPATCH_EX_H_
+
+#include <Protocol/SmmIchnDispatch.h>
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL;
+
+//
+// Related Definitions
+//
+///
+/// Ichn Dispatch Extended Types
+///
+typedef enum {
+ IchnExPciExpress = NUM_ICHN_TYPES + 1,
+ IchnExMonitor,
+ IchnExSpi,
+ IchnExQRT,
+ IchnExGpioUnlock,
+ IchnExTmrOverflow,
+ IchnExPcie0Hotplug,
+ IchnExPcie1Hotplug,
+ IchnExPcie2Hotplug,
+ IchnExPcie3Hotplug,
+ IchnExPcie0LinkActive,
+ IchnExPcie1LinkActive,
+ IchnExPcie2LinkActive,
+ IchnExPcie3LinkActive,
+ //
+ // INSERT NEW ITEMS JUST BEFORE THIS LINE
+ //
+ IchnExTypeMAX ///< the maximum number of items in this enumeration
+} EFI_SMM_ICHN_EX_SMI_TYPE;
+
+typedef struct {
+ EFI_SMM_ICHN_EX_SMI_TYPE Type;
+} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT;
+
+//
+// Member functions
+//
+
+/**
+ Dispatch function for a ICH n Extended specific SMI handler.
+
+ @param[in] DispatchHandle Handle of this dispatch function.
+ @param[in] DispatchContext Pointer to the dispatch function's context.
+ The DispatchContext fields are filled in
+ by the dispatching driver prior to
+ invoking this dispatch function.
+
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) (
+ IN EFI_HANDLE DispatchHandle,
+ IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext
+ );
+
+/**
+ Register a child SMI source dispatch function with a parent SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param[in] DispatchContext Pointer to the dispatch function's context.
+ The caller fills this context in before calling
+ the register function to indicate to the register
+ function the ICHN SMI source for which the dispatch
+ function should be invoked.
+ @param[out] DispatchHandle Handle of dispatch function, for when interfacing
+ with the parent SMM driver.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this
+ child.
+ @retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value
+ is not within valid range.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) (
+ IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This,
+ IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction,
+ IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext,
+ OUT EFI_HANDLE * DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval Others TBD
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) (
+ IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+///
+/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol
+///
+/// This protocol provides the ability to dispatch function for a ICHn specific SMI.
+/// This protocol acts as an extension to the EFI_SMM_ICHN_DISPATCH_PROTOCOL capabilities
+/// by defining several new SMI types: IchnExPciExpress, IchnExMonitor, IchnExSpi,
+/// IchnExQRT, IchnGpioUnlockSmi, IchnExTmrOverflow, IchnExPcieXHotplug, IchnExPcieXLinkActive.
+///
+struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL {
+ EFI_SMM_ICHN_EX_REGISTER Register; ///< Register a child SMI source dispatch function with a parent SMM driver.
+ EFI_SMM_ICHN_EX_UNREGISTER UnRegister; ///< Un-register a child SMI source dispatch function with a parent SMM driver.
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/Spi.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/Spi.h new file mode 100644 index 0000000000..03878f0065 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/Spi.h @@ -0,0 +1,296 @@ +/** @file
+ This file defines the EFI SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SPI_H_
+#define _EFI_SPI_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiSpiProtocolGuid;
+extern EFI_GUID gEfiSmmSpi2ProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+///
+/// Number of Prefix Opcodes allowed on the SPI interface
+///
+#define SPI_NUM_PREFIX_OPCODE 2
+
+///
+/// Number of Opcodes in the Opcode Menu
+///
+#define SPI_NUM_OPCODE 8
+
+///
+/// Opcode Type
+/// EnumSpiOpcodeCommand: Command without address
+/// EnumSpiOpcodeRead: Read with address
+/// EnumSpiOpcodeWrite: Write with address
+///
+typedef enum {
+ EnumSpiOpcodeReadNoAddr,
+ EnumSpiOpcodeWriteNoAddr,
+ EnumSpiOpcodeRead,
+ EnumSpiOpcodeWrite,
+ EnumSpiOpcodeMax
+} SPI_OPCODE_TYPE;
+
+typedef enum {
+ EnumSpiCycle20MHz,
+ EnumSpiCycle33MHz,
+ EnumSpiCycle66MHz, ///< Not supported by CHV
+ EnumSpiCycle50MHz,
+ EnumSpiCycleMax
+} SPI_CYCLE_FREQUENCY;
+
+typedef enum {
+ EnumSpiRegionAll,
+ EnumSpiRegionBios,
+ EnumSpiRegionSeC,
+ EnumSpiRegionDescriptor,
+ EnumSpiRegionPlatformData,
+ EnumSpiRegionMax
+} SPI_REGION_TYPE;
+
+///
+/// Hardware Sequencing required operations (as listed in the EDS "Hardware
+/// Sequencing Commands and Opcode Requirements"
+///
+typedef enum {
+ EnumSpiOperationWriteStatus,
+ EnumSpiOperationProgramData_1_Byte,
+ EnumSpiOperationProgramData_64_Byte,
+ EnumSpiOperationReadData,
+ EnumSpiOperationWriteDisable,
+ EnumSpiOperationReadStatus,
+ EnumSpiOperationWriteEnable,
+ EnumSpiOperationFastRead,
+ EnumSpiOperationEnableWriteStatus,
+ EnumSpiOperationErase_256_Byte,
+ EnumSpiOperationErase_4K_Byte,
+ EnumSpiOperationErase_8K_Byte,
+ EnumSpiOperationErase_64K_Byte,
+ EnumSpiOperationFullChipErase,
+ EnumSpiOperationJedecId,
+ EnumSpiOperationDualOutputFastRead,
+ EnumSpiOperationDiscoveryParameters,
+ EnumSpiOperationOther,
+ EnumSpiOperationMax
+} SPI_OPERATION;
+
+///
+/// SPI Command Configuration
+///
+typedef struct _SPI_COMMAND_CONFIG {
+ ///
+ /// The expected frequency to be used (value to be programmed to the SSFC Register)
+ ///
+ SPI_CYCLE_FREQUENCY Frequency;
+ ///
+ /// Which Hardware Sequencing required operation this opcode respoinds to.
+ /// The required operations are listed in EDS Table 5-55: "Hardware
+ /// Sequencing Commands and Opcode Requirements"
+ /// If the opcode does not corresponds to any operation listed, use
+ /// EnumSpiOperationOther, and provides TYPE and Code for it in
+ /// SpecialOpcodeEntry.
+ ///
+ SPI_OPERATION Operation;
+} SPI_COMMAND_CONFIG;
+
+///
+/// Special Opcode entries
+///
+typedef struct _SPI_SPECIAL_OPCODE_ENTRY {
+ ///
+ /// Opcode Menu Index whose Opcode Type/Menu Configuration Register need to be
+ /// overrided or programmed per "Type" and "Code". Filled this field with 0xFF
+ /// as the end tag of SpecialOpcodeEntry.
+ ///
+ UINT8 OpcodeIndex;
+ ///
+ /// Operation Type (value to be programmed to the OPTYPE register)
+ ///
+ SPI_OPCODE_TYPE Type;
+ ///
+ /// The opcode (value to be programmed to the OPMENU register)
+ ///
+ UINT8 Code;
+} SPI_SPECIAL_OPCODE_ENTRY;
+
+///
+/// Initialization data table loaded to the SPI host controller
+///
+/// Note: Most of time, the SPI flash parts with the same vendor would have the same
+/// Prefix Opcode, Opcode menu, so you can provide one table for the SPI flash parts with
+/// the same vendor.
+///
+typedef struct _SPI_INIT_DATA {
+ ///
+ /// Prefix opcodes which are loaded into the SPI host controller
+ ///
+ UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];
+ ///
+ /// Determines Opcode Type, Menu and Frequency of the SPI commands
+ ///
+ SPI_COMMAND_CONFIG SpiCmdConfig[SPI_NUM_OPCODE];
+ ///
+ /// Special Opcode entry for the special operations.
+ ///
+ SPI_SPECIAL_OPCODE_ENTRY *SpecialOpcodeEntry;
+ ///
+ /// The offset of the start of the BIOS image relative to the flash device.
+ /// Please note this is a Flash Linear Address, NOT a memory space address.
+ /// This value is platform specific and depends on the system flash map.
+ /// This value is only used on non Descriptor mode.
+ ///
+ UINTN BiosStartOffset;
+ ///
+ /// The the BIOS Image size in flash. This value is platform specific
+ /// and depends on the system flash map. Please note BIOS Image size may
+ /// be smaller than BIOS Region size (in Descriptor Mode) or the flash size
+ /// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be
+ /// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash
+ /// (in Non Descriptor Mode)
+ ///
+ UINTN BiosSize;
+} SPI_INIT_DATA;
+
+//
+// Protocol member functions
+//
+
+/**
+ JEDEC Read IDs from SPI flash part, this function will return 1-byte Vendor ID and 2-byte Device ID
+
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
+ @param[in] Address This value is to determine the command is sent to SPI Component 1 or 2
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Read Jedec Id completed.
+ @retval EFI_DEVICE_ERROR Device error, operation failed.
+ @exception EFI_UNSUPPORTED This function is unsupported after SpiProtocolInit is called
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_READ_ID) (
+ IN EFI_SPI_PROTOCOL * This,
+ IN UINTN Address,
+ IN OUT UINT8 * Buffer
+ );
+
+/**
+ Initializes the host controller to execute SPI commands.
+
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
+ @param[in] InitData Pointer to caller-allocated buffer containing the SPI
+ interface initialization table.
+
+ @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.
+ @retval EFI_ACCESS_DENIED The SPI configuration interface is locked.
+ @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.
+ @retval EFI_DEVICE_ERROR Device error, operation failed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_INIT) (
+ IN EFI_SPI_PROTOCOL * This,
+ IN SPI_INIT_DATA * InitData
+ );
+
+/**
+ Execute SPI commands from the host controller.
+
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
+ @param[in] OpcodeIndex Index of the command in the OpCode Menu.
+ @param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
+ @param[in] DataCycle TRUE if the SPI cycle contains data
+ @param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
+ @param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
+ @param[in] Address In Descriptor Mode, for Descriptor Region, SeC Region and Platform
+ Region, this value specifies the offset from the Region Base; for BIOS Region,
+ this value specifies the offset from the start of the BIOS Image. In Non
+ Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
+ Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
+ Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
+ supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
+ the flash (in Non Descriptor Mode)
+ @param[in] DataByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
+ @param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionMe,
+ EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
+ Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
+ and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
+ to base of the 1st flash device (i.e., it is a Flash Linear Address).
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @exception EFI_UNSUPPORTED Command not supported.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_EXECUTE) (
+ IN EFI_SPI_PROTOCOL * This,
+ IN UINT8 OpcodeIndex,
+ IN UINT8 PrefixOpcodeIndex,
+ IN BOOLEAN DataCycle,
+ IN BOOLEAN Atomic,
+ IN BOOLEAN ShiftOut,
+ IN UINTN Address,
+ IN UINT32 DataByteCount,
+ IN OUT UINT8 *Buffer,
+ IN SPI_REGION_TYPE SpiRegionType
+ );
+
+/**
+ Initializes the host controller to execute SPI commands.
+
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
+ @param[in] InitData Pointer to caller-allocated buffer containing the SPI
+ interface initialization table.
+
+ @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.
+ @retval EFI_ACCESS_DENIED The SPI configuration interface is locked.
+ @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.
+ @retval EFI_DEVICE_ERROR Device error, operation failed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_LOCK) (
+ IN EFI_SPI_PROTOCOL * This
+ );
+
+///
+/// EFI SPI Protocol definition
+///
+/// These protocols/PPI allows a platform module to perform SPI operations through the
+/// Intel PCH SPI Host Controller Interface.
+///
+struct _EFI_SPI_PROTOCOL {
+ EFI_SPI_READ_ID ReadId; ///< JEDEC Read IDs from SPI flash part, this function will return 1-byte Vendor ID and 2-byte Device ID.
+ EFI_SPI_INIT Init; ///< Initialize the host controller to execute SPI commands.
+ EFI_SPI_LOCK Lock;
+ EFI_SPI_EXECUTE Execute; ///< Execute SPI commands from the host controller.
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiAcpi.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiAcpi.h new file mode 100644 index 0000000000..e30402af56 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiAcpi.h @@ -0,0 +1,112 @@ +/** @file
+ SPI Device ACPI Protocol
+
+ This protocol supports the enumerations of device on the SPI bus.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_ACPI_H__
+#define __SPI_ACPI_H__
+
+#include <Protocol/DevicePath.h>
+
+///
+/// SPI ACPI protocol
+///
+typedef struct _EFI_SPI_ACPI_PROTOCOL EFI_SPI_ACPI_PROTOCOL;
+
+typedef struct _SPI_TARGET_SETTINGS {
+UINT32 WireMode;
+UINT32 ChipSelectLine;
+UINT32 ChipSelectPolarity;
+UINT32 SerialClockPolarity;
+UINT32 SerialClockPhase;
+UINT32 DataFrameSize; //supported are 8, 16, 32
+UINT32 ClockSpeed;
+UINT32 LoopbackMode;
+UINT8 BytesPerEntry;
+UINT32 NotDefined; // to be asked to SSG reference in Spi0BusConfig.c mE2PROM_target
+}SPI_TARGET_SETTINGS;
+
+///
+/// SPI device description
+///
+/// This structure provides the platform specific information which
+/// describes an SPI device.
+///
+typedef struct {
+ ///
+ /// Hardware revision - SPI _HRV value
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// Device path node for the SPI device.
+ ///
+ CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ SPI_TARGET_SETTINGS *targetSettings;
+}EFI_SPI_DEVICE;
+
+/**
+ Enumerate the SPI devices
+
+ This routine must be called at or below TPL_NOTIFY.
+
+ This function walks the platform specific data to enumerates the
+ SPI devices on an SPI bus.
+
+ @param[in] This Address of an EFI_SPI_ACPI_PROTOCOL
+ structure.
+ @param[in, out] Device Buffer containing the address of an
+ EFI_SPI_DEVICE structure. Enumeration
+ is started by setting the initial
+ EFI_SPI_DEVICE structure address to NULL.
+ The buffer receives an EFI_SPI_DEVICE
+ structure address for the next SPI device.
+
+ @retval EFI_SUCCESS The platform data for the next device
+ on the SPI bus was returned successfully.
+ @retval EFI_INVALID_PARAMETER NextDevice was NULL
+ @retval EFI_NO_MAPPING PreviousDevice does not point to a valid
+ EFI_SPI_DEVICE structure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_ACPI_ENUMERATE) (
+ IN CONST EFI_SPI_ACPI_PROTOCOL *This,
+ IN OUT CONST EFI_SPI_DEVICE **Device
+ );
+
+///
+/// SPI device description
+///
+/// This structure provides the platform specific information which
+/// describes an SPI device.
+///
+struct _EFI_SPI_ACPI_PROTOCOL {
+ ///
+ /// Walk the platform's list of SPI devices on the bus. This
+ /// routine returns the next SPI device in the platform's list
+ /// for this SPI bus.
+ ///
+ EFI_SPI_ACPI_ENUMERATE Enumerate;
+};
+
+///
+/// Variable containing the GUID for the SPI device enumeration protocol
+///
+extern EFI_GUID gEfiSpiAcpiProtocolGuid;
+
+#endif // __SPI_ACPI_H__
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiBus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiBus.h new file mode 100644 index 0000000000..d946cba07b --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiBus.h @@ -0,0 +1,164 @@ +/** @file
+ SPI bus interface
+
+ This layer provides I/O access to an SPI device.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_BUS_H__
+#define __SPI_BUS_H__
+
+///
+/// SPI bus protocol
+///
+typedef struct _EFI_SPI_BUS_PROTOCOL EFI_SPI_BUS_PROTOCOL;
+
+///
+/// SPI device operation
+///
+/// This structure provides the information necessary for an operation
+/// on an SPI device
+///
+typedef struct {
+ // Number of bytes to read, set to zero for write only operations
+ UINT32 ReadBytes;
+
+ // Number of bytes read after read operation.
+ UINT32 BytesRead;
+
+ // Address of the buffer to receive data from the SPI device. Use NULL
+ // for write only operations. The ReadBuffer must be at least ReadBytes
+ // in length.
+ //
+ UINT8 *ReadBuffer;
+
+ // Number of bytes to send to the SPI device
+ UINT32 WriteBytes;
+
+ // Number of bytes written after write operation.
+ UINT32 BytesWritten;
+
+ //
+ // Address of the buffer containing the data to send to the SPI device.
+ // The WriteBuffer must be at least WriteBytes in length.
+ UINT8 *WriteBuffer;
+
+ ///
+ /// Timeout for the SPI operation in 100 ns units
+ ///
+ UINT32 Timeout;
+ }EFI_SPI_REQUEST_PACKET;
+
+/**
+ Perform an SPI operation on the device
+
+ This routine must be called at or below TPL_NOTIFY. For synchronous
+ requests this routine must be called at or below TPL_CALLBACK.
+
+ N.B. The typical consumers of this API are the third party SPI
+ drivers. Extreme care must be taken by other consumers of this
+ API to prevent confusing the third party SPI drivers due to a
+ state change at the SPI device which the third party SPI drivers
+ did not initiate. SPI platform drivers may use this API within
+ these guidelines.
+
+ This routine queues an operation to the SPI controller for execution
+ on the SPI bus.
+
+ As an upper layer driver writer, the following need to be provided
+ to the platform vendor:
+
+ 1. ACPI CID value or string - this is used to connect the upper layer
+ driver to the device.
+ 2. ChipSelect value to identify the slave devices
+
+ @param[in] This Address of an EFI_I2C_BUS_PROTOCOL
+ Structure
+ @param[in] AcpiId AcpiId to let API know the SPI controller selection
+ @param[in] ChipSelect ChipSelect line for one of the slave devices
+
+ @param[in] Event Event to set for asynchronous operations,
+ NULL for synchronous operations
+ @param[in] RequestPacket Address of an EFI_SPI_REQUEST_PACKET
+ structure describing the SPI operation
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_ABORTED The request did not complete because the driver
+ was shutdown.
+ @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
+ @retval EFI_DEVICE_ERROR There was an SPI error (NACK) during the operation.
+ This could indicate the slave device is not present.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL
+ @retval EFI_NO_RESPONSE The SPI device is not responding to the
+ slave address. EFI_DEVICE_ERROR may also be
+ returned if the controller can not distinguish
+ when the NACK occurred.
+ @retval EFI_NOT_FOUND SPI slave address exceeds maximum address
+ @retval EFI_NOT_READY SPI bus is busy or operation pending, wait for
+ the event and then read status pointed to by
+ the request packet.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI operation
+ @retval EFI_TIMEOUT The transaction did not complete within an internally
+ specified timeout period.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_BUS_START_REQUEST) (
+ IN CONST EFI_SPI_BUS_PROTOCOL *This,
+ IN EFI_EVENT Event OPTIONAL,
+ IN UINT8 ChipSelect,
+ IN EFI_SPI_REQUEST_PACKET *RequestPacket
+ );
+
+///
+/// The SPI bus protocol enables access to a specific device on the SPI bus.
+///
+/// Each SPI device is described as an ACPI node (HID, UID and CID) within the
+/// platform layer. The SPI bus protocol enumerates the SPI devices in the
+/// platform and creates a unique handle and device path for each SPI device.
+///
+/// SPI Chip Select is abstracted to limit operation to the specified SPI device.
+/// The third party providing the SPI device support
+/// provides an ordered list of Chip Select line for the SPI device to the team
+/// building the platform layer. The platform team must preserve the order of the
+/// supplied list. ChipSelect is the number of entries in this list
+
+struct _EFI_SPI_BUS_PROTOCOL {
+
+ EFI_SPI_BUS_START_REQUEST StartRequest;
+
+ ///
+ /// The maximum number of bytes the SPI host controller
+ /// is able to receive from the SPI bus.
+ ///
+ UINT32 MaximumReceiveBytes;
+
+ ///
+ /// The maximum number of bytes the SPI host controller
+ /// is able to send on the SPI bus.
+ ///
+ UINT32 MaximumTransmitBytes;
+
+ ///
+ /// The maximum number of bytes in the SPI bus transaction.
+ ///
+ UINT32 MaximumTotalBytes;
+};
+
+///
+/// GUID for the SPI bus protocol
+///
+extern EFI_GUID gEfiSpiBusProtocolGuid;
+
+#endif // __SPI_BUS_H__
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiHost.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiHost.h new file mode 100644 index 0000000000..2396947f0d --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Protocol/SpiHost.h @@ -0,0 +1,105 @@ +/** @file
+ SPI host interface declaration
+
+ A driver or application uses the SPI host protocol to
+ perform operations on the SPI bus. With the support
+ of the SPI platform driver, access is possible to any
+ device on the SPI bus, even devices behind multiplexers
+ and switches.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_HOST_H__
+#define __SPI_HOST_H__
+
+//#include <Protocol/SpiMaster.h>
+
+#include <Protocol/SpiBus.h>
+/**
+ Declare the forward references
+
+**/
+typedef struct _EFI_SPI_HOST_PROTOCOL EFI_SPI_HOST_PROTOCOL;
+
+/**
+ Queue an SPI operation for execution on the SPI controller.
+
+ @param[in] This Address of an EFI_SPI_HOST_PROTOCOL instance.
+ @param[in] Event Event to set for asynchronous operations,
+ NULL for synchronous operations
+ @param[in] RequestPacket Address of an EFI_SPI_REQUEST_PACKET
+
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER
+ @retval EFI_ABORTED The request did not complete because the driver
+ was shutdown.
+ @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
+ @retval EFI_DEVICE_ERROR There was an SPI error during the operation.
+ This could indicate the slave device is not present.
+ @retval EFI_NO_RESPONSE The SPI device is not responding to the
+ slave address. EFI_DEVICE_ERROR may also be
+ returned if the controller can not distinguish
+ when the NACK occurred.
+ @retval EFI_NOT_FOUND SPI slave address exceeds maximum address
+ @retval EFI_NOT_READY SPI bus is busy or operation pending, wait for
+ the event and then read status pointed to by
+ the request packet.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI operation
+ @retval EFI_TIMEOUT The transaction did not complete within an internally
+ specified timeout period.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_HOST_START_REQUEST) (
+ IN CONST EFI_SPI_HOST_PROTOCOL *This,
+ IN CONST EFI_SPI_DEVICE * SpiDevice,
+ IN EFI_EVENT Event OPTIONAL,
+ IN UINT8 ChipSelect,
+ IN EFI_SPI_REQUEST_PACKET *RequestPacket
+ );
+
+///
+/// Host access to the SPI bus.
+///
+struct _EFI_SPI_HOST_PROTOCOL {
+ ///
+ /// Queue an operation for execution on the SPI bus
+ ///
+ EFI_SPI_HOST_START_REQUEST StartRequest;
+
+ ///
+ /// The maximum number of bytes the SPI host controller
+ /// is able to receive from the SPI bus.
+ ///
+ UINT32 MaximumReceiveBytes;
+
+ ///
+ /// The maximum number of bytes the SPI host controller
+ /// is able to send on the SPI bus.
+ ///
+ UINT32 MaximumTransmitBytes;
+
+ ///
+ /// The maximum number of bytes in the SPI bus transaction.
+ ///
+ UINT32 MaximumTotalBytes;
+};
+
+///
+/// GUID for the EFI_SPI_HOST_PROTOCOL
+///
+extern EFI_GUID gEfiSpiHostProtocolGuid;
+
+#endif // __SPI_HOST_H__
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/SpiAccess.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/SpiAccess.h new file mode 100644 index 0000000000..a7f5682fa8 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/SpiAccess.h @@ -0,0 +1,63 @@ +/** @file:
+ The header of Spi accessed driver.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPI_ACCESS_H_
+#define _SPI_ACCESS_H_
+
+#include <PiDxe.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DriverLib.h>
+#include <Protocol/SpiBus.h>
+
+#define SPI_ACCESS_PROTOCOL_GUID \
+ {0xced4f30b, 0xdc71, 0x405f, 0x83, 0xf, 0x2b, 0x4b, 0xbb, 0x65, 0xba, 0xce}
+
+typedef struct _SPI_ACCESS_PROTOCOL SPI_ACCESS_PROTOCOL;
+
+#define DID_SPI_ID_PREFIX "SPI"
+#define DID_SPI_ID_SUFFIX "\\OEMK"
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DEVICE_READ) (
+ IN UINT8 ControllerId,
+ IN UINT8 ChipSelect,
+ IN OUT UINT8 *ReadBuffer,
+ IN UINT32 BytesCount
+);
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DEVICE_WRITE) (
+ IN UINT8 ControllerId,
+ IN UINT8 ChipSelect,
+ IN UINT8 *WriteBuffer,
+ IN UINT32 BytesCount
+);
+
+typedef struct _SPI_ACCESS_PROTOCOL {
+ SPI_DEVICE_READ ReadRequest;
+ SPI_DEVICE_WRITE WriteRequest;
+} SPI_ACCESS_PROTOCOL;
+
+extern EFI_GUID gEfiSpiAccessProtocolGuid;
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/TianoApi.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/TianoApi.h new file mode 100644 index 0000000000..3634d34764 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/TianoApi.h @@ -0,0 +1,60 @@ +/** @file
+ Tiano intrinsic definitions.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TIANO_API_H_
+#define _TIANO_API_H_
+
+//
+// Pointer to internal runtime function
+//
+#define EFI_INTERNAL_FUNCTION 0x00000002
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_INTERNAL_POINTER 0x00000004
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_IPF_GP_POINTER 0x00000008
+
+#define EFI_TPL_DRIVER 6
+
+//
+// EFI Event Types
+//
+#define EFI_EVENT_TIMER 0x80000000
+#define EFI_EVENT_RUNTIME 0x40000000
+#define EFI_EVENT_RUNTIME_CONTEXT 0x20000000
+
+#define EFI_EVENT_NOTIFY_WAIT 0x00000100
+#define EFI_EVENT_NOTIFY_SIGNAL 0x00000200
+
+#define EFI_EVENT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201
+#define EFI_EVENT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202
+
+#define EFI_EVENT_EFI_SIGNAL_MASK 0x000000FF
+#define EFI_EVENT_EFI_SIGNAL_MAX 4
+
+//
+// Task priority level
+//
+#define EFI_TPL_APPLICATION 4
+#define EFI_TPL_CALLBACK 8
+#define EFI_TPL_NOTIFY 16
+#define EFI_TPL_HIGH_LEVEL 31
+
+#endif
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